[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Ia32 / FspApiEntryT.nasm

;; @file\r
;  Provide FSP API entry points.\r
;\r
; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;;\r
\r
    SECTION .text\r
\r
%include    "SaveRestoreSseNasm.inc"\r
%include    "MicrocodeLoadNasm.inc"\r
\r
;\r
; Following are fixed PCDs\r
;\r
extern   ASM_PFX(PcdGet32 (PcdTemporaryRamBase))\r
extern   ASM_PFX(PcdGet32 (PcdTemporaryRamSize))\r
extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))\r
\r
;\r
; Following functions will be provided in PlatformSecLib\r
;\r
extern ASM_PFX(AsmGetFspBaseAddress)\r
extern ASM_PFX(AsmGetFspInfoHeaderNoStack)\r
;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation\r
extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation\r
extern ASM_PFX(SecCarInit)\r
\r
;\r
; Define the data length that we saved on the stack top\r
;\r
DATA_LEN_OF_PER0         EQU   18h\r
DATA_LEN_OF_MCUD         EQU   18h\r
DATA_LEN_AT_STACK_TOP    EQU   (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r
\r
;\r
; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid\r
;        build error. This needs to be fixed later on.\r
;\r
struc MicrocodeHdr\r
    .MicrocodeHdrVersion:      resd    1\r
    .MicrocodeHdrRevision:     resd    1\r
    .MicrocodeHdrDate:         resd    1\r
    .MicrocodeHdrProcessor:    resd    1\r
    .MicrocodeHdrChecksum:     resd    1\r
    .MicrocodeHdrLoader:       resd    1\r
    .MicrocodeHdrFlags:        resd    1\r
    .MicrocodeHdrDataSize:     resd    1\r
    .MicrocodeHdrTotalSize:    resd    1\r
    .MicrocodeHdrRsvd:         resd    3\r
    .size:\r
endstruc\r
\r
struc ExtSigHdr\r
    .ExtSigHdrCount:          resd    1\r
    .ExtSigHdrChecksum:       resd    1\r
    .ExtSigHdrRsvd:           resd    3\r
    .size:\r
endstruc\r
\r
struc ExtSig\r
    .ExtSigProcessor:         resd    1\r
    .ExtSigFlags:             resd    1\r
    .ExtSigChecksum:          resd    1\r
    .size:\r
endstruc\r
\r
struc LoadMicrocodeParams\r
    ; FSP_UPD_HEADER {\r
    .FspUpdHeader:            resd    8\r
    ; }\r
    ; FSPT_CORE_UPD {\r
    .MicrocodeCodeAddr:       resd    1\r
    .MicrocodeCodeSize:       resd    1\r
    .CodeRegionBase:          resd    1\r
    .CodeRegionSize:          resd    1\r
    ; }\r
    .size:\r
endstruc\r
\r
struc LoadMicrocodeParamsFsp22\r
    ; FSP_UPD_HEADER {\r
    .FspUpdHeaderSignature:   resd    2\r
    .FspUpdHeaderRevision:    resb    1\r
    .FspUpdHeaderReserved:    resb   23\r
    ; }\r
    ; FSPT_ARCH_UPD {\r
    .FsptArchRevision:        resb    1\r
    .FsptArchReserved:        resb    3\r
    .FsptArchUpd:             resd    7\r
    ; }\r
    ; FSPT_CORE_UPD {\r
    .MicrocodeCodeAddr:       resd    1\r
    .MicrocodeCodeSize:       resd    1\r
    .CodeRegionBase:          resd    1\r
    .CodeRegionSize:          resd    1\r
    ; }\r
    .size:\r
endstruc\r
\r
struc LoadMicrocodeParamsFsp24\r
    ; FSP_UPD_HEADER {\r
    .FspUpdHeaderSignature:   resd    2\r
    .FspUpdHeaderRevision:    resb    1\r
    .FspUpdHeaderReserved:    resb   23\r
    ; }\r
    ; FSPT_ARCH2_UPD {\r
    .FsptArchRevision:        resb    1\r
    .FsptArchReserved:        resb    3\r
    .FsptArchLength:          resd    1\r
    .FspDebugHandler          resq    1\r
    .FsptArchUpd:             resd    4\r
    ; }\r
    ; FSPT_CORE_UPD {\r
    .MicrocodeCodeAddr:       resq    1\r
    .MicrocodeCodeSize:       resq    1\r
    .CodeRegionBase:          resq    1\r
    .CodeRegionSize:          resq    1\r
    ; }\r
    .size:\r
endstruc\r
\r
;\r
; Define SSE macros\r
;\r
;\r
;args 1: ReturnAddress  2:MmxRegister\r
;\r
%macro LOAD_MMX_EXT 2\r
  mov     esi, %1\r
  movd    %2, esi              ; save ReturnAddress into MMX\r
%endmacro\r
\r
;\r
;args 1: RoutineLabel  2:MmxRegister\r
;\r
%macro CALL_MMX_EXT  2\r
  mov     esi, %%ReturnAddress\r
  movd    %2, esi              ; save ReturnAddress into MMX\r
  jmp     %1\r
%%ReturnAddress:\r
%endmacro\r
\r
;\r
;arg 1:MmxRegister\r
;\r
%macro RET_ESI_EXT   1\r
  movd    esi, %1              ; move ReturnAddress from MMX to ESI\r
  jmp     esi\r
%endmacro\r
\r
;\r
;arg 1:RoutineLabel\r
;\r
%macro CALL_MMX   1\r
         CALL_MMX_EXT  %1, mm7\r
%endmacro\r
\r
%macro RET_ESI 0\r
         RET_ESI_EXT   mm7\r
%endmacro\r
\r
%macro CALL_EDI  1\r
\r
  mov     edi,  %%ReturnAddress\r
  jmp     %1\r
%%ReturnAddress:\r
\r
%endmacro\r
\r
%macro CALL_EBP 1\r
  mov     ebp, %%ReturnAddress\r
  jmp     %1\r
%%ReturnAddress:\r
%endmacro\r
\r
%macro RET_EBP 0\r
  jmp     ebp                           ; restore EIP from EBP\r
%endmacro\r
\r
;\r
; Load UPD region pointer in ECX\r
;\r
global ASM_PFX(LoadUpdPointerToECX)\r
ASM_PFX(LoadUpdPointerToECX):\r
  ;\r
  ; esp + 4 is input UPD parameter\r
  ; If esp + 4 is NULL the default UPD should be used\r
  ; ecx will be the UPD region that should be used\r
  ;\r
  mov       ecx, dword [esp + 4]\r
  cmp       ecx, 0\r
  jnz       ParamValid\r
\r
  ;\r
  ; Fall back to default UPD region\r
  ;\r
  CALL_EDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)\r
  mov       ecx, DWORD [eax + 01Ch]      ; Read FsptImageBaseAddress\r
  add       ecx, DWORD [eax + 024h]      ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset\r
ParamValid:\r
  RET_EBP\r
\r
;\r
; @todo: The strong/weak implementation does not work.\r
;        This needs to be reviewed later.\r
;\r
;------------------------------------------------------------------------------\r
;\r
;;global ASM_PFX(SecPlatformInitDefault)\r
;ASM_PFX(SecPlatformInitDefault):\r
;   ; Inputs:\r
;   ;   mm7 -> Return address\r
;   ; Outputs:\r
;   ;   eax -> 0 - Successful, Non-zero - Failed.\r
;   ; Register Usage:\r
;   ;   eax is cleared and ebp is used for return address.\r
;   ;   All others reserved.\r
;\r
;   ; Save return address to EBP\r
;   movd  ebp, mm7\r
;\r
;   xor   eax, eax\r
;Exit1:\r
;   jmp   ebp\r
\r
;------------------------------------------------------------------------------\r
global ASM_PFX(LoadMicrocodeDefault)\r
ASM_PFX(LoadMicrocodeDefault):\r
   ; Inputs:\r
   ;   ecx -> UPD region contains LoadMicrocodeParams pointer\r
   ; Register Usage:\r
   ;   All are destroyed\r
   ; Assumptions:\r
   ;   No memory available, stack is hard-coded and used for return address\r
   ;   Executed by SBSP and NBSP\r
   ;   Beginning of microcode update region starts on paragraph boundary\r
\r
   ;\r
   ; Save return address to EBP\r
   ;\r
   movd   ebp, mm7\r
\r
   mov    esp, ecx  ; ECX has been assigned to UPD region\r
   cmp    esp, 0\r
   jz     ParamError\r
\r
   ; skip loading Microcode if the MicrocodeCodeSize is zero\r
   ; and report error if size is less than 2k\r
   ; first check UPD header revision\r
   cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
   jb     Fsp20UpdHeader\r
   cmp    byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
   je     Fsp24UpdHeader\r
   jmp    Fsp22UpdHeader\r
\r
Fsp20UpdHeader:\r
   ; UPD structure is compliant with FSP spec 2.0/2.1\r
   mov    eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
   cmp    eax, 0\r
   jz     Exit2\r
   cmp    eax, 0800h\r
   jl     ParamError\r
\r
   mov    esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
   cmp    esi, 0\r
   jnz    CheckMainHeader\r
   jmp    ParamError\r
\r
Fsp22UpdHeader:\r
   ; UPD structure is compliant with FSP spec 2.2\r
   mov    eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
   cmp    eax, 0\r
   jz     Exit2\r
   cmp    eax, 0800h\r
   jl     ParamError\r
\r
   mov    esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
   cmp    esi, 0\r
   jnz    CheckMainHeader\r
   jmp    ParamError\r
\r
Fsp24UpdHeader:\r
   ; UPD structure is compliant with FSP spec 2.4\r
   mov    eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
   cmp    eax, 0\r
   jz     Exit2\r
   cmp    eax, 0800h\r
   jl     ParamError\r
\r
   mov    esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
   cmp    esi, 0\r
   jnz    CheckMainHeader\r
\r
ParamError:\r
   mov    eax, 080000002h\r
   jmp    Exit2\r
\r
CheckMainHeader:\r
   ; Get processor signature and platform ID from the installed processor\r
   ; and save into registers for later use\r
   ; ebx = processor signature\r
   ; edx = platform ID\r
   mov   eax, 1\r
   cpuid\r
   mov   ebx, eax\r
   mov   ecx, MSR_IA32_PLATFORM_ID\r
   rdmsr\r
   mov   ecx, edx\r
   shr   ecx, 50-32                          ; shift (50d-32d=18d=0x12) bits\r
   and   ecx, 7h                             ; platform id at bit[52..50]\r
   mov   edx, 1\r
   shl   edx, cl\r
\r
   ; Current register usage\r
   ; esp -> stack with parameters\r
   ; esi -> microcode update to check\r
   ; ebx = processor signature\r
   ; edx = platform ID\r
\r
   ; Check for valid microcode header\r
   ; Minimal test checking for header version and loader version as 1\r
   mov   eax, dword 1\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax\r
   jne   AdvanceFixedSize\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax\r
   jne   AdvanceFixedSize\r
\r
   ; Check if signature and plaform ID match\r
   cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]\r
   jne   LoadMicrocodeDefault1\r
   test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]\r
   jnz   LoadCheck  ; Jif signature and platform ID match\r
\r
LoadMicrocodeDefault1:\r
   ; Check if extended header exists\r
   ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r
   xor   eax, eax\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r
   je    NextMicrocode\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax\r
   je    NextMicrocode\r
\r
   ; Then verify total size - sizeof header > data size\r
   mov   ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r
   sub   ecx, MicrocodeHdr.size\r
   cmp   ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r
   jng   NextMicrocode    ; Jif extended header does not exist\r
\r
   ; Set edi -> extended header\r
   mov   edi, esi\r
   add   edi, MicrocodeHdr.size\r
   add   edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r
\r
   ; Get count of extended structures\r
   mov   ecx, dword [edi + ExtSigHdr.ExtSigHdrCount]\r
\r
   ; Move pointer to first signature structure\r
   add   edi, ExtSigHdr.size\r
\r
CheckExtSig:\r
   ; Check if extended signature and platform ID match\r
   cmp   dword [edi + ExtSig.ExtSigProcessor], ebx\r
   jne   LoadMicrocodeDefault2\r
   test  dword [edi + ExtSig.ExtSigFlags], edx\r
   jnz   LoadCheck      ; Jif signature and platform ID match\r
LoadMicrocodeDefault2:\r
   ; Check if any more extended signatures exist\r
   add   edi, ExtSig.size\r
   loop  CheckExtSig\r
\r
NextMicrocode:\r
   ; Advance just after end of this microcode\r
   xor   eax, eax\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r
   je    LoadMicrocodeDefault3\r
   add   esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r
   jmp   CheckAddress\r
LoadMicrocodeDefault3:\r
   add   esi, dword  2048\r
   jmp   CheckAddress\r
\r
AdvanceFixedSize:\r
   ; Advance by 4X dwords\r
   add   esi, dword  1024\r
\r
CheckAddress:\r
   ; Check UPD header revision\r
   cmp   byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
   jb     Fsp20UpdHeader1\r
   cmp    byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
   je     Fsp24UpdHeader1;\r
   jmp    Fsp22UpdHeader1\r
\r
Fsp20UpdHeader1:\r
   ; UPD structure is compliant with FSP spec 2.0/2.1\r
   ; Is automatic size detection ?\r
   mov   eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
   cmp   eax, 0ffffffffh\r
   jz    LoadMicrocodeDefault4\r
\r
   ; Address >= microcode region address + microcode region size?\r
   add   eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
   cmp   esi, eax\r
   jae   Done        ;Jif address is outside of microcode region\r
   jmp   CheckMainHeader\r
\r
Fsp22UpdHeader1:\r
   ; UPD structure is compliant with FSP spec 2.2\r
   ; Is automatic size detection ?\r
   mov   eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
   cmp   eax, 0ffffffffh\r
   jz    LoadMicrocodeDefault4\r
\r
   ; Address >= microcode region address + microcode region size?\r
   add   eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
   cmp   esi, eax\r
   jae   Done        ;Jif address is outside of microcode region\r
   jmp   CheckMainHeader\r
\r
Fsp24UpdHeader1:\r
   ; UPD structure is compliant with FSP spec 2.4\r
   ; Is automatic size detection ?\r
   mov   eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
   cmp   eax, 0ffffffffh\r
   jz    LoadMicrocodeDefault4\r
\r
   ; Address >= microcode region address + microcode region size?\r
   add   eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
   cmp   esi, eax\r
   jae   Done        ;Jif address is outside of microcode region\r
   jmp   CheckMainHeader\r
\r
LoadMicrocodeDefault4:\r
   ; Is valid Microcode start point ?\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
   jz    Done\r
\r
LoadCheck:\r
   ; Get the revision of the current microcode update loaded\r
   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
   xor   eax, eax               ; Clear EAX\r
   xor   edx, edx               ; Clear EDX\r
   wrmsr                        ; Load 0 to MSR at 8Bh\r
\r
   mov   eax, 1\r
   cpuid\r
   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
   rdmsr                        ; Get current microcode signature\r
\r
   ; Verify this microcode update is not already loaded\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r
   je    Continue\r
\r
LoadMicrocode:\r
   ; EAX contains the linear address of the start of the Update Data\r
   ; EDX contains zero\r
   ; ECX contains 79h (IA32_BIOS_UPDT_TRIG)\r
   ; Start microcode load with wrmsr\r
   mov   eax, esi\r
   add   eax, MicrocodeHdr.size\r
   xor   edx, edx\r
   mov   ecx, MSR_IA32_BIOS_UPDT_TRIG\r
   wrmsr\r
   mov   eax, 1\r
   cpuid\r
\r
Continue:\r
   jmp   NextMicrocode\r
\r
Done:\r
   mov   eax, 1\r
   cpuid\r
   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
   rdmsr                         ; Get current microcode signature\r
   xor   eax, eax\r
   cmp   edx, 0\r
   jnz   Exit2\r
   mov   eax, 08000000Eh\r
\r
Exit2:\r
   jmp   ebp\r
\r
;\r
; EstablishStackFsp: EDI should be preserved cross this function\r
;\r
global ASM_PFX(EstablishStackFsp)\r
ASM_PFX(EstablishStackFsp):\r
  ;\r
  ; Save parameter pointer in edx\r
  ;\r
  mov       edx, ecx   ; ECX has been assigned to UPD region\r
\r
  ;\r
  ; Enable FSP STACK\r
  ;\r
  mov       esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r
  add       esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r
\r
  push      DATA_LEN_OF_MCUD     ; Size of the data region\r
  push      4455434Dh            ; Signature of the  data region 'MCUD'\r
\r
  ; check UPD structure revision (edx + 8)\r
  cmp       byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
  jb        Fsp20UpdHeader2\r
  cmp       byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
  je        Fsp24UpdHeader2\r
  jmp       Fsp22UpdHeader2\r
\r
Fsp20UpdHeader2:\r
  ; UPD structure is compliant with FSP spec 2.0/2.1\r
  push      dword [edx + LoadMicrocodeParams.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
  push      dword [edx + LoadMicrocodeParams.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
  push      dword [edx + LoadMicrocodeParams.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
  push      dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
  jmp       ContinueAfterUpdPush\r
\r
Fsp22UpdHeader2:\r
  ; UPD structure is compliant with FSP spec 2.2\r
  push      dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
  push      dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
  push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
  push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
  jmp       ContinueAfterUpdPush\r
\r
Fsp24UpdHeader2:\r
  ; UPD structure is compliant with FSP spec 2.4\r
  push      dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 24\r
  push      dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 16\r
  push      dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 8\r
  push      dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
\r
ContinueAfterUpdPush:\r
  ;\r
  ; Save API entry/exit timestamp into stack\r
  ;\r
  push      DATA_LEN_OF_PER0     ; Size of the data region\r
  push      30524550h            ; Signature of the  data region 'PER0'\r
  rdtsc\r
  push      edx\r
  push      eax\r
  LOAD_EDX\r
  push      edx\r
  LOAD_EAX\r
  push      eax\r
\r
  ;\r
  ; Terminator for the data on stack\r
  ;\r
  push      0\r
\r
  ;\r
  ; Set ECX/EDX to the BootLoader temporary memory range\r
  ;\r
  mov       ecx,  [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r
  mov       edx, ecx\r
  add       edx,  [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r
  sub       edx,  [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]\r
\r
  cmp       ecx, edx        ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.\r
  jb        EstablishStackFspSuccess\r
  mov       eax, 80000003h  ;EFI_UNSUPPORTED\r
  jmp       EstablishStackFspExit\r
EstablishStackFspSuccess:\r
  xor       eax, eax\r
\r
EstablishStackFspExit:\r
  RET_ESI\r
\r
;----------------------------------------------------------------------------\r
; TempRamInit API\r
;\r
; This FSP API will load the microcode update, enable code caching for the\r
; region specified by the boot loader and also setup a temporary stack to be\r
; used till main memory is initialized.\r
;\r
;----------------------------------------------------------------------------\r
global ASM_PFX(TempRamInitApi)\r
ASM_PFX(TempRamInitApi):\r
  ;\r
  ; Ensure SSE is enabled\r
  ;\r
  ENABLE_SSE\r
\r
  ;\r
  ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6\r
  ;\r
  SAVE_REGS\r
\r
  ;\r
  ; Save timestamp into XMM6\r
  ;\r
  rdtsc\r
  SAVE_EAX\r
  SAVE_EDX\r
\r
  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param\r
  SAVE_ECX                               ; save UPD param to slot 3 in xmm6\r
\r
  ;\r
  ; Sec Platform Init\r
  ;\r
  CALL_MMX  ASM_PFX(SecPlatformInit)\r
  cmp       eax, 0\r
  jnz       TempRamInitExit\r
\r
  ; Load microcode\r
  LOAD_ESP\r
  LOAD_ECX\r
  CALL_MMX  ASM_PFX(LoadMicrocodeDefault)\r
  SAVE_UCODE_STATUS                 ; Save microcode return status in slot 1 in xmm5.\r
  ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r
\r
  ; Call Sec CAR Init\r
  LOAD_ESP\r
  LOAD_ECX\r
  CALL_MMX  ASM_PFX(SecCarInit)\r
  cmp       eax, 0\r
  jnz       TempRamInitExit\r
\r
  LOAD_ESP\r
  LOAD_ECX\r
  mov       edi, ecx                ; Save UPD param to EDI for later code use\r
  CALL_MMX  ASM_PFX(EstablishStackFsp)\r
  cmp       eax, 0\r
  jnz       TempRamInitExit\r
\r
  LOAD_UCODE_STATUS                 ; Restore microcode status if no CAR init error from slot 1 in xmm5.\r
\r
TempRamInitExit:\r
  mov       bl, al                  ; save al data in bl\r
  mov       al, 07Fh                ; API exit postcode 7f\r
  out       080h, al\r
  mov       al, bl                  ; restore al data from bl\r
\r
  ;\r
  ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r
  ;\r
  LOAD_REGS\r
  ret\r
\r
;----------------------------------------------------------------------------\r
; Module Entrypoint API\r
;----------------------------------------------------------------------------\r
global ASM_PFX(_ModuleEntryPoint)\r
ASM_PFX(_ModuleEntryPoint):\r
  jmp $\r
Commit	Line	Data
cf1d4549 JY	1	;; @file\r
	2	; Provide FSP API entry points.\r
	3	;\r
6f219bef	4	; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
9672cd30	5	; SPDX-License-Identifier: BSD-2-Clause-Patent\r
cf1d4549 JY	6	;;\r
	7	\r
	8	SECTION .text\r
	9	\r
	10	%include "SaveRestoreSseNasm.inc"\r
	11	%include "MicrocodeLoadNasm.inc"\r
	12	\r
	13	;\r
	14	; Following are fixed PCDs\r
	15	;\r
	16	extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))\r
	17	extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))\r
	18	extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))\r
	19	\r
	20	;\r
	21	; Following functions will be provided in PlatformSecLib\r
	22	;\r
	23	extern ASM_PFX(AsmGetFspBaseAddress)\r
b84f32ae	24	extern ASM_PFX(AsmGetFspInfoHeaderNoStack)\r
cf1d4549 JY	25	;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation\r
	26	extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation\r
	27	extern ASM_PFX(SecCarInit)\r
	28	\r
	29	;\r
	30	; Define the data length that we saved on the stack top\r
	31	;\r
	32	DATA_LEN_OF_PER0 EQU 18h\r
	33	DATA_LEN_OF_MCUD EQU 18h\r
	34	DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r
	35	\r
	36	;\r
	37	; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid\r
	38	; build error. This needs to be fixed later on.\r
	39	;\r
	40	struc MicrocodeHdr\r
	41	.MicrocodeHdrVersion: resd 1\r
	42	.MicrocodeHdrRevision: resd 1\r
	43	.MicrocodeHdrDate: resd 1\r
	44	.MicrocodeHdrProcessor: resd 1\r
	45	.MicrocodeHdrChecksum: resd 1\r
	46	.MicrocodeHdrLoader: resd 1\r
	47	.MicrocodeHdrFlags: resd 1\r
	48	.MicrocodeHdrDataSize: resd 1\r
	49	.MicrocodeHdrTotalSize: resd 1\r
	50	.MicrocodeHdrRsvd: resd 3\r
	51	.size:\r
	52	endstruc\r
	53	\r
	54	struc ExtSigHdr\r
	55	.ExtSigHdrCount: resd 1\r
	56	.ExtSigHdrChecksum: resd 1\r
	57	.ExtSigHdrRsvd: resd 3\r
	58	.size:\r
	59	endstruc\r
	60	\r
	61	struc ExtSig\r
	62	.ExtSigProcessor: resd 1\r
	63	.ExtSigFlags: resd 1\r
	64	.ExtSigChecksum: resd 1\r
	65	.size:\r
	66	endstruc\r
	67	\r
	68	struc LoadMicrocodeParams\r
	69	; FSP_UPD_HEADER {\r
	70	.FspUpdHeader: resd 8\r
	71	; }\r
	72	; FSPT_CORE_UPD {\r
	73	.MicrocodeCodeAddr: resd 1\r
	74	.MicrocodeCodeSize: resd 1\r
	75	.CodeRegionBase: resd 1\r
	76	.CodeRegionSize: resd 1\r
	77	; }\r
	78	.size:\r
	79	endstruc\r
	80	\r
89f569ae CC	81	struc LoadMicrocodeParamsFsp22\r
	82	; FSP_UPD_HEADER {\r
	83	.FspUpdHeaderSignature: resd 2\r
	84	.FspUpdHeaderRevision: resb 1\r
	85	.FspUpdHeaderReserved: resb 23\r
	86	; }\r
6f219bef TK	87	; FSPT_ARCH_UPD {\r
	88	.FsptArchRevision: resb 1\r
	89	.FsptArchReserved: resb 3\r
	90	.FsptArchUpd: resd 7\r
89f569ae CC	91	; }\r
	92	; FSPT_CORE_UPD {\r
	93	.MicrocodeCodeAddr: resd 1\r
	94	.MicrocodeCodeSize: resd 1\r
	95	.CodeRegionBase: resd 1\r
	96	.CodeRegionSize: resd 1\r
	97	; }\r
	98	.size:\r
	99	endstruc\r
cf1d4549	100	\r
6f219bef TK	101	struc LoadMicrocodeParamsFsp24\r
	102	; FSP_UPD_HEADER {\r
	103	.FspUpdHeaderSignature: resd 2\r
	104	.FspUpdHeaderRevision: resb 1\r
	105	.FspUpdHeaderReserved: resb 23\r
	106	; }\r
	107	; FSPT_ARCH2_UPD {\r
	108	.FsptArchRevision: resb 1\r
	109	.FsptArchReserved: resb 3\r
	110	.FsptArchLength: resd 1\r
	111	.FspDebugHandler resq 1\r
	112	.FsptArchUpd: resd 4\r
	113	; }\r
	114	; FSPT_CORE_UPD {\r
	115	.MicrocodeCodeAddr: resq 1\r
	116	.MicrocodeCodeSize: resq 1\r
	117	.CodeRegionBase: resq 1\r
	118	.CodeRegionSize: resq 1\r
	119	; }\r
	120	.size:\r
	121	endstruc\r
	122	\r
cf1d4549 JY	123	;\r
	124	; Define SSE macros\r
	125	;\r
	126	;\r
	127	;args 1: ReturnAddress 2:MmxRegister\r
	128	;\r
	129	%macro LOAD_MMX_EXT 2\r
	130	mov esi, %1\r
	131	movd %2, esi ; save ReturnAddress into MMX\r
	132	%endmacro\r
	133	\r
	134	;\r
	135	;args 1: RoutineLabel 2:MmxRegister\r
	136	;\r
	137	%macro CALL_MMX_EXT 2\r
	138	mov esi, %%ReturnAddress\r
	139	movd %2, esi ; save ReturnAddress into MMX\r
	140	jmp %1\r
	141	%%ReturnAddress:\r
	142	%endmacro\r
	143	\r
	144	;\r
	145	;arg 1:MmxRegister\r
	146	;\r
	147	%macro RET_ESI_EXT 1\r
	148	movd esi, %1 ; move ReturnAddress from MMX to ESI\r
	149	jmp esi\r
	150	%endmacro\r
	151	\r
	152	;\r
	153	;arg 1:RoutineLabel\r
	154	;\r
	155	%macro CALL_MMX 1\r
	156	CALL_MMX_EXT %1, mm7\r
	157	%endmacro\r
	158	\r
	159	%macro RET_ESI 0\r
	160	RET_ESI_EXT mm7\r
	161	%endmacro\r
	162	\r
b84f32ae CC	163	%macro CALL_EDI 1\r
	164	\r
	165	mov edi, %%ReturnAddress\r
	166	jmp %1\r
	167	%%ReturnAddress:\r
	168	\r
	169	%endmacro\r
	170	\r
	171	%macro CALL_EBP 1\r
	172	mov ebp, %%ReturnAddress\r
	173	jmp %1\r
	174	%%ReturnAddress:\r
	175	%endmacro\r
	176	\r
	177	%macro RET_EBP 0\r
	178	jmp ebp ; restore EIP from EBP\r
	179	%endmacro\r
	180	\r
	181	;\r
	182	; Load UPD region pointer in ECX\r
	183	;\r
	184	global ASM_PFX(LoadUpdPointerToECX)\r
	185	ASM_PFX(LoadUpdPointerToECX):\r
	186	;\r
	187	; esp + 4 is input UPD parameter\r
	188	; If esp + 4 is NULL the default UPD should be used\r
	189	; ecx will be the UPD region that should be used\r
	190	;\r
	191	mov ecx, dword [esp + 4]\r
	192	cmp ecx, 0\r
	193	jnz ParamValid\r
	194	\r
	195	;\r
	196	; Fall back to default UPD region\r
	197	;\r
	198	CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack)\r
	199	mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress\r
	200	add ecx, DWORD [eax + 024h] ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset\r
	201	ParamValid:\r
	202	RET_EBP\r
	203	\r
cf1d4549 JY	204	;\r
	205	; @todo: The strong/weak implementation does not work.\r
	206	; This needs to be reviewed later.\r
	207	;\r
	208	;------------------------------------------------------------------------------\r
	209	;\r
	210	;;global ASM_PFX(SecPlatformInitDefault)\r
	211	;ASM_PFX(SecPlatformInitDefault):\r
	212	; ; Inputs:\r
	213	; ; mm7 -> Return address\r
	214	; ; Outputs:\r
	215	; ; eax -> 0 - Successful, Non-zero - Failed.\r
	216	; ; Register Usage:\r
	217	; ; eax is cleared and ebp is used for return address.\r
	218	; ; All others reserved.\r
	219	;\r
	220	; ; Save return address to EBP\r
	221	; movd ebp, mm7\r
	222	;\r
	223	; xor eax, eax\r
	224	;Exit1:\r
	225	; jmp ebp\r
	226	\r
	227	;------------------------------------------------------------------------------\r
	228	global ASM_PFX(LoadMicrocodeDefault)\r
	229	ASM_PFX(LoadMicrocodeDefault):\r
	230	; Inputs:\r
b84f32ae	231	; ecx -> UPD region contains LoadMicrocodeParams pointer\r
cf1d4549	232	; Register Usage:\r
b84f32ae	233	; All are destroyed\r
cf1d4549 JY	234	; Assumptions:\r
	235	; No memory available, stack is hard-coded and used for return address\r
	236	; Executed by SBSP and NBSP\r
	237	; Beginning of microcode update region starts on paragraph boundary\r
	238	\r
cf1d4549 JY	239	;\r
cf1d4549 JY	240	; Save return address to EBP\r
6f219bef	241	;\r
cf1d4549 JY	242	movd ebp, mm7\r
cf1d4549 JY	243	\r
b84f32ae	244	mov esp, ecx ; ECX has been assigned to UPD region\r
cf1d4549 JY	245	cmp esp, 0\r
cf1d4549 JY	246	jz ParamError\r
4c53eb72 YS	247	\r
	248	; skip loading Microcode if the MicrocodeCodeSize is zero\r
	249	; and report error if size is less than 2k\r
89f569ae CC	250	; first check UPD header revision\r
89f569ae CC	251	cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
6f219bef TK	252	jb Fsp20UpdHeader\r
	253	cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
	254	je Fsp24UpdHeader\r
	255	jmp Fsp22UpdHeader\r
89f569ae	256	\r
6f219bef	257	Fsp20UpdHeader:\r
89f569ae	258	; UPD structure is compliant with FSP spec 2.0/2.1\r
4c53eb72 YS	259	mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
	260	cmp eax, 0\r
	261	jz Exit2\r
	262	cmp eax, 0800h\r
	263	jl ParamError\r
	264	\r
cf1d4549 JY	265	mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
	266	cmp esi, 0\r
	267	jnz CheckMainHeader\r
89f569ae CC	268	jmp ParamError\r
	269	\r
	270	Fsp22UpdHeader:\r
	271	; UPD structure is compliant with FSP spec 2.2\r
	272	mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
	273	cmp eax, 0\r
	274	jz Exit2\r
	275	cmp eax, 0800h\r
	276	jl ParamError\r
	277	\r
	278	mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
	279	cmp esi, 0\r
	280	jnz CheckMainHeader\r
6f219bef TK	281	jmp ParamError\r
	282	\r
	283	Fsp24UpdHeader:\r
	284	; UPD structure is compliant with FSP spec 2.4\r
	285	mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
	286	cmp eax, 0\r
	287	jz Exit2\r
	288	cmp eax, 0800h\r
	289	jl ParamError\r
	290	\r
	291	mov esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
	292	cmp esi, 0\r
	293	jnz CheckMainHeader\r
cf1d4549 JY	294	\r
	295	ParamError:\r
	296	mov eax, 080000002h\r
	297	jmp Exit2\r
	298	\r
	299	CheckMainHeader:\r
	300	; Get processor signature and platform ID from the installed processor\r
	301	; and save into registers for later use\r
	302	; ebx = processor signature\r
	303	; edx = platform ID\r
	304	mov eax, 1\r
	305	cpuid\r
	306	mov ebx, eax\r
	307	mov ecx, MSR_IA32_PLATFORM_ID\r
	308	rdmsr\r
	309	mov ecx, edx\r
	310	shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits\r
	311	and ecx, 7h ; platform id at bit[52..50]\r
	312	mov edx, 1\r
	313	shl edx, cl\r
	314	\r
	315	; Current register usage\r
	316	; esp -> stack with parameters\r
	317	; esi -> microcode update to check\r
	318	; ebx = processor signature\r
	319	; edx = platform ID\r
	320	\r
	321	; Check for valid microcode header\r
	322	; Minimal test checking for header version and loader version as 1\r
	323	mov eax, dword 1\r
	324	cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax\r
	325	jne AdvanceFixedSize\r
	326	cmp dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax\r
	327	jne AdvanceFixedSize\r
	328	\r
	329	; Check if signature and plaform ID match\r
	330	cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]\r
	331	jne LoadMicrocodeDefault1\r
	332	test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]\r
	333	jnz LoadCheck ; Jif signature and platform ID match\r
	334	\r
	335	LoadMicrocodeDefault1:\r
	336	; Check if extended header exists\r
	337	; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r
	338	xor eax, eax\r
	339	cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r
	340	je NextMicrocode\r
	341	cmp dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax\r
	342	je NextMicrocode\r
	343	\r
	344	; Then verify total size - sizeof header > data size\r
	345	mov ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r
	346	sub ecx, MicrocodeHdr.size\r
	347	cmp ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r
	348	jng NextMicrocode ; Jif extended header does not exist\r
	349	\r
	350	; Set edi -> extended header\r
	351	mov edi, esi\r
	352	add edi, MicrocodeHdr.size\r
	353	add edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r
	354	\r
	355	; Get count of extended structures\r
	356	mov ecx, dword [edi + ExtSigHdr.ExtSigHdrCount]\r
	357	\r
358	; Move pointer to first signature structure\r
359	add edi, ExtSigHdr.size\r
360	\r
361	CheckExtSig:\r
362	; Check if extended signature and platform ID match\r
363	cmp dword [edi + ExtSig.ExtSigProcessor], ebx\r
364	jne LoadMicrocodeDefault2\r
365	test dword [edi + ExtSig.ExtSigFlags], edx\r
366	jnz LoadCheck ; Jif signature and platform ID match\r
367	LoadMicrocodeDefault2:\r
368	; Check if any more extended signatures exist\r
369	add edi, ExtSig.size\r
370	loop CheckExtSig\r
371	\r
372	NextMicrocode:\r
373	; Advance just after end of this microcode\r
374	xor eax, eax\r
375	cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r
376	je LoadMicrocodeDefault3\r
377	add esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r
378	jmp CheckAddress\r
379	LoadMicrocodeDefault3:\r
380	add esi, dword 2048\r
381	jmp CheckAddress\r
382	\r
383	AdvanceFixedSize:\r
384	; Advance by 4X dwords\r
385	add esi, dword 1024\r
386	\r
387	CheckAddress:\r
89f569ae	388	; Check UPD header revision\r
6f219bef TK	389	cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
	390	jb Fsp20UpdHeader1\r
	391	cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
	392	je Fsp24UpdHeader1;\r
	393	jmp Fsp22UpdHeader1\r
89f569ae	394	\r
6f219bef	395	Fsp20UpdHeader1:\r
89f569ae	396	; UPD structure is compliant with FSP spec 2.0/2.1\r
cf1d4549 JY	397	; Is automatic size detection ?\r
	398	mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
	399	cmp eax, 0ffffffffh\r
	400	jz LoadMicrocodeDefault4\r
	401	\r
	402	; Address >= microcode region address + microcode region size?\r
	403	add eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
	404	cmp esi, eax\r
	405	jae Done ;Jif address is outside of microcode region\r
	406	jmp CheckMainHeader\r
	407	\r
89f569ae CC	408	Fsp22UpdHeader1:\r
	409	; UPD structure is compliant with FSP spec 2.2\r
	410	; Is automatic size detection ?\r
	411	mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
	412	cmp eax, 0ffffffffh\r
	413	jz LoadMicrocodeDefault4\r
	414	\r
	415	; Address >= microcode region address + microcode region size?\r
	416	add eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
	417	cmp esi, eax\r
	418	jae Done ;Jif address is outside of microcode region\r
	419	jmp CheckMainHeader\r
	420	\r
6f219bef TK	421	Fsp24UpdHeader1:\r
	422	; UPD structure is compliant with FSP spec 2.4\r
	423	; Is automatic size detection ?\r
	424	mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
	425	cmp eax, 0ffffffffh\r
	426	jz LoadMicrocodeDefault4\r
	427	\r
	428	; Address >= microcode region address + microcode region size?\r
	429	add eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
	430	cmp esi, eax\r
	431	jae Done ;Jif address is outside of microcode region\r
	432	jmp CheckMainHeader\r
	433	\r
cf1d4549	434	LoadMicrocodeDefault4:\r
31e97bda CL	435	; Is valid Microcode start point ?\r
	436	cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
	437	jz Done\r
	438	\r
cf1d4549 JY	439	LoadCheck:\r
	440	; Get the revision of the current microcode update loaded\r
	441	mov ecx, MSR_IA32_BIOS_SIGN_ID\r
	442	xor eax, eax ; Clear EAX\r
	443	xor edx, edx ; Clear EDX\r
	444	wrmsr ; Load 0 to MSR at 8Bh\r
	445	\r
	446	mov eax, 1\r
	447	cpuid\r
	448	mov ecx, MSR_IA32_BIOS_SIGN_ID\r
6f219bef	449	rdmsr ; Get current microcode signature\r
cf1d4549 JY	450	\r
	451	; Verify this microcode update is not already loaded\r
	452	cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r
	453	je Continue\r
	454	\r
	455	LoadMicrocode:\r
	456	; EAX contains the linear address of the start of the Update Data\r
	457	; EDX contains zero\r
	458	; ECX contains 79h (IA32_BIOS_UPDT_TRIG)\r
	459	; Start microcode load with wrmsr\r
	460	mov eax, esi\r
	461	add eax, MicrocodeHdr.size\r
	462	xor edx, edx\r
	463	mov ecx, MSR_IA32_BIOS_UPDT_TRIG\r
	464	wrmsr\r
	465	mov eax, 1\r
	466	cpuid\r
	467	\r
	468	Continue:\r
	469	jmp NextMicrocode\r
	470	\r
	471	Done:\r
	472	mov eax, 1\r
	473	cpuid\r
	474	mov ecx, MSR_IA32_BIOS_SIGN_ID\r
	475	rdmsr ; Get current microcode signature\r
	476	xor eax, eax\r
	477	cmp edx, 0\r
	478	jnz Exit2\r
	479	mov eax, 08000000Eh\r
	480	\r
	481	Exit2:\r
	482	jmp ebp\r
	483	\r
b84f32ae CC	484	;\r
	485	; EstablishStackFsp: EDI should be preserved cross this function\r
	486	;\r
cf1d4549 JY	487	global ASM_PFX(EstablishStackFsp)\r
	488	ASM_PFX(EstablishStackFsp):\r
	489	;\r
	490	; Save parameter pointer in edx\r
	491	;\r
b84f32ae	492	mov edx, ecx ; ECX has been assigned to UPD region\r
cf1d4549 JY	493	\r
	494	;\r
	495	; Enable FSP STACK\r
	496	;\r
	497	mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r
	498	add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r
	499	\r
	500	push DATA_LEN_OF_MCUD ; Size of the data region\r
	501	push 4455434Dh ; Signature of the data region 'MCUD'\r
cf1d4549	502	\r
89f569ae CC	503	; check UPD structure revision (edx + 8)\r
89f569ae CC	504	cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
6f219bef TK	505	jb Fsp20UpdHeader2\r
	506	cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
	507	je Fsp24UpdHeader2\r
	508	jmp Fsp22UpdHeader2\r
89f569ae	509	\r
6f219bef	510	Fsp20UpdHeader2:\r
89f569ae CC	511	; UPD structure is compliant with FSP spec 2.0/2.1\r
	512	push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r
	513	push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r
	514	push dword [edx + LoadMicrocodeParams.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r
	515	push dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
	516	jmp ContinueAfterUpdPush\r
	517	\r
	518	Fsp22UpdHeader2:\r
	519	; UPD structure is compliant with FSP spec 2.2\r
	520	push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r
	521	push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r
	522	push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r
	523	push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
6f219bef TK	524	jmp ContinueAfterUpdPush\r
	525	\r
	526	Fsp24UpdHeader2:\r
	527	; UPD structure is compliant with FSP spec 2.4\r
	528	push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 24\r
	529	push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 16\r
	530	push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 8\r
	531	push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
89f569ae CC	532	\r
89f569ae CC	533	ContinueAfterUpdPush:\r
cf1d4549 JY	534	;\r
	535	; Save API entry/exit timestamp into stack\r
	536	;\r
	537	push DATA_LEN_OF_PER0 ; Size of the data region\r
	538	push 30524550h ; Signature of the data region 'PER0'\r
	539	rdtsc\r
	540	push edx\r
	541	push eax\r
	542	LOAD_EDX\r
	543	push edx\r
	544	LOAD_EAX\r
	545	push eax\r
	546	\r
	547	;\r
	548	; Terminator for the data on stack\r
	549	;\r
	550	push 0\r
	551	\r
	552	;\r
	553	; Set ECX/EDX to the BootLoader temporary memory range\r
	554	;\r
	555	mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r
	556	mov edx, ecx\r
	557	add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r
	558	sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]\r
	559	\r
	560	cmp ecx, edx ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.\r
	561	jb EstablishStackFspSuccess\r
	562	mov eax, 80000003h ;EFI_UNSUPPORTED\r
	563	jmp EstablishStackFspExit\r
	564	EstablishStackFspSuccess:\r
	565	xor eax, eax\r
	566	\r
	567	EstablishStackFspExit:\r
	568	RET_ESI\r
	569	\r
	570	;----------------------------------------------------------------------------\r
	571	; TempRamInit API\r
	572	;\r
	573	; This FSP API will load the microcode update, enable code caching for the\r
	574	; region specified by the boot loader and also setup a temporary stack to be\r
	575	; used till main memory is initialized.\r
	576	;\r
	577	;----------------------------------------------------------------------------\r
	578	global ASM_PFX(TempRamInitApi)\r
	579	ASM_PFX(TempRamInitApi):\r
	580	;\r
	581	; Ensure SSE is enabled\r
	582	;\r
	583	ENABLE_SSE\r
	584	\r
	585	;\r
	586	; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6\r
	587	;\r
	588	SAVE_REGS\r
	589	\r
	590	;\r
	591	; Save timestamp into XMM6\r
	592	;\r
	593	rdtsc\r
	594	SAVE_EAX\r
	595	SAVE_EDX\r
	596	\r
3182843f KT	597	CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param\r
	598	SAVE_ECX ; save UPD param to slot 3 in xmm6\r
	599	\r
cf1d4549 JY	600	;\r
	601	; Sec Platform Init\r
	602	;\r
	603	CALL_MMX ASM_PFX(SecPlatformInit)\r
	604	cmp eax, 0\r
	605	jnz TempRamInitExit\r
	606	\r
	607	; Load microcode\r
	608	LOAD_ESP\r
3182843f	609	LOAD_ECX\r
cf1d4549	610	CALL_MMX ASM_PFX(LoadMicrocodeDefault)\r
3182843f	611	SAVE_UCODE_STATUS ; Save microcode return status in slot 1 in xmm5.\r
cf1d4549 JY	612	;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r
	613	\r
	614	; Call Sec CAR Init\r
	615	LOAD_ESP\r
3182843f	616	LOAD_ECX\r
cf1d4549 JY	617	CALL_MMX ASM_PFX(SecCarInit)\r
	618	cmp eax, 0\r
	619	jnz TempRamInitExit\r
	620	\r
	621	LOAD_ESP\r
3182843f KT	622	LOAD_ECX\r
3182843f KT	623	mov edi, ecx ; Save UPD param to EDI for later code use\r
cf1d4549 JY	624	CALL_MMX ASM_PFX(EstablishStackFsp)\r
	625	cmp eax, 0\r
	626	jnz TempRamInitExit\r
	627	\r
3182843f	628	LOAD_UCODE_STATUS ; Restore microcode status if no CAR init error from slot 1 in xmm5.\r
cf1d4549 JY	629	\r
cf1d4549 JY	630	TempRamInitExit:\r
6f219bef TK	631	mov bl, al ; save al data in bl\r
	632	mov al, 07Fh ; API exit postcode 7f\r
	633	out 080h, al\r
	634	mov al, bl ; restore al data from bl\r
cf1d4549 JY	635	\r
	636	;\r
	637	; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r
	638	;\r
	639	LOAD_REGS\r
	640	ret\r
	641	\r
	642	;----------------------------------------------------------------------------\r
	643	; Module Entrypoint API\r
	644	;----------------------------------------------------------------------------\r
	645	global ASM_PFX(_ModuleEntryPoint)\r
	646	ASM_PFX(_ModuleEntryPoint):\r
	647	jmp $\r