IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T

[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Ia32 / SaveRestoreSseNasm.inc

;------------------------------------------------------------------------------\r
;\r
; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Abstract:\r
;\r
;   Provide macro for register save/restore using SSE registers\r
;\r
;------------------------------------------------------------------------------\r
\r
;\r
; Define SSE instruction set\r
;\r
%ifdef USE_SSE41_FLAG\r
;\r
; Define SSE macros using SSE 4.1 instructions\r
; args 1:XMM, 2:IDX, 3:REG\r
%macro SXMMN    3\r
             pinsrd  %1, %3, (%2 & 3)\r
             %endmacro\r
\r
;\r
;args 1:XMM, 2:REG, 3:IDX\r
;\r
%macro LXMMN    3\r
             pextrd  %2, %1, (%3 & 3)\r
             %endmacro\r
%else\r
;\r
; Define SSE macros using SSE 2 instructions\r
; args 1:XMM, 2:IDX, 3:REG\r
%macro SXMMN    3\r
             pinsrw  %1, %3, (%2 & 3) * 2\r
             ror     %3, 16\r
             pinsrw  %1, %3, (%2 & 3) * 2 + 1\r
             rol     %3, 16\r
             %endmacro\r
\r
;\r
;args 1:XMM, 2:REG, 3:IDX\r
;\r
%macro LXMMN    3\r
             pshufd  %1, %1, ((0E4E4E4h >> (%3 * 2))  & 0FFh)\r
             movd    %2, %1\r
             pshufd  %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)\r
             %endmacro\r
%endif\r
\r
;\r
; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slot 3\r
;\r
%macro SAVE_REGS    0\r
  SXMMN      xmm7, 0, ebp\r
  SXMMN      xmm7, 1, ebx\r
  SXMMN      xmm7, 2, esi\r
  SXMMN      xmm7, 3, edi\r
  SAVE_ESP\r
             %endmacro\r
\r
%macro LOAD_REGS    0\r
  LXMMN      xmm7, ebp, 0\r
  LXMMN      xmm7, ebx, 1\r
  LXMMN      xmm7, esi, 2\r
  LXMMN      xmm7, edi, 3\r
  LOAD_ESP\r
             %endmacro\r
\r
;\r
; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slot 3\r
;\r
%macro LOAD_ESP    0\r
  movd       esp,  xmm6\r
             %endmacro\r
\r
%macro SAVE_ESP    0\r
  SXMMN      xmm6, 0, esp\r
             %endmacro\r
\r
%macro LOAD_EAX    0\r
  LXMMN      xmm6, eax, 1\r
             %endmacro\r
\r
%macro SAVE_EAX    0\r
  SXMMN      xmm6, 1, eax\r
             %endmacro\r
\r
%macro LOAD_EDX    0\r
  LXMMN      xmm6, edx, 2\r
             %endmacro\r
\r
%macro SAVE_EDX    0\r
  SXMMN      xmm6, 2, edx\r
             %endmacro\r
\r
%macro LOAD_ECX    0\r
  LXMMN      xmm6, ecx, 3\r
             %endmacro\r
\r
%macro SAVE_ECX    0\r
  SXMMN      xmm6, 3, ecx\r
             %endmacro\r
\r
;\r
; XMM5 slot 0 for calling stack\r
; arg 1:Entry\r
%macro CALL_XMM       1\r
             mov     esi, %%ReturnAddress\r
             SXMMN   xmm5, 0, esi\r
             mov     esi,  %1\r
             jmp     esi\r
%%ReturnAddress:\r
             %endmacro\r
\r
%macro RET_XMM       0\r
             LXMMN   xmm5, esi, 0\r
             jmp     esi\r
             %endmacro\r
\r
;\r
; XMM5 slot 1 for uCode status\r
;\r
%macro LOAD_UCODE_STATUS    0\r
  LXMMN      xmm5, eax, 1\r
             %endmacro\r
\r
%macro SAVE_UCODE_STATUS    0\r
  SXMMN      xmm5, 1, eax\r
             %endmacro\r
\r
%macro ENABLE_SSE   0\r
            ;\r
            ; Initialize floating point units\r
            ;\r
            jmp     NextAddress\r
align 4\r
            ;\r
            ; Float control word initial value:\r
            ; all exceptions masked, double-precision, round-to-nearest\r
            ;\r
FpuControlWord       DW      027Fh\r
            ;\r
            ; Multimedia-extensions control word:\r
            ; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
            ;\r
MmxControlWord       DD      01F80h\r
SseError:\r
            ;\r
            ; Processor has to support SSE\r
            ;\r
            jmp     SseError\r
NextAddress:\r
            finit\r
            fldcw   [FpuControlWord]\r
\r
            ;\r
            ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
            ; whether the processor supports SSE instruction.\r
            ;\r
            mov     eax, 1\r
            cpuid\r
            bt      edx, 25\r
            jnc     SseError\r
\r
%ifdef USE_SSE41_FLAG\r
            ;\r
            ; SSE 4.1 support\r
            ;\r
            bt      ecx, 19\r
            jnc     SseError\r
%endif\r
\r
            ;\r
            ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
            ;\r
            mov     eax, cr4\r
            or      eax, 00000600h\r
            mov     cr4, eax\r
\r
            ;\r
            ; The processor should support SSE instruction and we can use\r
            ; ldmxcsr instruction\r
            ;\r
            ldmxcsr [MmxControlWord]\r
            %endmacro\r