IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114

1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer
  respectively in TempRamInitApi in IA32 FspSecCoreT.
2.Correct inappropriate description in the return value of
  AsmGetFspInfoHeader.
3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in
  FspHeler.nasm.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 73821ad22a49cea81d607b56d0bedfbae8a30761..2cff8b3643246a45d01a83c13856f8e3052b12f2 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -594,37 +594,38 @@ ASM_PFX(TempRamInitApi):
   SAVE_EAX\r
   SAVE_EDX\r
 \r
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param\r
+  SAVE_ECX                               ; save UPD param to slot 3 in xmm6\r
+\r
   ;\r
   ; Sec Platform Init\r
   ;\r
-  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param\r
   CALL_MMX  ASM_PFX(SecPlatformInit)\r
   cmp       eax, 0\r
   jnz       TempRamInitExit\r
 \r
   ; Load microcode\r
   LOAD_ESP\r
-  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param\r
+  LOAD_ECX\r
   CALL_MMX  ASM_PFX(LoadMicrocodeDefault)\r
-  SXMMN     xmm6, 3, eax            ;Save microcode return status in ECX-SLOT 3 in xmm6.\r
+  SAVE_UCODE_STATUS                 ; Save microcode return status in slot 1 in xmm5.\r
   ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r
 \r
   ; Call Sec CAR Init\r
   LOAD_ESP\r
-  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param\r
+  LOAD_ECX\r
   CALL_MMX  ASM_PFX(SecCarInit)\r
   cmp       eax, 0\r
   jnz       TempRamInitExit\r
 \r
   LOAD_ESP\r
-  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param\r
-  mov       edi, ecx                     ; Save UPD param to EDI for later code use\r
+  LOAD_ECX\r
+  mov       edi, ecx                ; Save UPD param to EDI for later code use\r
   CALL_MMX  ASM_PFX(EstablishStackFsp)\r
   cmp       eax, 0\r
   jnz       TempRamInitExit\r
 \r
-  LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
-  SXMMN     xmm6, 3, edi  ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6.\r
+  LOAD_UCODE_STATUS                 ; Restore microcode status if no CAR init error from slot 1 in xmm5.\r
 \r
 TempRamInitExit:\r
   mov       bl, al                  ; save al data in bl\r

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm
index e3e1945473f895c162849e545698c216ad1c52d8..3c63f6eea50f60f66a1aea9ab92c24fb807bb5a7 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm
@@ -7,6 +7,8 @@
 \r
     SECTION .text\r
 \r
+FSP_HEADER_IMGBASE_OFFSET    EQU   1Ch\r
+\r
 global ASM_PFX(FspInfoHeaderRelativeOff)\r
 ASM_PFX(FspInfoHeaderRelativeOff):\r
    DD    0x12345678               ; This value must be patched by the build script\r
@@ -14,7 +16,7 @@ ASM_PFX(FspInfoHeaderRelativeOff):
 global ASM_PFX(AsmGetFspBaseAddress)\r
 ASM_PFX(AsmGetFspBaseAddress):\r
    call  ASM_PFX(AsmGetFspInfoHeader)\r
-   add   eax, 0x1C\r
+   add   eax, FSP_HEADER_IMGBASE_OFFSET\r
    mov   eax, dword [eax]\r
    ret\r
 \r

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
index 4c321cbeceb2089596fc2a030eb4d4b827cd39ee..a222f2e37676042c66c8fe827ca1ac3f41509613 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------\r
 ;\r
-; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Abstract:\r
@@ -16,21 +16,21 @@
 ;\r
 ; Define SSE macros using SSE 4.1 instructions\r
 ; args 1:XMM, 2:IDX, 3:REG\r
-%macro SXMMN           3\r
+%macro SXMMN    3\r
              pinsrd  %1, %3, (%2 & 3)\r
              %endmacro\r
 \r
 ;\r
 ;args 1:XMM, 2:REG, 3:IDX\r
 ;\r
-%macro LXMMN           3\r
+%macro LXMMN    3\r
              pextrd  %2, %1, (%3 & 3)\r
              %endmacro\r
 %else\r
 ;\r
 ; Define SSE macros using SSE 2 instructions\r
 ; args 1:XMM, 2:IDX, 3:REG\r
-%macro SXMMN       3\r
+%macro SXMMN    3\r
              pinsrw  %1, %3, (%2 & 3) * 2\r
              ror     %3, 16\r
              pinsrw  %1, %3, (%2 & 3) * 2 + 1\r
@@ -38,19 +38,19 @@
              %endmacro\r
 \r
 ;\r
-;args 1:XMM, 2:REG,  3:IDX\r
+;args 1:XMM, 2:REG, 3:IDX\r
 ;\r
 %macro LXMMN    3\r
-             pshufd  %1, %1,  ((0E4E4E4h >> (%3 * 2))  & 0FFh)\r
+             pshufd  %1, %1, ((0E4E4E4h >> (%3 * 2))  & 0FFh)\r
              movd    %2, %1\r
-             pshufd  %1, %1,  ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)\r
+             pshufd  %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)\r
              %endmacro\r
 %endif\r
 \r
 ;\r
-; XMM7 to save/restore EBP, EBX, ESI, EDI\r
+; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slot 3\r
 ;\r
-%macro SAVE_REGS   0\r
+%macro SAVE_REGS    0\r
   SXMMN      xmm7, 0, ebp\r
   SXMMN      xmm7, 1, ebx\r
   SXMMN      xmm7, 2, esi\r
@@ -67,63 +67,67 @@
              %endmacro\r
 \r
 ;\r
-; XMM6 to save/restore EAX, EDX, ECX, ESP\r
+; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slot 3\r
 ;\r
-%macro LOAD_EAX     0\r
+%macro LOAD_ESP    0\r
+  movd       esp,  xmm6\r
+             %endmacro\r
+\r
+%macro SAVE_ESP    0\r
+  SXMMN      xmm6, 0, esp\r
+             %endmacro\r
+\r
+%macro LOAD_EAX    0\r
   LXMMN      xmm6, eax, 1\r
              %endmacro\r
 \r
-%macro SAVE_EAX     0\r
+%macro SAVE_EAX    0\r
   SXMMN      xmm6, 1, eax\r
              %endmacro\r
 \r
-%macro LOAD_EDX     0\r
+%macro LOAD_EDX    0\r
   LXMMN      xmm6, edx, 2\r
              %endmacro\r
 \r
-%macro SAVE_EDX     0\r
+%macro SAVE_EDX    0\r
   SXMMN      xmm6, 2, edx\r
              %endmacro\r
 \r
-%macro SAVE_ECX     0\r
-  SXMMN      xmm6, 3, ecx\r
-             %endmacro\r
-\r
-%macro LOAD_ECX     0\r
+%macro LOAD_ECX    0\r
   LXMMN      xmm6, ecx, 3\r
              %endmacro\r
 \r
-%macro SAVE_ESP     0\r
-  SXMMN      xmm6, 0, esp\r
+%macro SAVE_ECX    0\r
+  SXMMN      xmm6, 3, ecx\r
              %endmacro\r
 \r
-%macro LOAD_ESP     0\r
-  movd       esp,  xmm6\r
-             %endmacro\r
 ;\r
-; XMM5 for calling stack\r
+; XMM5 slot 0 for calling stack\r
 ; arg 1:Entry\r
 %macro CALL_XMM       1\r
              mov     esi, %%ReturnAddress\r
-             pslldq  xmm5, 4\r
-%ifdef USE_SSE41_FLAG\r
-             pinsrd  xmm5, esi, 0\r
-%else\r
-             pinsrw  xmm5, esi, 0\r
-             ror     esi,  16\r
-             pinsrw  xmm5, esi, 1\r
-%endif\r
+             SXMMN   xmm5, 0, esi\r
              mov     esi,  %1\r
              jmp     esi\r
 %%ReturnAddress:\r
              %endmacro\r
 \r
 %macro RET_XMM       0\r
-             movd    esi, xmm5\r
-             psrldq  xmm5, 4\r
+             LXMMN   xmm5, esi, 0\r
              jmp     esi\r
              %endmacro\r
 \r
+;\r
+; XMM5 slot 1 for uCode status\r
+;\r
+%macro LOAD_UCODE_STATUS    0\r
+  LXMMN      xmm5, eax, 1\r
+             %endmacro\r
+\r
+%macro SAVE_UCODE_STATUS    0\r
+  SXMMN      xmm5, 1, eax\r
+             %endmacro\r
+\r
 %macro ENABLE_SSE   0\r
             ;\r
             ; Initialize floating point units\r

diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/SecFsp.h
index d7a5976c12823577a468639e1c5b56c94e69af3e..693af29f203eeac46eea86945822719a1b381704 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.h
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h
@@ -79,7 +79,7 @@ AsmGetFspBaseAddress (
 /**\r
   This interface gets FspInfoHeader pointer\r
 \r
-  @return   FSP binary base address.\r
+  @return   FSP info header.\r
 \r
 **/\r
 UINTN\r

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
index 122fa1d174cace22d03f2bb075e98398fd879afe..71624a3aad734bc86e61cefc66a4e704cbf74dee 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
@@ -7,10 +7,12 @@
     DEFAULT  REL\r
     SECTION .text\r
 \r
+FSP_HEADER_IMGBASE_OFFSET    EQU   1Ch\r
+\r
 global ASM_PFX(AsmGetFspBaseAddress)\r
 ASM_PFX(AsmGetFspBaseAddress):\r
    call  ASM_PFX(AsmGetFspInfoHeader)\r
-   add   rax, 0x1C\r
+   add   rax, FSP_HEADER_IMGBASE_OFFSET\r
    mov   eax, [rax]\r
    ret\r
 \r