]> git.proxmox.com Git - mirror_edk2.git/blame - IntelFsp2Pkg/Include/FspEas/FspApi.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / IntelFsp2Pkg / Include / FspEas / FspApi.h
CommitLineData
cf1d4549
JY		 1/** @file\r
2 Intel FSP API definition from Intel Firmware Support Package External\r
5a3641bf 3 Architecture Specification v2.0 and above.\r
cf1d4549 4\r
6f219bef 5 Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
9672cd30 6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
cf1d4549
JY		 7\r
8**/\r
9\r
10#ifndef _FSP_API_H_\r
11#define _FSP_API_H_\r
12\r
f2cdb268 13#include <Pi/PiStatusCode.h>\r
140446cd 14#include <Base.h>\r
f2cdb268 15\r
19089568
GM		 16///\r
17/// FSP Reset Status code\r
140446cd 18/// These are defined in FSP EAS v2.4 section 13.2.2 - OEM Status Code\r
19089568 19/// @{\r
140446cd
CC		 20\r
21#define ENCODE_RESET_REQUEST(ResetType) \\r
22 ((EFI_STATUS)((MAX_BIT >> 1) | (ResetType)))\r
23#define FSP_STATUS_RESET_REQUIRED_COLD ENCODE_RESET_REQUEST(1)\r
24#define FSP_STATUS_RESET_REQUIRED_WARM ENCODE_RESET_REQUEST(2)\r
25#define FSP_STATUS_RESET_REQUIRED_3 ENCODE_RESET_REQUEST(3)\r
26#define FSP_STATUS_RESET_REQUIRED_4 ENCODE_RESET_REQUEST(4)\r
27#define FSP_STATUS_RESET_REQUIRED_5 ENCODE_RESET_REQUEST(5)\r
28#define FSP_STATUS_RESET_REQUIRED_6 ENCODE_RESET_REQUEST(6)\r
29#define FSP_STATUS_RESET_REQUIRED_7 ENCODE_RESET_REQUEST(7)\r
30#define FSP_STATUS_RESET_REQUIRED_8 ENCODE_RESET_REQUEST(8)\r
31#define FSP_STATUS_VARIABLE_REQUEST ENCODE_RESET_REQUEST(10)\r
19089568
GM		 32/// @}\r
33\r
f2cdb268
CC		 34///\r
35/// FSP Event related definition.\r
36///\r
111f2228
MK		 37#define FSP_EVENT_CODE 0xF5000000\r
38#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)\r
f2cdb268
CC		 39\r
40/*\r
41 FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.\r
42 These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the\r
43 status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3.\r
44\r
45 @param[in] Type Indicates the type of event being reported.\r
46 See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE.\r
47 @param[in] Value Describes the current status of a hardware or software entity.\r
48 This includes information about the class and subclass that is used to classify the entity as well as an operation.\r
49 For progress events, the operation is the current activity. For error events, it is the exception.\r
50 For debug events, it is not defined at this time.\r
51 See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE.\r
52 @param[in] Instance The enumeration of a hardware or software entity within the system.\r
53 A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them.\r
54 An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant.\r
55 Valid instance numbers start with 1.\r
56 @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event.\r
57 This parameter may be NULL.\r
58 @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data.\r
59 For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages.\r
60 This parameter is NULL when no additional data is provided.\r
61\r
62 @retval EFI_SUCCESS The event was handled successfully.\r
63 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
64 @retval EFI_DEVICE_ERROR The event handler failed.\r
65*/\r
66typedef\r
67EFI_STATUS\r
111f2228 68(EFIAPI *FSP_EVENT_HANDLER)(\r
f2cdb268
CC		 69 IN EFI_STATUS_CODE_TYPE Type,\r
70 IN EFI_STATUS_CODE_VALUE Value,\r
71 IN UINT32 Instance,\r
72 IN OPTIONAL EFI_GUID *CallerId,\r
73 IN OPTIONAL EFI_STATUS_CODE_DATA *Data\r
74 );\r
75\r
76/*\r
77 Handler for FSP-T debug log messages, provided by the bootloader.\r
78\r
79 @param[in] DebugMessage A pointer to the debug message to be written to the log.\r
80 @param[in] MessageLength Number of bytes to written to the debug log.\r
81\r
82 @retval UINT32 The return value indicates the number of bytes actually written to\r
83 the debug log. If the return value is less than MessageLength,\r
84 an error occurred.\r
85*/\r
86typedef\r
87UINT32\r
111f2228
MK		 88(EFIAPI *FSP_DEBUG_HANDLER)(\r
89 IN CHAR8 *DebugMessage,\r
f2cdb268
CC		 90 IN UINT32 MessageLength\r
91 );\r
92\r
cf1d4549 93#pragma pack(1)\r
6d0ac988
JY		 94///\r
95/// FSP_UPD_HEADER Configuration.\r
96///\r
cf1d4549
JY		 97typedef struct {\r
98 ///\r
99 /// UPD Region Signature. This signature will be\r
100 /// "XXXXXX_T" for FSP-T\r
101 /// "XXXXXX_M" for FSP-M\r
102 /// "XXXXXX_S" for FSP-S\r
5a3641bf 103 /// "XXXXXX_I" for FSP-I\r
cf1d4549
JY		 104 /// Where XXXXXX is an unique signature\r
105 ///\r
111f2228 106 UINT64 Signature;\r
cf1d4549 107 ///\r
89f569ae 108 /// Revision of the Data structure.\r
5a3641bf
CC		 109 /// For FSP spec 2.0/2.1, this value is 1 and only FSPM_UPD having ARCH_UPD.\r
110 /// For FSP spec 2.2 and above, this value is 2 and ARCH_UPD present in all UPD structures.\r
cf1d4549 111 ///\r
111f2228
MK		 112 UINT8 Revision;\r
113 UINT8 Reserved[23];\r
cf1d4549
JY		 114} FSP_UPD_HEADER;\r
115\r
89f569ae
CC		 116///\r
117/// FSPT_ARCH_UPD Configuration.\r
118///\r
119typedef struct {\r
120 ///\r
6f219bef 121 /// Revision of the structure is 1 for this version of the specification.\r
89f569ae 122 ///\r
111f2228
MK		 123 UINT8 Revision;\r
124 UINT8 Reserved[3];\r
89f569ae 125 ///\r
6f219bef 126 /// Length of the structure in bytes. The current value for this field is 32.\r
89f569ae 127 ///\r
111f2228 128 UINT32 Length;\r
89f569ae
CC		 129 ///\r
130 /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r
131 /// occurring during FSP execution.\r
132 ///\r
111f2228
MK		 133 FSP_DEBUG_HANDLER FspDebugHandler;\r
134 UINT8 Reserved1[20];\r
89f569ae
CC		 135} FSPT_ARCH_UPD;\r
136\r
6f219bef 137///\r
5a3641bf 138/// FSPT_ARCH2_UPD Configuration for FSP 2.4 and above.\r
6f219bef
TK		 139///\r
140typedef struct {\r
141 ///\r
142 /// Revision of the structure is 2 for this version of the specification.\r
143 ///\r
140446cd
CC		 144 UINT8 Revision;\r
145 UINT8 Reserved[3];\r
6f219bef
TK		 146 ///\r
147 /// Length of the structure in bytes. The current value for this field is 32.\r
148 ///\r
140446cd 149 UINT32 Length;\r
6f219bef
TK		 150 ///\r
151 /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r
152 /// occurring during FSP execution.\r
153 ///\r
140446cd
CC		 154 EFI_PHYSICAL_ADDRESS FspDebugHandler;\r
155 UINT8 Reserved1[16];\r
6f219bef
TK		 156} FSPT_ARCH2_UPD;\r
157\r
6d0ac988
JY		 158///\r
159/// FSPM_ARCH_UPD Configuration.\r
160///\r
cf1d4549
JY		 161typedef struct {\r
162 ///\r
163 /// Revision of the structure. For FSP v2.0 value is 1.\r
164 ///\r
111f2228
MK		 165 UINT8 Revision;\r
166 UINT8 Reserved[3];\r
cf1d4549
JY		 167 ///\r
168 /// Pointer to the non-volatile storage (NVS) data buffer.\r
169 /// If it is NULL it indicates the NVS data is not available.\r
170 ///\r
111f2228 171 VOID *NvsBufferPtr;\r
cf1d4549
JY		 172 ///\r
173 /// Pointer to the temporary stack base address to be\r
174 /// consumed inside FspMemoryInit() API.\r
175 ///\r
111f2228 176 VOID *StackBase;\r
cf1d4549
JY		 177 ///\r
178 /// Temporary stack size to be consumed inside\r
179 /// FspMemoryInit() API.\r
180 ///\r
111f2228 181 UINT32 StackSize;\r
cf1d4549
JY		 182 ///\r
183 /// Size of memory to be reserved by FSP below "top\r
184 /// of low usable memory" for bootloader usage.\r
185 ///\r
111f2228 186 UINT32 BootLoaderTolumSize;\r
cf1d4549
JY		 187 ///\r
188 /// Current boot mode.\r
189 ///\r
111f2228 190 UINT32 BootMode;\r
f2cdb268
CC		 191 ///\r
192 /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r
193 /// This value is only valid if Revision is >= 2.\r
194 ///\r
111f2228
MK		 195 FSP_EVENT_HANDLER *FspEventHandler;\r
196 UINT8 Reserved1[4];\r
cf1d4549
JY		 197} FSPM_ARCH_UPD;\r
198\r
6f219bef 199///\r
5a3641bf 200/// FSPM_ARCH2_UPD Configuration for FSP 2.4 and above.\r
6f219bef
TK		 201///\r
202typedef struct {\r
203 ///\r
204 /// Revision of the structure is 3 for this version of the specification.\r
205 ///\r
140446cd
CC		 206 UINT8 Revision;\r
207 UINT8 Reserved[3];\r
6f219bef
TK		 208 ///\r
209 /// Length of the structure in bytes. The current value for this field is 64.\r
210 ///\r
140446cd 211 UINT32 Length;\r
6f219bef 212 ///\r
5a3641bf
CC		 213 /// Pointer to the non-volatile storage (NVS) data buffer.\r
214 /// If it is NULL it indicates the NVS data is not available.\r
215 /// This value is deprecated starting with v2.4 of the FSP specification,\r
216 /// and will be removed in an upcoming version of the FSP specification.\r
217 ///\r
218 EFI_PHYSICAL_ADDRESS NvsBufferPtr;\r
219 ///\r
6f219bef
TK		 220 /// Pointer to the temporary stack base address to be\r
221 /// consumed inside FspMemoryInit() API.\r
222 ///\r
140446cd 223 EFI_PHYSICAL_ADDRESS StackBase;\r
6f219bef
TK		 224 ///\r
225 /// Temporary stack size to be consumed inside\r
226 /// FspMemoryInit() API.\r
227 ///\r
140446cd 228 UINT64 StackSize;\r
6f219bef
TK		 229 ///\r
230 /// Size of memory to be reserved by FSP below "top\r
231 /// of low usable memory" for bootloader usage.\r
232 ///\r
140446cd 233 UINT32 BootLoaderTolumSize;\r
6f219bef
TK		 234 ///\r
235 /// Current boot mode.\r
236 ///\r
140446cd 237 UINT32 BootMode;\r
6f219bef
TK		 238 ///\r
239 /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r
240 /// This value is only valid if Revision is >= 2.\r
241 ///\r
140446cd 242 EFI_PHYSICAL_ADDRESS FspEventHandler;\r
5a3641bf 243 UINT8 Reserved1[16];\r
6f219bef
TK		 244} FSPM_ARCH2_UPD;\r
245\r
246///\r
247/// FSPS_ARCH_UPD Configuration.\r
248///\r
89f569ae
CC		 249typedef struct {\r
250 ///\r
6f219bef 251 /// Revision of the structure is 1 for this version of the specification.\r
89f569ae 252 ///\r
111f2228
MK		 253 UINT8 Revision;\r
254 UINT8 Reserved[3];\r
89f569ae 255 ///\r
6f219bef 256 /// Length of the structure in bytes. The current value for this field is 32.\r
89f569ae 257 ///\r
111f2228 258 UINT32 Length;\r
89f569ae
CC		 259 ///\r
260 /// FspEventHandler Optional event handler for the bootloader to be informed of events\r
261 /// occurring during FSP execution.\r
262 ///\r
111f2228 263 FSP_EVENT_HANDLER FspEventHandler;\r
89f569ae
CC		 264 ///\r
265 /// A FSP binary may optionally implement multi-phase silicon initialization,\r
266 /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER\r
267 /// is non-zero.\r
268 /// To enable multi-phase silicon initialization, the bootloader must set\r
269 /// EnableMultiPhaseSiliconInit to a non-zero value.\r
270 ///\r
111f2228
MK		 271 UINT8 EnableMultiPhaseSiliconInit;\r
272 UINT8 Reserved1[19];\r
89f569ae
CC		 273} FSPS_ARCH_UPD;\r
274\r
6f219bef 275///\r
5a3641bf 276/// FSPS_ARCH2_UPD Configuration for FSP 2.4 and above.\r
6f219bef
TK		 277///\r
278typedef struct {\r
279 ///\r
280 /// Revision of the structure is 2 for this version of the specification.\r
281 ///\r
140446cd
CC		 282 UINT8 Revision;\r
283 UINT8 Reserved[3];\r
6f219bef
TK		 284 ///\r
285 /// Length of the structure in bytes. The current value for this field is 32.\r
286 ///\r
140446cd 287 UINT32 Length;\r
6f219bef
TK		 288 ///\r
289 /// FspEventHandler Optional event handler for the bootloader to be informed of events\r
290 /// occurring during FSP execution.\r
291 ///\r
140446cd
CC		 292 EFI_PHYSICAL_ADDRESS FspEventHandler;\r
293 UINT8 Reserved1[16];\r
6f219bef
TK		 294} FSPS_ARCH2_UPD;\r
295\r
5a3641bf
CC		 296///\r
297/// FSPI_ARCH_UPD Configuration.\r
298///\r
299typedef struct {\r
300 ///\r
301 /// Revision of the structure is 1 for this version of the specification.\r
302 ///\r
303 UINT8 Revision;\r
304 UINT8 Reserved[3];\r
305 ///\r
306 /// Length of the structure in bytes. The current value for this field is 64.\r
307 ///\r
308 UINT32 Length;\r
309 ///\r
310 /// The physical memory-mapped base address of the bootloader SMM firmware volume (FV).\r
311 ///\r
312 EFI_PHYSICAL_ADDRESS BootloaderSmmFvBaseAddress;\r
313 ///\r
314 /// The length in bytes of the bootloader SMM firmware volume (FV).\r
315 ///\r
316 UINT64 BootloaderSmmFvLength;\r
317 ///\r
318 /// The physical memory-mapped base address of the bootloader SMM FV context data.\r
319 /// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.\r
320 ///\r
321 EFI_PHYSICAL_ADDRESS BootloaderSmmFvContextData;\r
322 ///\r
323 /// The length in bytes of the bootloader SMM FV context data.\r
324 /// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.\r
325 ///\r
326 UINT16 BootloaderSmmFvContextDataLength;\r
327 UINT8 Reserved1[30];\r
328} FSPI_ARCH_UPD;\r
329\r
6d0ac988
JY		 330///\r
331/// FSPT_UPD_COMMON Configuration.\r
332///\r
cf1d4549 333typedef struct {\r
6d0ac988
JY		 334 ///\r
335 /// FSP_UPD_HEADER Configuration.\r
336 ///\r
111f2228 337 FSP_UPD_HEADER FspUpdHeader;\r
cf1d4549
JY		 338} FSPT_UPD_COMMON;\r
339\r
89f569ae
CC		 340///\r
341/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r
342///\r
343typedef struct {\r
344 ///\r
345 /// FSP_UPD_HEADER Configuration.\r
346 ///\r
111f2228 347 FSP_UPD_HEADER FspUpdHeader;\r
89f569ae
CC		 348\r
349 ///\r
350 /// FSPT_ARCH_UPD Configuration.\r
351 ///\r
111f2228 352 FSPT_ARCH_UPD FsptArchUpd;\r
89f569ae
CC		 353} FSPT_UPD_COMMON_FSP22;\r
354\r
6f219bef
TK		 355///\r
356/// FSPT_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
357///\r
358typedef struct {\r
359 ///\r
360 /// FSP_UPD_HEADER Configuration.\r
361 ///\r
362 FSP_UPD_HEADER FspUpdHeader;\r
363\r
364 ///\r
365 /// FSPT_ARCH2_UPD Configuration.\r
366 ///\r
367 FSPT_ARCH2_UPD FsptArchUpd;\r
368} FSPT_UPD_COMMON_FSP24;\r
369\r
6d0ac988
JY		 370///\r
371/// FSPM_UPD_COMMON Configuration.\r
372///\r
cf1d4549 373typedef struct {\r
6d0ac988
JY		 374 ///\r
375 /// FSP_UPD_HEADER Configuration.\r
376 ///\r
111f2228 377 FSP_UPD_HEADER FspUpdHeader;\r
6d0ac988
JY		 378 ///\r
379 /// FSPM_ARCH_UPD Configuration.\r
380 ///\r
111f2228 381 FSPM_ARCH_UPD FspmArchUpd;\r
cf1d4549
JY		 382} FSPM_UPD_COMMON;\r
383\r
6f219bef
TK		 384///\r
385/// FSPM_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
386///\r
387typedef struct {\r
388 ///\r
389 /// FSP_UPD_HEADER Configuration.\r
390 ///\r
391 FSP_UPD_HEADER FspUpdHeader;\r
392 ///\r
393 /// FSPM_ARCH2_UPD Configuration.\r
394 ///\r
395 FSPM_ARCH2_UPD FspmArchUpd;\r
396} FSPM_UPD_COMMON_FSP24;\r
397\r
6d0ac988
JY		 398///\r
399/// FSPS_UPD_COMMON Configuration.\r
400///\r
cf1d4549 401typedef struct {\r
6d0ac988
JY		 402 ///\r
403 /// FSP_UPD_HEADER Configuration.\r
404 ///\r
111f2228 405 FSP_UPD_HEADER FspUpdHeader;\r
cf1d4549
JY		 406} FSPS_UPD_COMMON;\r
407\r
89f569ae
CC		 408///\r
409/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r
410///\r
411typedef struct {\r
412 ///\r
413 /// FSP_UPD_HEADER Configuration.\r
414 ///\r
111f2228 415 FSP_UPD_HEADER FspUpdHeader;\r
89f569ae
CC		 416\r
417 ///\r
418 /// FSPS_ARCH_UPD Configuration.\r
419 ///\r
111f2228 420 FSPS_ARCH_UPD FspsArchUpd;\r
89f569ae
CC		 421} FSPS_UPD_COMMON_FSP22;\r
422\r
6f219bef
TK		 423///\r
424/// FSPS_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
425///\r
426typedef struct {\r
427 ///\r
428 /// FSP_UPD_HEADER Configuration.\r
429 ///\r
430 FSP_UPD_HEADER FspUpdHeader;\r
431\r
432 ///\r
433 /// FSPS_ARCH2_UPD Configuration.\r
434 ///\r
435 FSPS_ARCH2_UPD FspsArchUpd;\r
436} FSPS_UPD_COMMON_FSP24;\r
437\r
5a3641bf
CC		 438///\r
439/// FSPI_UPD_COMMON Configuration.\r
440///\r
441typedef struct {\r
442 ///\r
443 /// FSP_UPD_HEADER Configuration.\r
444 ///\r
445 FSP_UPD_HEADER FspUpdHeader;\r
446\r
447 ///\r
448 /// FSPI_ARCH_UPD Configuration.\r
449 ///\r
450 FSPI_ARCH_UPD FspiArchUpd;\r
451} FSPI_UPD_COMMON;\r
452\r
6d0ac988
JY		 453///\r
454/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.\r
455///\r
cf1d4549
JY		 456typedef enum {\r
457 ///\r
458 /// This stage is notified when the bootloader completes the\r
459 /// PCI enumeration and the resource allocation for the\r
460 /// PCI devices is complete.\r
461 ///\r
462 EnumInitPhaseAfterPciEnumeration = 0x20,\r
463 ///\r
464 /// This stage is notified just before the bootloader hand-off\r
465 /// to the OS loader.\r
466 ///\r
111f2228 467 EnumInitPhaseReadyToBoot = 0x40,\r
cf1d4549
JY		 468 ///\r
469 /// This stage is notified just before the firmware/Preboot\r
470 /// environment transfers management of all system resources\r
471 /// to the OS or next level execution environment.\r
472 ///\r
111f2228 473 EnumInitPhaseEndOfFirmware = 0xF0\r
cf1d4549
JY		 474} FSP_INIT_PHASE;\r
475\r
6d0ac988
JY		 476///\r
477/// Definition of NOTIFY_PHASE_PARAMS.\r
478///\r
cf1d4549
JY		 479typedef struct {\r
480 ///\r
481 /// Notification phase used for NotifyPhase API\r
482 ///\r
111f2228 483 FSP_INIT_PHASE Phase;\r
cf1d4549
JY		 484} NOTIFY_PHASE_PARAMS;\r
485\r
f2cdb268
CC		 486///\r
487/// Action definition for FspMultiPhaseSiInit API\r
488///\r
489typedef enum {\r
df25a545
CC		 490 EnumMultiPhaseGetNumberOfPhases = 0x0,\r
491 EnumMultiPhaseExecutePhase = 0x1,\r
492 EnumMultiPhaseGetVariableRequestInfo = 0x2,\r
493 EnumMultiPhaseCompleteVariableRequest = 0x3\r
f2cdb268
CC		 494} FSP_MULTI_PHASE_ACTION;\r
495\r
df25a545
CC		 496typedef enum {\r
497 EnumFspVariableRequestGetVariable = 0x0,\r
498 EnumFspVariableRequestGetNextVariableName = 0x1,\r
499 EnumFspVariableRequestSetVariable = 0x2,\r
500 EnumFspVariableRequestQueryVariableInfo = 0x3\r
501} FSP_VARIABLE_REQUEST_TYPE;\r
502\r
503#pragma pack(16)\r
504typedef struct {\r
505 IN FSP_VARIABLE_REQUEST_TYPE VariableRequest;\r
506 IN OUT CHAR16 *VariableName;\r
507 IN OUT UINT64 *VariableNameSize;\r
508 IN OUT EFI_GUID *VariableGuid;\r
509 IN OUT UINT32 *Attributes;\r
510 IN OUT UINT64 *DataSize;\r
511 IN OUT VOID *Data;\r
512 OUT UINT64 *MaximumVariableStorageSize;\r
513 OUT UINT64 *RemainingVariableStorageSize;\r
514 OUT UINT64 *MaximumVariableSize;\r
515} FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS;\r
516\r
517typedef struct {\r
518 EFI_STATUS VariableRequestStatus;\r
519} FSP_MULTI_PHASE_COMPLETE_VARIABLE_REQUEST_PARAMS;\r
520#pragma pack()\r
521\r
f2cdb268
CC		 522///\r
523/// Data structure returned by FSP when bootloader calling\r
524/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)\r
525///\r
526typedef struct {\r
111f2228
MK		 527 UINT32 NumberOfPhases;\r
528 UINT32 PhasesExecuted;\r
f2cdb268
CC		 529} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;\r
530\r
531///\r
532/// FspMultiPhaseSiInit function parameter.\r
533///\r
534/// For action 0 (EnumMultiPhaseGetNumberOfPhases):\r
535/// - PhaseIndex must be 0.\r
536/// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS.\r
537///\r
538/// For action 1 (EnumMultiPhaseExecutePhase):\r
539/// - PhaseIndex will be the phase that will be executed by FSP.\r
540/// - MultiPhaseParamPtr shall be NULL.\r
541///\r
542typedef struct {\r
111f2228
MK		 543 IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;\r
544 IN UINT32 PhaseIndex;\r
545 IN OUT VOID *MultiPhaseParamPtr;\r
f2cdb268
CC		 546} FSP_MULTI_PHASE_PARAMS;\r
547\r
cf1d4549
JY		 548#pragma pack()\r
549\r
550/**\r
551 This FSP API is called soon after coming out of reset and before memory and stack is\r
552 available. This FSP API will load the microcode update, enable code caching for the\r
553 region specified by the boot loader and also setup a temporary stack to be used until\r
554 main memory is initialized.\r
555\r
556 A hardcoded stack can be set up with the following values, and the "esp" register\r
557 initialized to point to this hardcoded stack.\r
558 1. The return address where the FSP will return control after setting up a temporary\r
559 stack.\r
560 2. A pointer to the input parameter structure\r
561\r
562 However, since the stack is in ROM and not writeable, this FSP API cannot be called\r
563 using the "call" instruction, but needs to be jumped to.\r
564\r
565 @param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure.\r
566\r
567 @retval EFI_SUCCESS Temporary RAM was initialized successfully.\r
568 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
569 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
570 @retval EFI_DEVICE_ERROR Temp RAM initialization failed.\r
571\r
572 If this function is successful, the FSP initializes the ECX and EDX registers to point to\r
573 a temporary but writeable memory range available to the boot loader and returns with\r
574 FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary\r
575 memory range and EDX points to the end of the range. Boot loader is free to use the\r
576 whole range described. Typically the boot loader can reload the ESP register to point\r
577 to the end of this returned range so that it can be used as a standard stack.\r
578**/\r
579typedef\r
580EFI_STATUS\r
111f2228 581(EFIAPI *FSP_TEMP_RAM_INIT)(\r
cf1d4549
JY		 582 IN VOID *FsptUpdDataPtr\r
583 );\r
584\r
585/**\r
586 This FSP API is used to notify the FSP about the different phases in the boot process.\r
587 This allows the FSP to take appropriate actions as needed during different initialization\r
588 phases. The phases will be platform dependent and will be documented with the FSP\r
589 release. The current FSP supports two notify phases:\r
590 Post PCI enumeration\r
591 Ready To Boot\r
592\r
593 @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r
594\r
595 @retval EFI_SUCCESS The notification was handled successfully.\r
596 @retval EFI_UNSUPPORTED The notification was not called in the proper order.\r
597 @retval EFI_INVALID_PARAMETER The notification code is invalid.\r
598**/\r
599typedef\r
600EFI_STATUS\r
111f2228 601(EFIAPI *FSP_NOTIFY_PHASE)(\r
cf1d4549
JY		 602 IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r
603 );\r
604\r
605/**\r
606 This FSP API is called after TempRamInit and initializes the memory.\r
607 This FSP API accepts a pointer to a data structure that will be platform dependent\r
608 and defined for each FSP binary. This will be documented in Integration guide with\r
609 each FSP release.\r
610 After FspMemInit completes its execution, it passes the pointer to the HobList and\r
e37bb20c 611 returns to the boot loader from where it was called. BootLoader is responsible to\r
91cc60ba 612 migrate its stack and data to Memory.\r
cf1d4549
JY		 613 FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
614 complete the silicon initialization and provides bootloader an opportunity to get\r
615 control after system memory is available and before the temporary RAM is torn down.\r
616\r
91cc60ba 617 @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure.\r
cf1d4549
JY		 618 @param[out] HobListPtr Pointer to receive the address of the HOB list.\r
619\r
620 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
621 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
622 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
623 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
624 @retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met.\r
df25a545 625 @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
cf1d4549
JY		 626**/\r
627typedef\r
628EFI_STATUS\r
111f2228 629(EFIAPI *FSP_MEMORY_INIT)(\r
cf1d4549
JY		 630 IN VOID *FspmUpdDataPtr,\r
631 OUT VOID **HobListPtr\r
632 );\r
633\r
cf1d4549
JY		 634/**\r
635 This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary\r
636 memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure\r
637 that will be platform dependent and defined for each FSP binary. This will be\r
638 documented in Integration Guide.\r
639 FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
640 complete the silicon initialization and provides bootloader an opportunity to get\r
641 control after system memory is available and before the temporary RAM is torn down.\r
642\r
643 @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.\r
644 This structure is normally defined in the Integration Guide.\r
645 And if it is not defined in the Integration Guide, pass NULL.\r
646\r
647 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
648 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
649 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
650 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
651**/\r
652typedef\r
653EFI_STATUS\r
111f2228 654(EFIAPI *FSP_TEMP_RAM_EXIT)(\r
cf1d4549
JY		 655 IN VOID *TempRamExitParamPtr\r
656 );\r
657\r
cf1d4549
JY		 658/**\r
659 This FSP API is called after TempRamExit API.\r
660 FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the\r
661 silicon initialization.\r
662\r
663 @param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure.\r
664 If NULL, FSP will use the default parameters.\r
665\r
666 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
667 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
668 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
669 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
91cc60ba 670 @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
cf1d4549
JY		 671**/\r
672typedef\r
673EFI_STATUS\r
111f2228 674(EFIAPI *FSP_SILICON_INIT)(\r
cf1d4549
JY		 675 IN VOID *FspsUpdDataPtr\r
676 );\r
677\r
f2cdb268
CC		 678/**\r
679 This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase.\r
680 This FSP API provides multi-phase silicon initialization; which brings greater modularity\r
681 beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an\r
682 extra API to FSP-S. This allows the bootloader to add board specific initialization steps\r
683 throughout the SiliconInit flow as needed.\r
684\r
685 @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:\r
686 FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain\r
687 how many phases supported by FSP.\r
688 For action - EnumMultiPhaseExecutePhase:\r
689 FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.\r
690 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
691 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
692 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
693 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
694 @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
695**/\r
696typedef\r
697EFI_STATUS\r
111f2228 698(EFIAPI *FSP_MULTI_PHASE_SI_INIT)(\r
f2cdb268 699 IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr\r
111f2228 700 );\r
f2cdb268 701\r
48249243
HZ		 702/**\r
703 This FSP API initializes SMM and provide any OS runtime silicon services,\r
704 including Reliability, Availability, and Serviceability (RAS) features implemented by the CPU.\r
705\r
706 @param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure.\r
707 If NULL, FSP will use the default parameters.\r
708\r
709 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
710 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
711 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
712 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
713 @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
714**/\r
715typedef\r
716EFI_STATUS\r
717(EFIAPI *FSP_SMM_INIT)(\r
718 IN VOID *FspiUpdDataPtr\r
719 );\r
720\r
df25a545
CC		 721/**\r
722 This FSP API provides multi-phase memory and silicon initialization, which brings greater modularity to the existing\r
723 FspMemoryInit() and FspSiliconInit() API. Increased modularity is achieved by adding an extra API to FSP-M and FSP-S.\r
724 This allows the bootloader to add board specific initialization steps throughout the MemoryInit and SiliconInit flows as needed.\r
725 The FspMemoryInit() API is always called before FspMultiPhaseMemInit(); it is the first phase of memory initialization. Similarly,\r
726 the FspSiliconInit() API is always called before FspMultiPhaseSiInit(); it is the first phase of silicon initialization.\r
727 After the first phase, subsequent phases are invoked by calling the FspMultiPhaseMem/SiInit() API.\r
728 The FspMultiPhaseMemInit() API may only be called after the FspMemoryInit() API and before the FspSiliconInit() API;\r
729 or in the case that FSP-T is being used, before the TempRamExit() API. The FspMultiPhaseSiInit() API may only be called after\r
730 the FspSiliconInit() API and before NotifyPhase() API; or in the case that FSP-I is being used, before the FspSmmInit() API.\r
731 The multi-phase APIs may not be called at any other time.\r
732\r
733 @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:\r
734 FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain\r
735 how many phases supported by FSP.\r
736 For action - EnumMultiPhaseExecutePhase:\r
737 FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.\r
738 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
739 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
740 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
741 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
742 @retval FSP_STATUS_RESET_REQUIRED_* A reset is required. These status codes will not be returned during S3.\r
743 @retval FSP_STATUS_VARIABLE_REQUEST A variable request has been made by FSP that needs boot loader handling.\r
744**/\r
745typedef\r
746EFI_STATUS\r
747(EFIAPI *FSP_MULTI_PHASE_INIT)(\r
748 IN FSP_MULTI_PHASE_PARAMS *MultiPhaseInitParamPtr\r
749 );\r
750\r
cf1d4549 751#endif\r
EFI Development Kit II mirror for PVE