]> git.proxmox.com Git - mirror_edk2.git/blame - IntelFsp2Pkg/Include/FspEas/FspApi.h
IntelFsp2Pkg: Support 64bit FspResetType for X64 build.
[mirror_edk2.git] / IntelFsp2Pkg / Include / FspEas / FspApi.h
CommitLineData
cf1d4549
JY
1/** @file\r
2 Intel FSP API definition from Intel Firmware Support Package External\r
f2cdb268 3 Architecture Specification v2.0 - v2.2\r
cf1d4549 4\r
6f219bef 5 Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
9672cd30 6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
cf1d4549
JY
7\r
8**/\r
9\r
10#ifndef _FSP_API_H_\r
11#define _FSP_API_H_\r
12\r
f2cdb268 13#include <Pi/PiStatusCode.h>\r
140446cd 14#include <Base.h>\r
f2cdb268 15\r
19089568
GM
16///\r
17/// FSP Reset Status code\r
140446cd 18/// These are defined in FSP EAS v2.4 section 13.2.2 - OEM Status Code\r
19089568 19/// @{\r
140446cd
CC
20\r
21#define ENCODE_RESET_REQUEST(ResetType) \\r
22 ((EFI_STATUS)((MAX_BIT >> 1) | (ResetType)))\r
23#define FSP_STATUS_RESET_REQUIRED_COLD ENCODE_RESET_REQUEST(1)\r
24#define FSP_STATUS_RESET_REQUIRED_WARM ENCODE_RESET_REQUEST(2)\r
25#define FSP_STATUS_RESET_REQUIRED_3 ENCODE_RESET_REQUEST(3)\r
26#define FSP_STATUS_RESET_REQUIRED_4 ENCODE_RESET_REQUEST(4)\r
27#define FSP_STATUS_RESET_REQUIRED_5 ENCODE_RESET_REQUEST(5)\r
28#define FSP_STATUS_RESET_REQUIRED_6 ENCODE_RESET_REQUEST(6)\r
29#define FSP_STATUS_RESET_REQUIRED_7 ENCODE_RESET_REQUEST(7)\r
30#define FSP_STATUS_RESET_REQUIRED_8 ENCODE_RESET_REQUEST(8)\r
31#define FSP_STATUS_VARIABLE_REQUEST ENCODE_RESET_REQUEST(10)\r
19089568
GM
32/// @}\r
33\r
f2cdb268
CC
34///\r
35/// FSP Event related definition.\r
36///\r
111f2228
MK
37#define FSP_EVENT_CODE 0xF5000000\r
38#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)\r
f2cdb268
CC
39\r
40/*\r
41 FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.\r
42 These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the\r
43 status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3.\r
44\r
45 @param[in] Type Indicates the type of event being reported.\r
46 See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE.\r
47 @param[in] Value Describes the current status of a hardware or software entity.\r
48 This includes information about the class and subclass that is used to classify the entity as well as an operation.\r
49 For progress events, the operation is the current activity. For error events, it is the exception.\r
50 For debug events, it is not defined at this time.\r
51 See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE.\r
52 @param[in] Instance The enumeration of a hardware or software entity within the system.\r
53 A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them.\r
54 An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant.\r
55 Valid instance numbers start with 1.\r
56 @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event.\r
57 This parameter may be NULL.\r
58 @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data.\r
59 For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages.\r
60 This parameter is NULL when no additional data is provided.\r
61\r
62 @retval EFI_SUCCESS The event was handled successfully.\r
63 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
64 @retval EFI_DEVICE_ERROR The event handler failed.\r
65*/\r
66typedef\r
67EFI_STATUS\r
111f2228 68(EFIAPI *FSP_EVENT_HANDLER)(\r
f2cdb268
CC
69 IN EFI_STATUS_CODE_TYPE Type,\r
70 IN EFI_STATUS_CODE_VALUE Value,\r
71 IN UINT32 Instance,\r
72 IN OPTIONAL EFI_GUID *CallerId,\r
73 IN OPTIONAL EFI_STATUS_CODE_DATA *Data\r
74 );\r
75\r
76/*\r
77 Handler for FSP-T debug log messages, provided by the bootloader.\r
78\r
79 @param[in] DebugMessage A pointer to the debug message to be written to the log.\r
80 @param[in] MessageLength Number of bytes to written to the debug log.\r
81\r
82 @retval UINT32 The return value indicates the number of bytes actually written to\r
83 the debug log. If the return value is less than MessageLength,\r
84 an error occurred.\r
85*/\r
86typedef\r
87UINT32\r
111f2228
MK
88(EFIAPI *FSP_DEBUG_HANDLER)(\r
89 IN CHAR8 *DebugMessage,\r
f2cdb268
CC
90 IN UINT32 MessageLength\r
91 );\r
92\r
cf1d4549 93#pragma pack(1)\r
6d0ac988
JY
94///\r
95/// FSP_UPD_HEADER Configuration.\r
96///\r
cf1d4549
JY
97typedef struct {\r
98 ///\r
99 /// UPD Region Signature. This signature will be\r
100 /// "XXXXXX_T" for FSP-T\r
101 /// "XXXXXX_M" for FSP-M\r
102 /// "XXXXXX_S" for FSP-S\r
103 /// Where XXXXXX is an unique signature\r
104 ///\r
111f2228 105 UINT64 Signature;\r
cf1d4549 106 ///\r
89f569ae
CC
107 /// Revision of the Data structure.\r
108 /// For FSP spec 2.0/2.1 value is 1.\r
109 /// For FSP spec 2.2 value is 2.\r
cf1d4549 110 ///\r
111f2228
MK
111 UINT8 Revision;\r
112 UINT8 Reserved[23];\r
cf1d4549
JY
113} FSP_UPD_HEADER;\r
114\r
89f569ae
CC
115///\r
116/// FSPT_ARCH_UPD Configuration.\r
117///\r
118typedef struct {\r
119 ///\r
6f219bef 120 /// Revision of the structure is 1 for this version of the specification.\r
89f569ae 121 ///\r
111f2228
MK
122 UINT8 Revision;\r
123 UINT8 Reserved[3];\r
89f569ae 124 ///\r
6f219bef 125 /// Length of the structure in bytes. The current value for this field is 32.\r
89f569ae 126 ///\r
111f2228 127 UINT32 Length;\r
89f569ae
CC
128 ///\r
129 /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r
130 /// occurring during FSP execution.\r
131 ///\r
111f2228
MK
132 FSP_DEBUG_HANDLER FspDebugHandler;\r
133 UINT8 Reserved1[20];\r
89f569ae
CC
134} FSPT_ARCH_UPD;\r
135\r
6f219bef
TK
136///\r
137/// FSPT_ARCH2_UPD Configuration.\r
138///\r
139typedef struct {\r
140 ///\r
141 /// Revision of the structure is 2 for this version of the specification.\r
142 ///\r
140446cd
CC
143 UINT8 Revision;\r
144 UINT8 Reserved[3];\r
6f219bef
TK
145 ///\r
146 /// Length of the structure in bytes. The current value for this field is 32.\r
147 ///\r
140446cd 148 UINT32 Length;\r
6f219bef
TK
149 ///\r
150 /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r
151 /// occurring during FSP execution.\r
152 ///\r
140446cd
CC
153 EFI_PHYSICAL_ADDRESS FspDebugHandler;\r
154 UINT8 Reserved1[16];\r
6f219bef
TK
155} FSPT_ARCH2_UPD;\r
156\r
6d0ac988
JY
157///\r
158/// FSPM_ARCH_UPD Configuration.\r
159///\r
cf1d4549
JY
160typedef struct {\r
161 ///\r
162 /// Revision of the structure. For FSP v2.0 value is 1.\r
163 ///\r
111f2228
MK
164 UINT8 Revision;\r
165 UINT8 Reserved[3];\r
cf1d4549
JY
166 ///\r
167 /// Pointer to the non-volatile storage (NVS) data buffer.\r
168 /// If it is NULL it indicates the NVS data is not available.\r
169 ///\r
111f2228 170 VOID *NvsBufferPtr;\r
cf1d4549
JY
171 ///\r
172 /// Pointer to the temporary stack base address to be\r
173 /// consumed inside FspMemoryInit() API.\r
174 ///\r
111f2228 175 VOID *StackBase;\r
cf1d4549
JY
176 ///\r
177 /// Temporary stack size to be consumed inside\r
178 /// FspMemoryInit() API.\r
179 ///\r
111f2228 180 UINT32 StackSize;\r
cf1d4549
JY
181 ///\r
182 /// Size of memory to be reserved by FSP below "top\r
183 /// of low usable memory" for bootloader usage.\r
184 ///\r
111f2228 185 UINT32 BootLoaderTolumSize;\r
cf1d4549
JY
186 ///\r
187 /// Current boot mode.\r
188 ///\r
111f2228 189 UINT32 BootMode;\r
f2cdb268
CC
190 ///\r
191 /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r
192 /// This value is only valid if Revision is >= 2.\r
193 ///\r
111f2228
MK
194 FSP_EVENT_HANDLER *FspEventHandler;\r
195 UINT8 Reserved1[4];\r
cf1d4549
JY
196} FSPM_ARCH_UPD;\r
197\r
6f219bef
TK
198///\r
199/// FSPM_ARCH2_UPD Configuration.\r
200///\r
201typedef struct {\r
202 ///\r
203 /// Revision of the structure is 3 for this version of the specification.\r
204 ///\r
140446cd
CC
205 UINT8 Revision;\r
206 UINT8 Reserved[3];\r
6f219bef
TK
207 ///\r
208 /// Length of the structure in bytes. The current value for this field is 64.\r
209 ///\r
140446cd 210 UINT32 Length;\r
6f219bef
TK
211 ///\r
212 /// Pointer to the temporary stack base address to be\r
213 /// consumed inside FspMemoryInit() API.\r
214 ///\r
140446cd 215 EFI_PHYSICAL_ADDRESS StackBase;\r
6f219bef
TK
216 ///\r
217 /// Temporary stack size to be consumed inside\r
218 /// FspMemoryInit() API.\r
219 ///\r
140446cd 220 UINT64 StackSize;\r
6f219bef
TK
221 ///\r
222 /// Size of memory to be reserved by FSP below "top\r
223 /// of low usable memory" for bootloader usage.\r
224 ///\r
140446cd 225 UINT32 BootLoaderTolumSize;\r
6f219bef
TK
226 ///\r
227 /// Current boot mode.\r
228 ///\r
140446cd 229 UINT32 BootMode;\r
6f219bef
TK
230 ///\r
231 /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r
232 /// This value is only valid if Revision is >= 2.\r
233 ///\r
140446cd
CC
234 EFI_PHYSICAL_ADDRESS FspEventHandler;\r
235 UINT8 Reserved1[24];\r
6f219bef
TK
236} FSPM_ARCH2_UPD;\r
237\r
238///\r
239/// FSPS_ARCH_UPD Configuration.\r
240///\r
89f569ae
CC
241typedef struct {\r
242 ///\r
6f219bef 243 /// Revision of the structure is 1 for this version of the specification.\r
89f569ae 244 ///\r
111f2228
MK
245 UINT8 Revision;\r
246 UINT8 Reserved[3];\r
89f569ae 247 ///\r
6f219bef 248 /// Length of the structure in bytes. The current value for this field is 32.\r
89f569ae 249 ///\r
111f2228 250 UINT32 Length;\r
89f569ae
CC
251 ///\r
252 /// FspEventHandler Optional event handler for the bootloader to be informed of events\r
253 /// occurring during FSP execution.\r
254 ///\r
111f2228 255 FSP_EVENT_HANDLER FspEventHandler;\r
89f569ae
CC
256 ///\r
257 /// A FSP binary may optionally implement multi-phase silicon initialization,\r
258 /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER\r
259 /// is non-zero.\r
260 /// To enable multi-phase silicon initialization, the bootloader must set\r
261 /// EnableMultiPhaseSiliconInit to a non-zero value.\r
262 ///\r
111f2228
MK
263 UINT8 EnableMultiPhaseSiliconInit;\r
264 UINT8 Reserved1[19];\r
89f569ae
CC
265} FSPS_ARCH_UPD;\r
266\r
6f219bef
TK
267///\r
268/// FSPS_ARCH2_UPD Configuration.\r
269///\r
270typedef struct {\r
271 ///\r
272 /// Revision of the structure is 2 for this version of the specification.\r
273 ///\r
140446cd
CC
274 UINT8 Revision;\r
275 UINT8 Reserved[3];\r
6f219bef
TK
276 ///\r
277 /// Length of the structure in bytes. The current value for this field is 32.\r
278 ///\r
140446cd 279 UINT32 Length;\r
6f219bef
TK
280 ///\r
281 /// FspEventHandler Optional event handler for the bootloader to be informed of events\r
282 /// occurring during FSP execution.\r
283 ///\r
140446cd
CC
284 EFI_PHYSICAL_ADDRESS FspEventHandler;\r
285 UINT8 Reserved1[16];\r
6f219bef
TK
286} FSPS_ARCH2_UPD;\r
287\r
6d0ac988
JY
288///\r
289/// FSPT_UPD_COMMON Configuration.\r
290///\r
cf1d4549 291typedef struct {\r
6d0ac988
JY
292 ///\r
293 /// FSP_UPD_HEADER Configuration.\r
294 ///\r
111f2228 295 FSP_UPD_HEADER FspUpdHeader;\r
cf1d4549
JY
296} FSPT_UPD_COMMON;\r
297\r
89f569ae
CC
298///\r
299/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r
300///\r
301typedef struct {\r
302 ///\r
303 /// FSP_UPD_HEADER Configuration.\r
304 ///\r
111f2228 305 FSP_UPD_HEADER FspUpdHeader;\r
89f569ae
CC
306\r
307 ///\r
308 /// FSPT_ARCH_UPD Configuration.\r
309 ///\r
111f2228 310 FSPT_ARCH_UPD FsptArchUpd;\r
89f569ae
CC
311} FSPT_UPD_COMMON_FSP22;\r
312\r
6f219bef
TK
313///\r
314/// FSPT_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
315///\r
316typedef struct {\r
317 ///\r
318 /// FSP_UPD_HEADER Configuration.\r
319 ///\r
320 FSP_UPD_HEADER FspUpdHeader;\r
321\r
322 ///\r
323 /// FSPT_ARCH2_UPD Configuration.\r
324 ///\r
325 FSPT_ARCH2_UPD FsptArchUpd;\r
326} FSPT_UPD_COMMON_FSP24;\r
327\r
6d0ac988
JY
328///\r
329/// FSPM_UPD_COMMON Configuration.\r
330///\r
cf1d4549 331typedef struct {\r
6d0ac988
JY
332 ///\r
333 /// FSP_UPD_HEADER Configuration.\r
334 ///\r
111f2228 335 FSP_UPD_HEADER FspUpdHeader;\r
6d0ac988
JY
336 ///\r
337 /// FSPM_ARCH_UPD Configuration.\r
338 ///\r
111f2228 339 FSPM_ARCH_UPD FspmArchUpd;\r
cf1d4549
JY
340} FSPM_UPD_COMMON;\r
341\r
6f219bef
TK
342///\r
343/// FSPM_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
344///\r
345typedef struct {\r
346 ///\r
347 /// FSP_UPD_HEADER Configuration.\r
348 ///\r
349 FSP_UPD_HEADER FspUpdHeader;\r
350 ///\r
351 /// FSPM_ARCH2_UPD Configuration.\r
352 ///\r
353 FSPM_ARCH2_UPD FspmArchUpd;\r
354} FSPM_UPD_COMMON_FSP24;\r
355\r
6d0ac988
JY
356///\r
357/// FSPS_UPD_COMMON Configuration.\r
358///\r
cf1d4549 359typedef struct {\r
6d0ac988
JY
360 ///\r
361 /// FSP_UPD_HEADER Configuration.\r
362 ///\r
111f2228 363 FSP_UPD_HEADER FspUpdHeader;\r
cf1d4549
JY
364} FSPS_UPD_COMMON;\r
365\r
89f569ae
CC
366///\r
367/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r
368///\r
369typedef struct {\r
370 ///\r
371 /// FSP_UPD_HEADER Configuration.\r
372 ///\r
111f2228 373 FSP_UPD_HEADER FspUpdHeader;\r
89f569ae
CC
374\r
375 ///\r
376 /// FSPS_ARCH_UPD Configuration.\r
377 ///\r
111f2228 378 FSPS_ARCH_UPD FspsArchUpd;\r
89f569ae
CC
379} FSPS_UPD_COMMON_FSP22;\r
380\r
6f219bef
TK
381///\r
382/// FSPS_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
383///\r
384typedef struct {\r
385 ///\r
386 /// FSP_UPD_HEADER Configuration.\r
387 ///\r
388 FSP_UPD_HEADER FspUpdHeader;\r
389\r
390 ///\r
391 /// FSPS_ARCH2_UPD Configuration.\r
392 ///\r
393 FSPS_ARCH2_UPD FspsArchUpd;\r
394} FSPS_UPD_COMMON_FSP24;\r
395\r
6d0ac988
JY
396///\r
397/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.\r
398///\r
cf1d4549
JY
399typedef enum {\r
400 ///\r
401 /// This stage is notified when the bootloader completes the\r
402 /// PCI enumeration and the resource allocation for the\r
403 /// PCI devices is complete.\r
404 ///\r
405 EnumInitPhaseAfterPciEnumeration = 0x20,\r
406 ///\r
407 /// This stage is notified just before the bootloader hand-off\r
408 /// to the OS loader.\r
409 ///\r
111f2228 410 EnumInitPhaseReadyToBoot = 0x40,\r
cf1d4549
JY
411 ///\r
412 /// This stage is notified just before the firmware/Preboot\r
413 /// environment transfers management of all system resources\r
414 /// to the OS or next level execution environment.\r
415 ///\r
111f2228 416 EnumInitPhaseEndOfFirmware = 0xF0\r
cf1d4549
JY
417} FSP_INIT_PHASE;\r
418\r
6d0ac988
JY
419///\r
420/// Definition of NOTIFY_PHASE_PARAMS.\r
421///\r
cf1d4549
JY
422typedef struct {\r
423 ///\r
424 /// Notification phase used for NotifyPhase API\r
425 ///\r
111f2228 426 FSP_INIT_PHASE Phase;\r
cf1d4549
JY
427} NOTIFY_PHASE_PARAMS;\r
428\r
f2cdb268
CC
429///\r
430/// Action definition for FspMultiPhaseSiInit API\r
431///\r
432typedef enum {\r
111f2228
MK
433 EnumMultiPhaseGetNumberOfPhases = 0x0,\r
434 EnumMultiPhaseExecutePhase = 0x1\r
f2cdb268
CC
435} FSP_MULTI_PHASE_ACTION;\r
436\r
437///\r
438/// Data structure returned by FSP when bootloader calling\r
439/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)\r
440///\r
441typedef struct {\r
111f2228
MK
442 UINT32 NumberOfPhases;\r
443 UINT32 PhasesExecuted;\r
f2cdb268
CC
444} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;\r
445\r
446///\r
447/// FspMultiPhaseSiInit function parameter.\r
448///\r
449/// For action 0 (EnumMultiPhaseGetNumberOfPhases):\r
450/// - PhaseIndex must be 0.\r
451/// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS.\r
452///\r
453/// For action 1 (EnumMultiPhaseExecutePhase):\r
454/// - PhaseIndex will be the phase that will be executed by FSP.\r
455/// - MultiPhaseParamPtr shall be NULL.\r
456///\r
457typedef struct {\r
111f2228
MK
458 IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;\r
459 IN UINT32 PhaseIndex;\r
460 IN OUT VOID *MultiPhaseParamPtr;\r
f2cdb268
CC
461} FSP_MULTI_PHASE_PARAMS;\r
462\r
cf1d4549
JY
463#pragma pack()\r
464\r
465/**\r
466 This FSP API is called soon after coming out of reset and before memory and stack is\r
467 available. This FSP API will load the microcode update, enable code caching for the\r
468 region specified by the boot loader and also setup a temporary stack to be used until\r
469 main memory is initialized.\r
470\r
471 A hardcoded stack can be set up with the following values, and the "esp" register\r
472 initialized to point to this hardcoded stack.\r
473 1. The return address where the FSP will return control after setting up a temporary\r
474 stack.\r
475 2. A pointer to the input parameter structure\r
476\r
477 However, since the stack is in ROM and not writeable, this FSP API cannot be called\r
478 using the "call" instruction, but needs to be jumped to.\r
479\r
480 @param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure.\r
481\r
482 @retval EFI_SUCCESS Temporary RAM was initialized successfully.\r
483 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
484 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
485 @retval EFI_DEVICE_ERROR Temp RAM initialization failed.\r
486\r
487 If this function is successful, the FSP initializes the ECX and EDX registers to point to\r
488 a temporary but writeable memory range available to the boot loader and returns with\r
489 FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary\r
490 memory range and EDX points to the end of the range. Boot loader is free to use the\r
491 whole range described. Typically the boot loader can reload the ESP register to point\r
492 to the end of this returned range so that it can be used as a standard stack.\r
493**/\r
494typedef\r
495EFI_STATUS\r
111f2228 496(EFIAPI *FSP_TEMP_RAM_INIT)(\r
cf1d4549
JY
497 IN VOID *FsptUpdDataPtr\r
498 );\r
499\r
500/**\r
501 This FSP API is used to notify the FSP about the different phases in the boot process.\r
502 This allows the FSP to take appropriate actions as needed during different initialization\r
503 phases. The phases will be platform dependent and will be documented with the FSP\r
504 release. The current FSP supports two notify phases:\r
505 Post PCI enumeration\r
506 Ready To Boot\r
507\r
508 @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r
509\r
510 @retval EFI_SUCCESS The notification was handled successfully.\r
511 @retval EFI_UNSUPPORTED The notification was not called in the proper order.\r
512 @retval EFI_INVALID_PARAMETER The notification code is invalid.\r
513**/\r
514typedef\r
515EFI_STATUS\r
111f2228 516(EFIAPI *FSP_NOTIFY_PHASE)(\r
cf1d4549
JY
517 IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r
518 );\r
519\r
520/**\r
521 This FSP API is called after TempRamInit and initializes the memory.\r
522 This FSP API accepts a pointer to a data structure that will be platform dependent\r
523 and defined for each FSP binary. This will be documented in Integration guide with\r
524 each FSP release.\r
525 After FspMemInit completes its execution, it passes the pointer to the HobList and\r
e37bb20c 526 returns to the boot loader from where it was called. BootLoader is responsible to\r
91cc60ba 527 migrate its stack and data to Memory.\r
cf1d4549
JY
528 FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
529 complete the silicon initialization and provides bootloader an opportunity to get\r
530 control after system memory is available and before the temporary RAM is torn down.\r
531\r
91cc60ba 532 @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure.\r
cf1d4549
JY
533 @param[out] HobListPtr Pointer to receive the address of the HOB list.\r
534\r
535 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
536 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
537 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
538 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
539 @retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met.\r
540 @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3.\r
541**/\r
542typedef\r
543EFI_STATUS\r
111f2228 544(EFIAPI *FSP_MEMORY_INIT)(\r
cf1d4549
JY
545 IN VOID *FspmUpdDataPtr,\r
546 OUT VOID **HobListPtr\r
547 );\r
548\r
cf1d4549
JY
549/**\r
550 This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary\r
551 memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure\r
552 that will be platform dependent and defined for each FSP binary. This will be\r
553 documented in Integration Guide.\r
554 FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
555 complete the silicon initialization and provides bootloader an opportunity to get\r
556 control after system memory is available and before the temporary RAM is torn down.\r
557\r
558 @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.\r
559 This structure is normally defined in the Integration Guide.\r
560 And if it is not defined in the Integration Guide, pass NULL.\r
561\r
562 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
563 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
564 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
565 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
566**/\r
567typedef\r
568EFI_STATUS\r
111f2228 569(EFIAPI *FSP_TEMP_RAM_EXIT)(\r
cf1d4549
JY
570 IN VOID *TempRamExitParamPtr\r
571 );\r
572\r
cf1d4549
JY
573/**\r
574 This FSP API is called after TempRamExit API.\r
575 FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the\r
576 silicon initialization.\r
577\r
578 @param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure.\r
579 If NULL, FSP will use the default parameters.\r
580\r
581 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
582 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
583 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
584 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
91cc60ba 585 @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
cf1d4549
JY
586**/\r
587typedef\r
588EFI_STATUS\r
111f2228 589(EFIAPI *FSP_SILICON_INIT)(\r
cf1d4549
JY
590 IN VOID *FspsUpdDataPtr\r
591 );\r
592\r
f2cdb268
CC
593/**\r
594 This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase.\r
595 This FSP API provides multi-phase silicon initialization; which brings greater modularity\r
596 beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an\r
597 extra API to FSP-S. This allows the bootloader to add board specific initialization steps\r
598 throughout the SiliconInit flow as needed.\r
599\r
600 @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:\r
601 FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain\r
602 how many phases supported by FSP.\r
603 For action - EnumMultiPhaseExecutePhase:\r
604 FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.\r
605 @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
606 @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
607 @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
608 @retval EFI_DEVICE_ERROR FSP initialization failed.\r
609 @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
610**/\r
611typedef\r
612EFI_STATUS\r
111f2228 613(EFIAPI *FSP_MULTI_PHASE_SI_INIT)(\r
f2cdb268 614 IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr\r
111f2228 615 );\r
f2cdb268 616\r
cf1d4549 617#endif\r