[mirror_edk2.git] / IntelFsp2WrapperPkg / IntelFsp2WrapperPkg.dec

## @file\r
# Provides drivers and definitions to support fsp in EDKII bios.\r
#\r
# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = IntelFsp2WrapperPkg\r
  PACKAGE_GUID                   = FAFE06D4-7245-42D7-9FD2-E5D5E36AB0A0\r
  PACKAGE_VERSION                = 0.1\r
\r
[Includes]\r
  Include\r
\r
[LibraryClasses]\r
  ##  @libraryclass  Provide FSP API related function.\r
  FspWrapperApiLib|Include/Library/FspWrapperApiLib.h\r
  FspWrapperApiTestLib|Include/Library/FspWrapperApiTestLib.h\r
\r
  ##  @libraryclass  Provide FSP hob process related function.\r
  FspWrapperHobProcessLib|Include/Library/FspWrapperHobProcessLib.h\r
\r
  ##  @libraryclass  Provide FSP platform related function.\r
  FspWrapperPlatformLib|Include/Library/FspWrapperPlatformLib.h\r
\r
[Guids]\r
  #\r
  # GUID defined in package\r
  #\r
  gIntelFsp2WrapperTokenSpaceGuid       = { 0xa34cf082, 0xf50, 0x4f0d,  { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }\r
  gFspApiPerformanceGuid                = { 0xc9122295, 0x56ed, 0x4d4e, { 0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40 } }\r
  gFspHobGuid                           = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }\r
\r
[Ppis]\r
  gFspSiliconInitDonePpiGuid            = { 0x4eb6e09c, 0xd256, 0x4e1e, { 0xb5, 0x0a, 0x87, 0x4b, 0xd2, 0x84, 0xb3, 0xde } }\r
  gTopOfTemporaryRamPpiGuid             = { 0x2f3962b2, 0x57c5, 0x44ec, { 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b } }\r
\r
[Protocols]\r
  gAddPerfRecordProtocolGuid            = { 0xc4a58d6d, 0x3677, 0x49cb, { 0xa0, 0x0a, 0x94, 0x70, 0x76, 0x5f, 0xb5, 0x5e } }\r
\r
################################################################################\r
#\r
# PCD Declarations section - list of all PCDs Declared by this Package\r
#                            Only this package should be providing the\r
#                            declaration, other packages should not.\r
#\r
################################################################################\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
  ## Provides the memory mapped base address of the BIOS CodeCache Flash Device.\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001\r
  ## Provides the size of the BIOS Flash Device.\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
\r
  ## Indicates the base address of the first Microcode Patch in the Microcode Region\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006\r
  ## Indicates the offset of the Cpu Microcode.\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007\r
\r
  ## Indicate the PEI memory size platform want to report\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004\r
  ## Indicate the PEI memory size platform want to report\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005\r
\r
  ## This is the base address of FSP-T\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300\r
\r
  ## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>\r
  #  If a bit is set, that means this FSP API is skipped.<BR>\r
  #  If a bit is clear, that means this FSP API is NOT skipped.<BR>\r
  #  NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>\r
  #  BIT[15:0] is for function:<BR>\r
  #    BIT0    - Skip TempRamInit<BR>\r
  #    BIT1    - Skip MemoryInit<BR>\r
  #    BIT2    - Skip TempRamExit<BR>\r
  #    BIT3    - Skip SiliconInit<BR>\r
  #    BIT4    - Skip NotifyPhase<BR>\r
  #  BIT[32:16] is for sub-function:<BR>\r
  #    BIT16   - Skip NotifyPhase (AfterPciEnumeration)<BR>\r
  #    BIT17   - Skip NotifyPhase (ReadyToBoot)<BR>\r
  #    BIT18   - Skip NotifyPhase (EndOfFirmware)<BR>\r
  #  Any undefined BITs are reserved for future use.<BR>\r
  # @Prompt Skip FSP API from FSP wrapper.\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009\r
\r
  ## This PCD decides how Wrapper code utilizes FSP\r
  # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)\r
  # 1: API mode (FSP Wrapper will call FSP API)\r
  #\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0x4000000A\r
\r
[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]\r
  #\r
  ## These are the base address of FSP-M/S\r
  #\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00001000\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001\r
  #\r
  # To provide flexibility for platform to pre-allocate FSP UPD buffer\r
  #\r
  # The PCDs define the pre-allocated FSPM and FSPS UPD Data Buffer Address.\r
  # 0x00000000 - Platform will not pre-allocate UPD buffer before FspWrapper module\r
  # non-zero   - Platform will pre-allocate UPD buffer and patch this value to\r
  #              buffer address before FspWrapper module executing.\r
  #\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000\r
  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001\r
Commit	Line	Data
cf1d4549 JY	1	## @file\r
	2	# Provides drivers and definitions to support fsp in EDKII bios.\r
	3	#\r
cae524cd	4	# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
512e23a3	5	# SPDX-License-Identifier: BSD-2-Clause-Patent\r
cf1d4549 JY	6	#\r
	7	##\r
	8	\r
	9	[Defines]\r
	10	DEC_SPECIFICATION = 0x00010005\r
	11	PACKAGE_NAME = IntelFsp2WrapperPkg\r
	12	PACKAGE_GUID = FAFE06D4-7245-42D7-9FD2-E5D5E36AB0A0\r
	13	PACKAGE_VERSION = 0.1\r
	14	\r
	15	[Includes]\r
	16	Include\r
	17	\r
	18	[LibraryClasses]\r
	19	## @libraryclass Provide FSP API related function.\r
	20	FspWrapperApiLib\|Include/Library/FspWrapperApiLib.h\r
	21	FspWrapperApiTestLib\|Include/Library/FspWrapperApiTestLib.h\r
	22	\r
	23	## @libraryclass Provide FSP hob process related function.\r
	24	FspWrapperHobProcessLib\|Include/Library/FspWrapperHobProcessLib.h\r
	25	\r
	26	## @libraryclass Provide FSP platform related function.\r
	27	FspWrapperPlatformLib\|Include/Library/FspWrapperPlatformLib.h\r
	28	\r
	29	[Guids]\r
	30	#\r
	31	# GUID defined in package\r
	32	#\r
6f6bf5c7	33	gIntelFsp2WrapperTokenSpaceGuid = { 0xa34cf082, 0xf50, 0x4f0d, { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }\r
cf1d4549 JY	34	gFspApiPerformanceGuid = { 0xc9122295, 0x56ed, 0x4d4e, { 0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40 } }\r
	35	gFspHobGuid = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }\r
	36	\r
	37	[Ppis]\r
	38	gFspSiliconInitDonePpiGuid = { 0x4eb6e09c, 0xd256, 0x4e1e, { 0xb5, 0x0a, 0x87, 0x4b, 0xd2, 0x84, 0xb3, 0xde } }\r
	39	gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, { 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b } }\r
	40	\r
	41	[Protocols]\r
	42	gAddPerfRecordProtocolGuid = { 0xc4a58d6d, 0x3677, 0x49cb, { 0xa0, 0x0a, 0x94, 0x70, 0x76, 0x5f, 0xb5, 0x5e } }\r
	43	\r
	44	################################################################################\r
	45	#\r
	46	# PCD Declarations section - list of all PCDs Declared by this Package\r
	47	# Only this package should be providing the\r
	48	# declaration, other packages should not.\r
	49	#\r
	50	################################################################################\r
	51	[PcdsFixedAtBuild, PcdsPatchableInModule]\r
	52	## Provides the memory mapped base address of the BIOS CodeCache Flash Device.\r
6f6bf5c7	53	gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress\|0xFFE00000\|UINT32\|0x10000001\r
cf1d4549	54	## Provides the size of the BIOS Flash Device.\r
6f6bf5c7	55	gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize\|0x00200000\|UINT32\|0x10000002\r
cf1d4549 JY	56	\r
cf1d4549 JY	57	## Indicates the base address of the first Microcode Patch in the Microcode Region\r
6f6bf5c7 JY	58	gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress\|0x0\|UINT64\|0x10000005\r
6f6bf5c7 JY	59	gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize\|0x0\|UINT64\|0x10000006\r
cf1d4549	60	## Indicates the offset of the Cpu Microcode.\r
6f6bf5c7	61	gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset\|0x90\|UINT32\|0x10000007\r
cf1d4549 JY	62	\r
cf1d4549 JY	63	## Indicate the PEI memory size platform want to report\r
6f6bf5c7	64	gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize\|0x1800000\|UINT32\|0x40000004\r
cf1d4549	65	## Indicate the PEI memory size platform want to report\r
6f6bf5c7	66	gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize\|0x3000000\|UINT32\|0x40000005\r
cf1d4549	67	\r
2098de62	68	## This is the base address of FSP-T\r
6f6bf5c7	69	gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress\|0x00000000\|UINT32\|0x00000300\r
6d40ea81	70	\r
4d4b8169 DG	71	## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>\r
	72	# If a bit is set, that means this FSP API is skipped.<BR>\r
	73	# If a bit is clear, that means this FSP API is NOT skipped.<BR>\r
	74	# NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>\r
	75	# BIT[15:0] is for function:<BR>\r
	76	# BIT0 - Skip TempRamInit<BR>\r
	77	# BIT1 - Skip MemoryInit<BR>\r
	78	# BIT2 - Skip TempRamExit<BR>\r
	79	# BIT3 - Skip SiliconInit<BR>\r
	80	# BIT4 - Skip NotifyPhase<BR>\r
	81	# BIT[32:16] is for sub-function:<BR>\r
	82	# BIT16 - Skip NotifyPhase (AfterPciEnumeration)<BR>\r
	83	# BIT17 - Skip NotifyPhase (ReadyToBoot)<BR>\r
	84	# BIT18 - Skip NotifyPhase (EndOfFirmware)<BR>\r
	85	# Any undefined BITs are reserved for future use.<BR>\r
	86	# @Prompt Skip FSP API from FSP wrapper.\r
	87	gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi\|0x00000000\|UINT32\|0x40000009\r
	88	\r
2098de62 CC	89	## This PCD decides how Wrapper code utilizes FSP\r
	90	# 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)\r
	91	# 1: API mode (FSP Wrapper will call FSP API)\r
	92	#\r
	93	gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection\|0x00000001\|UINT8\|0x4000000A\r
	94	\r
6d40ea81	95	[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]\r
2098de62 CC	96	#\r
	97	## These are the base address of FSP-M/S\r
	98	#\r
	99	gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress\|0x00000000\|UINT32\|0x00001000\r
6d40ea81	100	gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress\|0x00000000\|UINT32\|0x00001001\r
e69dcef5 CC	101	#\r
	102	# To provide flexibility for platform to pre-allocate FSP UPD buffer\r
	103	#\r
	104	# The PCDs define the pre-allocated FSPM and FSPS UPD Data Buffer Address.\r
	105	# 0x00000000 - Platform will not pre-allocate UPD buffer before FspWrapper module\r
	106	# non-zero - Platform will pre-allocate UPD buffer and patch this value to\r
	107	# buffer address before FspWrapper module executing.\r
	108	#\r
	109	gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress\|0x00000000\|UINT32\|0x50000000\r
cae524cd	110	gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress\|0x00000000\|UINT32\|0x50000001\r