[mirror_edk2.git] / IntelFsp2WrapperPkg / Library / BaseFspWrapperApiLib / FspWrapperApiLib.c

/** @file\r
  Provide FSP API related function.\r
\r
  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <PiPei.h>\r
\r
#include <Library/FspWrapperApiLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
\r
/**\r
  Wrapper for a thunk to transition from long mode to compatibility mode to execute 32-bit code and then transit back to\r
  long mode.\r
\r
  @param[in] Function     The 32bit code entry to be executed.\r
  @param[in] Param1       The first parameter to pass to 32bit code.\r
  @param[in] Param2       The second parameter to pass to 32bit code.\r
\r
  @return EFI_STATUS.\r
**/\r
EFI_STATUS\r
Execute32BitCode (\r
  IN UINT64  Function,\r
  IN UINT64  Param1,\r
  IN UINT64  Param2\r
  );\r
\r
/**\r
  Wrapper to execute 64-bit code directly from long mode.\r
\r
  @param[in] Function     The 64bit code entry to be executed.\r
  @param[in] Param1       The first parameter to pass to 64bit code.\r
  @param[in] Param2       The second parameter to pass to 64bit code.\r
\r
  @return EFI_STATUS.\r
**/\r
EFI_STATUS\r
Execute64BitCode (\r
  IN UINT64  Function,\r
  IN UINT64  Param1,\r
  IN UINT64  Param2\r
  );\r
\r
/**\r
  Find FSP header pointer.\r
\r
  @param[in] FlashFvFspBase Flash address of FSP FV.\r
\r
  @return FSP header pointer.\r
**/\r
FSP_INFO_HEADER *\r
EFIAPI\r
FspFindFspHeader (\r
  IN EFI_PHYSICAL_ADDRESS  FlashFvFspBase\r
  )\r
{\r
  UINT8  *CheckPointer;\r
\r
  CheckPointer = (UINT8 *)(UINTN)FlashFvFspBase;\r
\r
  if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->Signature != EFI_FVH_SIGNATURE) {\r
    return NULL;\r
  }\r
\r
  if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset != 0) {\r
    CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset;\r
    CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)CheckPointer)->ExtHeaderSize;\r
    CheckPointer = (UINT8 *)ALIGN_POINTER (CheckPointer, 8);\r
  } else {\r
    CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->HeaderLength;\r
  }\r
\r
  CheckPointer = CheckPointer + sizeof (EFI_FFS_FILE_HEADER);\r
\r
  if (((EFI_RAW_SECTION *)CheckPointer)->Type != EFI_SECTION_RAW) {\r
    return NULL;\r
  }\r
\r
  CheckPointer = CheckPointer + sizeof (EFI_RAW_SECTION);\r
\r
  return (FSP_INFO_HEADER *)CheckPointer;\r
}\r
\r
/**\r
  Call FSP API - FspNotifyPhase.\r
\r
  @param[in] NotifyPhaseParams Address pointer to the NOTIFY_PHASE_PARAMS structure.\r
\r
  @return EFI status returned by FspNotifyPhase API.\r
**/\r
EFI_STATUS\r
EFIAPI\r
CallFspNotifyPhase (\r
  IN NOTIFY_PHASE_PARAMS  *NotifyPhaseParams\r
  )\r
{\r
  FSP_INFO_HEADER   *FspHeader;\r
  FSP_NOTIFY_PHASE  NotifyPhaseApi;\r
  EFI_STATUS        Status;\r
  BOOLEAN           InterruptState;\r
\r
  FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspsBaseAddress));\r
  if (FspHeader == NULL) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset);\r
  InterruptState = SaveAndDisableInterrupts ();\r
  if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
    Status = Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams, (UINTN)NULL);\r
  } else {\r
    Status = Execute64BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams, (UINTN)NULL);\r
  }\r
  SetInterruptState (InterruptState);\r
\r
  return Status;\r
}\r
\r
/**\r
  Call FSP API - FspMemoryInit.\r
\r
  @param[in]  FspmUpdDataPtr Address pointer to the FSP_MEMORY_INIT_PARAMS structure.\r
  @param[out] HobListPtr     Address of the HobList pointer.\r
\r
  @return EFI status returned by FspMemoryInit API.\r
**/\r
EFI_STATUS\r
EFIAPI\r
CallFspMemoryInit (\r
  IN VOID   *FspmUpdDataPtr,\r
  OUT VOID  **HobListPtr\r
  )\r
{\r
  FSP_INFO_HEADER  *FspHeader;\r
  FSP_MEMORY_INIT  FspMemoryInitApi;\r
  EFI_STATUS       Status;\r
  BOOLEAN          InterruptState;\r
\r
  FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));\r
  if (FspHeader == NULL) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset);\r
  InterruptState   = SaveAndDisableInterrupts ();\r
  if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
    Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);\r
  } else {\r
    Status = Execute64BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);\r
  }\r
  SetInterruptState (InterruptState);\r
\r
  return Status;\r
}\r
\r
/**\r
  Call FSP API - TempRamExit.\r
\r
  @param[in] TempRamExitParam    Address pointer to the TempRamExit parameters structure.\r
\r
  @return EFI status returned by TempRamExit API.\r
**/\r
EFI_STATUS\r
EFIAPI\r
CallTempRamExit (\r
  IN VOID  *TempRamExitParam\r
  )\r
{\r
  FSP_INFO_HEADER    *FspHeader;\r
  FSP_TEMP_RAM_EXIT  TempRamExitApi;\r
  EFI_STATUS         Status;\r
  BOOLEAN            InterruptState;\r
\r
  FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));\r
  if (FspHeader == NULL) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset);\r
  InterruptState = SaveAndDisableInterrupts ();\r
  if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
    Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam, (UINTN)NULL);\r
  } else {\r
    Status = Execute64BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam, (UINTN)NULL);\r
  }\r
  SetInterruptState (InterruptState);\r
\r
  return Status;\r
}\r
\r
/**\r
  Call FSP API - FspSiliconInit.\r
\r
  @param[in] FspsUpdDataPtr Address pointer to the Silicon Init parameters structure.\r
\r
  @return EFI status returned by FspSiliconInit API.\r
**/\r
EFI_STATUS\r
EFIAPI\r
CallFspSiliconInit (\r
  IN VOID  *FspsUpdDataPtr\r
  )\r
{\r
  FSP_INFO_HEADER   *FspHeader;\r
  FSP_SILICON_INIT  FspSiliconInitApi;\r
  EFI_STATUS        Status;\r
  BOOLEAN           InterruptState;\r
\r
  FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspsBaseAddress));\r
  if (FspHeader == NULL) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset);\r
  InterruptState    = SaveAndDisableInterrupts ();\r
  if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
    Status = Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdDataPtr, (UINTN)NULL);\r
  } else {\r
    Status = Execute64BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdDataPtr, (UINTN)NULL);\r
  }\r
  SetInterruptState (InterruptState);\r
\r
  return Status;\r
}\r
Commit	Line	Data
cf1d4549 JY	1	/** @file\r
	2	Provide FSP API related function.\r
	3	\r
86a2f3c4	4	Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
512e23a3	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
cf1d4549 JY	6	\r
	7	**/\r
	8	\r
	9	#include <PiPei.h>\r
	10	\r
	11	#include <Library/FspWrapperApiLib.h>\r
	12	#include <Library/BaseLib.h>\r
	13	#include <Library/BaseMemoryLib.h>\r
	14	\r
	15	/**\r
86a2f3c4	16	Wrapper for a thunk to transition from long mode to compatibility mode to execute 32-bit code and then transit back to\r
cf1d4549 JY	17	long mode.\r
	18	\r
	19	@param[in] Function The 32bit code entry to be executed.\r
	20	@param[in] Param1 The first parameter to pass to 32bit code.\r
	21	@param[in] Param2 The second parameter to pass to 32bit code.\r
	22	\r
	23	@return EFI_STATUS.\r
	24	**/\r
	25	EFI_STATUS\r
	26	Execute32BitCode (\r
7c7184e2 MK	27	IN UINT64 Function,\r
	28	IN UINT64 Param1,\r
	29	IN UINT64 Param2\r
cf1d4549 JY	30	);\r
cf1d4549 JY	31	\r
86a2f3c4 TK	32	/**\r
	33	Wrapper to execute 64-bit code directly from long mode.\r
	34	\r
	35	@param[in] Function The 64bit code entry to be executed.\r
	36	@param[in] Param1 The first parameter to pass to 64bit code.\r
	37	@param[in] Param2 The second parameter to pass to 64bit code.\r
	38	\r
	39	@return EFI_STATUS.\r
	40	**/\r
	41	EFI_STATUS\r
	42	Execute64BitCode (\r
	43	IN UINT64 Function,\r
	44	IN UINT64 Param1,\r
	45	IN UINT64 Param2\r
	46	);\r
	47	\r
cf1d4549 JY	48	/**\r
	49	Find FSP header pointer.\r
	50	\r
	51	@param[in] FlashFvFspBase Flash address of FSP FV.\r
	52	\r
	53	@return FSP header pointer.\r
	54	**/\r
	55	FSP_INFO_HEADER *\r
	56	EFIAPI\r
	57	FspFindFspHeader (\r
	58	IN EFI_PHYSICAL_ADDRESS FlashFvFspBase\r
	59	)\r
	60	{\r
7c7184e2	61	UINT8 *CheckPointer;\r
cf1d4549	62	\r
7c7184e2	63	CheckPointer = (UINT8 *)(UINTN)FlashFvFspBase;\r
cf1d4549 JY	64	\r
	65	if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->Signature != EFI_FVH_SIGNATURE) {\r
	66	return NULL;\r
	67	}\r
	68	\r
	69	if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset != 0) {\r
	70	CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset;\r
	71	CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)CheckPointer)->ExtHeaderSize;\r
7c7184e2	72	CheckPointer = (UINT8 *)ALIGN_POINTER (CheckPointer, 8);\r
cf1d4549 JY	73	} else {\r
	74	CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->HeaderLength;\r
	75	}\r
	76	\r
cf1d4549 JY	77	CheckPointer = CheckPointer + sizeof (EFI_FFS_FILE_HEADER);\r
	78	\r
	79	if (((EFI_RAW_SECTION *)CheckPointer)->Type != EFI_SECTION_RAW) {\r
	80	return NULL;\r
	81	}\r
	82	\r
	83	CheckPointer = CheckPointer + sizeof (EFI_RAW_SECTION);\r
	84	\r
	85	return (FSP_INFO_HEADER *)CheckPointer;\r
	86	}\r
	87	\r
	88	/**\r
	89	Call FSP API - FspNotifyPhase.\r
	90	\r
	91	@param[in] NotifyPhaseParams Address pointer to the NOTIFY_PHASE_PARAMS structure.\r
	92	\r
	93	@return EFI status returned by FspNotifyPhase API.\r
	94	**/\r
	95	EFI_STATUS\r
	96	EFIAPI\r
	97	CallFspNotifyPhase (\r
7c7184e2	98	IN NOTIFY_PHASE_PARAMS *NotifyPhaseParams\r
cf1d4549 JY	99	)\r
cf1d4549 JY	100	{\r
7c7184e2 MK	101	FSP_INFO_HEADER *FspHeader;\r
	102	FSP_NOTIFY_PHASE NotifyPhaseApi;\r
	103	EFI_STATUS Status;\r
	104	BOOLEAN InterruptState;\r
cf1d4549 JY	105	\r
	106	FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspsBaseAddress));\r
	107	if (FspHeader == NULL) {\r
	108	return EFI_DEVICE_ERROR;\r
	109	}\r
	110	\r
d953f4f1	111	NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset);\r
cf1d4549	112	InterruptState = SaveAndDisableInterrupts ();\r
86a2f3c4 TK	113	if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
	114	Status = Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams, (UINTN)NULL);\r
	115	} else {\r
	116	Status = Execute64BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams, (UINTN)NULL);\r
	117	}\r
cf1d4549 JY	118	SetInterruptState (InterruptState);\r
	119	\r
	120	return Status;\r
	121	}\r
	122	\r
	123	/**\r
	124	Call FSP API - FspMemoryInit.\r
	125	\r
	126	@param[in] FspmUpdDataPtr Address pointer to the FSP_MEMORY_INIT_PARAMS structure.\r
	127	@param[out] HobListPtr Address of the HobList pointer.\r
	128	\r
	129	@return EFI status returned by FspMemoryInit API.\r
	130	**/\r
	131	EFI_STATUS\r
	132	EFIAPI\r
	133	CallFspMemoryInit (\r
7c7184e2 MK	134	IN VOID *FspmUpdDataPtr,\r
7c7184e2 MK	135	OUT VOID **HobListPtr\r
cf1d4549 JY	136	)\r
cf1d4549 JY	137	{\r
7c7184e2 MK	138	FSP_INFO_HEADER *FspHeader;\r
	139	FSP_MEMORY_INIT FspMemoryInitApi;\r
	140	EFI_STATUS Status;\r
	141	BOOLEAN InterruptState;\r
cf1d4549 JY	142	\r
	143	FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));\r
	144	if (FspHeader == NULL) {\r
	145	return EFI_DEVICE_ERROR;\r
	146	}\r
	147	\r
d953f4f1	148	FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset);\r
7c7184e2	149	InterruptState = SaveAndDisableInterrupts ();\r
86a2f3c4 TK	150	if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
	151	Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);\r
	152	} else {\r
	153	Status = Execute64BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);\r
	154	}\r
cf1d4549 JY	155	SetInterruptState (InterruptState);\r
	156	\r
	157	return Status;\r
	158	}\r
	159	\r
	160	/**\r
	161	Call FSP API - TempRamExit.\r
	162	\r
	163	@param[in] TempRamExitParam Address pointer to the TempRamExit parameters structure.\r
	164	\r
	165	@return EFI status returned by TempRamExit API.\r
	166	**/\r
	167	EFI_STATUS\r
	168	EFIAPI\r
	169	CallTempRamExit (\r
7c7184e2	170	IN VOID *TempRamExitParam\r
cf1d4549 JY	171	)\r
cf1d4549 JY	172	{\r
7c7184e2 MK	173	FSP_INFO_HEADER *FspHeader;\r
	174	FSP_TEMP_RAM_EXIT TempRamExitApi;\r
	175	EFI_STATUS Status;\r
	176	BOOLEAN InterruptState;\r
cf1d4549 JY	177	\r
	178	FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));\r
	179	if (FspHeader == NULL) {\r
	180	return EFI_DEVICE_ERROR;\r
	181	}\r
	182	\r
d953f4f1	183	TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset);\r
cf1d4549	184	InterruptState = SaveAndDisableInterrupts ();\r
86a2f3c4 TK	185	if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
	186	Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam, (UINTN)NULL);\r
	187	} else {\r
	188	Status = Execute64BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam, (UINTN)NULL);\r
	189	}\r
cf1d4549 JY	190	SetInterruptState (InterruptState);\r
	191	\r
	192	return Status;\r
	193	}\r
	194	\r
	195	/**\r
	196	Call FSP API - FspSiliconInit.\r
	197	\r
	198	@param[in] FspsUpdDataPtr Address pointer to the Silicon Init parameters structure.\r
	199	\r
	200	@return EFI status returned by FspSiliconInit API.\r
	201	**/\r
	202	EFI_STATUS\r
	203	EFIAPI\r
	204	CallFspSiliconInit (\r
7c7184e2	205	IN VOID *FspsUpdDataPtr\r
cf1d4549 JY	206	)\r
cf1d4549 JY	207	{\r
7c7184e2 MK	208	FSP_INFO_HEADER *FspHeader;\r
	209	FSP_SILICON_INIT FspSiliconInitApi;\r
	210	EFI_STATUS Status;\r
	211	BOOLEAN InterruptState;\r
cf1d4549 JY	212	\r
	213	FspHeader = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspsBaseAddress));\r
	214	if (FspHeader == NULL) {\r
	215	return EFI_DEVICE_ERROR;\r
	216	}\r
	217	\r
d953f4f1	218	FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset);\r
7c7184e2	219	InterruptState = SaveAndDisableInterrupts ();\r
86a2f3c4 TK	220	if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) == FSP_IA32) {\r
	221	Status = Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdDataPtr, (UINTN)NULL);\r
	222	} else {\r
	223	Status = Execute64BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdDataPtr, (UINTN)NULL);\r
	224	}\r
cf1d4549 JY	225	SetInterruptState (InterruptState);\r
	226	\r
	227	return Status;\r
	228	}\r