projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 9429e8a0 JY |
1 | ## @file\r |
| 2 | # IntelSilicon Package\r | |
| 3 | #\r | |
| 4 | # This package provides common open source Intel silicon modules.\r | |
| 5 | #\r | |
| 339cb0af | 6 | # Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 8f7a05e1 | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 9429e8a0 JY |
8 | #\r |
| 9 | ##\r | |
| 10 | \r | |
| 11 | [Defines]\r | |
| 12 | DEC_SPECIFICATION = 0x00010005\r | |
| 13 | PACKAGE_NAME = IntelSiliconPkg\r | |
| 14 | PACKAGE_GUID = F7A58914-FA0E-4F71-BD6A-220FDF824A49\r | |
| 15 | PACKAGE_VERSION = 0.1\r | |
| 16 | \r | |
| 17 | [Includes]\r | |
| 18 | Include\r | |
| 63998d7c | 19 | \r |
| c8a2f3c3 SZ |
20 | [LibraryClasses.IA32, LibraryClasses.X64]\r |
| 21 | ## @libraryclass Provides services to access Microcode region on flash device.\r | |
| 22 | #\r | |
| 23 | MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h\r | |
| 24 | \r | |
| 63998d7c | 25 | [Guids]\r |
| a5991c88 GM |
26 | ## GUID for Package token space\r |
| 27 | # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735}\r | |
| 2048ab4b | 28 | gIntelSiliconPkgTokenSpaceGuid = { 0xa9f8d54e, 0x1107, 0x4f0a, { 0xad, 0xd0, 0x45, 0x87, 0xe7, 0xa4, 0xa7, 0x35 } }\r |
| a5991c88 | 29 | \r |
| 63998d7c MG |
30 | ## HOB GUID to publish SMBIOS data records from PEI phase\r |
| 31 | # HOB data format is same as SMBIOS records defined in SMBIOS spec or OEM defined types\r | |
| 32 | # Generic DXE Library / Driver can locate HOB(s) and add SMBIOS records into SMBIOS table\r | |
| 33 | gIntelSmbiosDataHobGuid = { 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}\r | |
| 34 | \r | |
| c8a2f3c3 SZ |
35 | ## Include/Guid/MicrocodeFmp.h\r |
| 36 | gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }\r | |
| 37 | \r | |
| 0b7df500 JY |
38 | [Ppis]\r |
| 39 | gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } }\r | |
| 40 | \r | |
| b7ff5027 JY |
41 | [Protocols]\r |
| 42 | gEdkiiPlatformVTdPolicyProtocolGuid = { 0x3d17e448, 0x466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }}\r | |
| 43 | \r | |
| 27bf6712 SZ |
44 | [PcdsFixedAtBuild, PcdsPatchableInModule]\r |
| 45 | ## Error code for VTd error.<BR><BR>\r | |
| 46 | # EDKII_ERROR_CODE_VTD_ERROR = (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x02008000<BR>\r | |
| 47 | # @Prompt Error code for VTd error.\r | |
| 48 | gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005\r | |
| 49 | \r | |
| a5991c88 GM |
50 | [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r |
| 51 | ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT)\r | |
| 52 | # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.\r | |
| 53 | # The default GUID can be updated by patching or runtime if platform support multiple VBT configurations.\r | |
| 54 | # @Prompt GUID of the FFS which contains the Graphics Video BIOS Table (VBT)\r | |
| 55 | # { 0x56752da9, 0xde6b, 0x4895, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 0x22 }\r | |
| 56 | gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid|{ 0xa9, 0x2d, 0x75, 0x56, 0x6b, 0xde, 0x95, 0x48, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 0x22 }|VOID*|0x00000001\r | |
| 57 | \r | |
| 0d12b733 | 58 | ## The mask is used to control VTd behavior.<BR><BR>\r |
| 8be3ff8f JY |
59 | # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PPI is installed in PEI.)\r |
| 60 | # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in normal boot. EndOfPEI in S3)\r | |
| 8c09f300 | 61 | # BIT2: Force no IOMMU access attribute request recording before DMAR table is installed.\r |
| 0d12b733 JY |
62 | # @Prompt The policy for VTd driver behavior.\r |
| 63 | gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x00000002\r | |
| 64 | \r | |
| 339cb0af SZ |
65 | ## Declares VTd PEI DMA buffer size.<BR><BR>\r |
| 66 | # When this PCD value is referred by platform to calculate the required\r | |
| 67 | # memory size for PEI (InstallPeiMemory), the PMR alignment requirement\r | |
| 68 | # needs be considered to be added with this PCD value for alignment\r | |
| 69 | # adjustment need by AllocateAlignedPages.\r | |
| 70 | # @Prompt The VTd PEI DMA buffer size.\r | |
| 71 | gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000|UINT32|0x00000003\r | |
| 72 | \r | |
| 73 | ## Declares VTd PEI DMA buffer size for S3.<BR><BR>\r | |
| 74 | # When this PCD value is referred by platform to calculate the required\r | |
| 75 | # memory size for PEI S3 (InstallPeiMemory), the PMR alignment requirement\r | |
| 76 | # needs be considered to be added with this PCD value for alignment\r | |
| 77 | # adjustment need by AllocateAlignedPages.\r | |
| 78 | # @Prompt The VTd PEI DMA buffer size for S3.\r | |
| 79 | gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT32|0x00000004\r | |
| 80 | \r |