[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / AhciMode.h

/** @file\r
  Header file for AHCI mode of ATA host controller.\r
\r
  Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __ATA_HC_AHCI_MODE_H__\r
#define __ATA_HC_AHCI_MODE_H__\r
\r
#define EFI_AHCI_BAR_INDEX  0x05\r
\r
#define EFI_AHCI_CAPABILITY_OFFSET  0x0000\r
#define   EFI_AHCI_CAP_SAM          BIT18\r
#define   EFI_AHCI_CAP_SSS          BIT27\r
#define   EFI_AHCI_CAP_S64A         BIT31\r
#define EFI_AHCI_GHC_OFFSET         0x0004\r
#define   EFI_AHCI_GHC_RESET        BIT0\r
#define   EFI_AHCI_GHC_IE           BIT1\r
#define   EFI_AHCI_GHC_ENABLE       BIT31\r
#define EFI_AHCI_IS_OFFSET          0x0008\r
#define EFI_AHCI_PI_OFFSET          0x000C\r
\r
#define EFI_AHCI_MAX_PORTS  32\r
\r
#define AHCI_CAPABILITY2_OFFSET  0x0024\r
#define   AHCI_CAP2_SDS          BIT3\r
#define   AHCI_CAP2_SADM         BIT4\r
\r
typedef struct {\r
  UINT32    Lower32;\r
  UINT32    Upper32;\r
} DATA_32;\r
\r
typedef union {\r
  DATA_32    Uint32;\r
  UINT64     Uint64;\r
} DATA_64;\r
\r
//\r
// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r
// Add a bit of margin for robustness.\r
//\r
#define  EFI_AHCI_BUS_PHY_DETECT_TIMEOUT  15\r
//\r
// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.\r
//\r
#define  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT  EFI_TIMER_PERIOD_MILLISECONDS(500)\r
//\r
// Refer SATA1.0a spec, the bus reset time should be less than 1s.\r
//\r
#define  EFI_AHCI_BUS_RESET_TIMEOUT  EFI_TIMER_PERIOD_SECONDS(1)\r
\r
#define  EFI_AHCI_ATAPI_DEVICE_SIG     0xEB140000\r
#define  EFI_AHCI_ATA_DEVICE_SIG       0x00000000\r
#define  EFI_AHCI_PORT_MULTIPLIER_SIG  0x96690000\r
#define  EFI_AHCI_ATAPI_SIG_MASK       0xFFFF0000\r
\r
//\r
// Each PRDT entry can point to a memory block up to 4M byte\r
//\r
#define EFI_AHCI_MAX_DATA_PER_PRDT  0x400000\r
\r
#define EFI_AHCI_FIS_REGISTER_H2D           0x27         // Register FIS - Host to Device\r
#define   EFI_AHCI_FIS_REGISTER_H2D_LENGTH  20\r
#define EFI_AHCI_FIS_REGISTER_D2H           0x34         // Register FIS - Device to Host\r
#define   EFI_AHCI_FIS_REGISTER_D2H_LENGTH  20\r
#define EFI_AHCI_FIS_DMA_ACTIVATE           0x39         // DMA Activate FIS - Device to Host\r
#define   EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH  4\r
#define EFI_AHCI_FIS_DMA_SETUP              0x41         // DMA Setup FIS - Bi-directional\r
#define   EFI_AHCI_FIS_DMA_SETUP_LENGTH     28\r
#define EFI_AHCI_FIS_DATA                   0x46         // Data FIS - Bi-directional\r
#define EFI_AHCI_FIS_BIST                   0x58         // BIST Activate FIS - Bi-directional\r
#define   EFI_AHCI_FIS_BIST_LENGTH          12\r
#define EFI_AHCI_FIS_PIO_SETUP              0x5F         // PIO Setup FIS - Device to Host\r
#define   EFI_AHCI_FIS_PIO_SETUP_LENGTH     20\r
#define EFI_AHCI_FIS_SET_DEVICE             0xA1         // Set Device Bits FIS - Device to Host\r
#define   EFI_AHCI_FIS_SET_DEVICE_LENGTH    8\r
\r
#define EFI_AHCI_D2H_FIS_OFFSET  0x40\r
#define EFI_AHCI_DMA_FIS_OFFSET  0x00\r
#define EFI_AHCI_PIO_FIS_OFFSET  0x20\r
#define EFI_AHCI_SDB_FIS_OFFSET  0x58\r
#define EFI_AHCI_FIS_TYPE_MASK   0xFF\r
#define EFI_AHCI_U_FIS_OFFSET    0x60\r
\r
//\r
// Port register\r
//\r
#define EFI_AHCI_PORT_START                  0x0100\r
#define EFI_AHCI_PORT_REG_WIDTH              0x0080\r
#define EFI_AHCI_PORT_CLB                    0x0000\r
#define EFI_AHCI_PORT_CLBU                   0x0004\r
#define EFI_AHCI_PORT_FB                     0x0008\r
#define EFI_AHCI_PORT_FBU                    0x000C\r
#define EFI_AHCI_PORT_IS                     0x0010\r
#define   EFI_AHCI_PORT_IS_DHRS              BIT0\r
#define   EFI_AHCI_PORT_IS_PSS               BIT1\r
#define   EFI_AHCI_PORT_IS_DSS               BIT2\r
#define   EFI_AHCI_PORT_IS_SDBS              BIT3\r
#define   EFI_AHCI_PORT_IS_UFS               BIT4\r
#define   EFI_AHCI_PORT_IS_DPS               BIT5\r
#define   EFI_AHCI_PORT_IS_PCS               BIT6\r
#define   EFI_AHCI_PORT_IS_DIS               BIT7\r
#define   EFI_AHCI_PORT_IS_PRCS              BIT22\r
#define   EFI_AHCI_PORT_IS_IPMS              BIT23\r
#define   EFI_AHCI_PORT_IS_OFS               BIT24\r
#define   EFI_AHCI_PORT_IS_INFS              BIT26\r
#define   EFI_AHCI_PORT_IS_IFS               BIT27\r
#define   EFI_AHCI_PORT_IS_HBDS              BIT28\r
#define   EFI_AHCI_PORT_IS_HBFS              BIT29\r
#define   EFI_AHCI_PORT_IS_TFES              BIT30\r
#define   EFI_AHCI_PORT_IS_CPDS              BIT31\r
#define   EFI_AHCI_PORT_IS_CLEAR             0xFFFFFFFF\r
#define   EFI_AHCI_PORT_IS_FIS_CLEAR         0x0000000F\r
#define   EFI_AHCI_PORT_IS_ERROR_MASK        (EFI_AHCI_PORT_IS_INFS | EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_HBDS | EFI_AHCI_PORT_IS_HBFS | EFI_AHCI_PORT_IS_TFES)\r
#define   EFI_AHCI_PORT_IS_FATAL_ERROR_MASK  (EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_HBDS | EFI_AHCI_PORT_IS_HBFS | EFI_AHCI_PORT_IS_TFES)\r
\r
#define EFI_AHCI_PORT_IE                  0x0014\r
#define EFI_AHCI_PORT_CMD                 0x0018\r
#define   EFI_AHCI_PORT_CMD_ST_MASK       0xFFFFFFFE\r
#define   EFI_AHCI_PORT_CMD_ST            BIT0\r
#define   EFI_AHCI_PORT_CMD_SUD           BIT1\r
#define   EFI_AHCI_PORT_CMD_POD           BIT2\r
#define   EFI_AHCI_PORT_CMD_CLO           BIT3\r
#define   EFI_AHCI_PORT_CMD_FRE           BIT4\r
#define   EFI_AHCI_PORT_CMD_CCS_MASK      (BIT8 | BIT9 | BIT10 | BIT11 | BIT12)\r
#define   EFI_AHCI_PORT_CMD_CCS_SHIFT     8\r
#define   EFI_AHCI_PORT_CMD_FR            BIT14\r
#define   EFI_AHCI_PORT_CMD_CR            BIT15\r
#define   EFI_AHCI_PORT_CMD_MASK          ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)\r
#define   EFI_AHCI_PORT_CMD_PMA           BIT17\r
#define   EFI_AHCI_PORT_CMD_HPCP          BIT18\r
#define   EFI_AHCI_PORT_CMD_MPSP          BIT19\r
#define   EFI_AHCI_PORT_CMD_CPD           BIT20\r
#define   EFI_AHCI_PORT_CMD_ESP           BIT21\r
#define   EFI_AHCI_PORT_CMD_ATAPI         BIT24\r
#define   EFI_AHCI_PORT_CMD_DLAE          BIT25\r
#define   EFI_AHCI_PORT_CMD_ALPE          BIT26\r
#define   EFI_AHCI_PORT_CMD_ASP           BIT27\r
#define   EFI_AHCI_PORT_CMD_ICC_MASK      (BIT28 | BIT29 | BIT30 | BIT31)\r
#define   EFI_AHCI_PORT_CMD_ACTIVE        (1 << 28 )\r
#define EFI_AHCI_PORT_TFD                 0x0020\r
#define   EFI_AHCI_PORT_TFD_MASK          (BIT7 | BIT3 | BIT0)\r
#define   EFI_AHCI_PORT_TFD_BSY           BIT7\r
#define   EFI_AHCI_PORT_TFD_DRQ           BIT3\r
#define   EFI_AHCI_PORT_TFD_ERR           BIT0\r
#define   EFI_AHCI_PORT_TFD_ERR_MASK      0x00FF00\r
#define EFI_AHCI_PORT_SIG                 0x0024\r
#define EFI_AHCI_PORT_SSTS                0x0028\r
#define   EFI_AHCI_PORT_SSTS_DET_MASK     0x000F\r
#define   EFI_AHCI_PORT_SSTS_DET          0x0001\r
#define   EFI_AHCI_PORT_SSTS_DET_PCE      0x0003\r
#define   EFI_AHCI_PORT_SSTS_SPD_MASK     0x00F0\r
#define EFI_AHCI_PORT_SCTL                0x002C\r
#define   EFI_AHCI_PORT_SCTL_DET_MASK     0x000F\r
#define   EFI_AHCI_PORT_SCTL_MASK         (~EFI_AHCI_PORT_SCTL_DET_MASK)\r
#define   EFI_AHCI_PORT_SCTL_DET_INIT     0x0001\r
#define   EFI_AHCI_PORT_SCTL_DET_PHYCOMM  0x0003\r
#define   EFI_AHCI_PORT_SCTL_SPD_MASK     0x00F0\r
#define   EFI_AHCI_PORT_SCTL_IPM_MASK     0x0F00\r
#define   EFI_AHCI_PORT_SCTL_IPM_INIT     0x0300\r
#define   EFI_AHCI_PORT_SCTL_IPM_PSD      0x0100\r
#define   EFI_AHCI_PORT_SCTL_IPM_SSD      0x0200\r
#define EFI_AHCI_PORT_SERR                0x0030\r
#define   EFI_AHCI_PORT_SERR_RDIE         BIT0\r
#define   EFI_AHCI_PORT_SERR_RCE          BIT1\r
#define   EFI_AHCI_PORT_SERR_TDIE         BIT8\r
#define   EFI_AHCI_PORT_SERR_PCDIE        BIT9\r
#define   EFI_AHCI_PORT_SERR_PE           BIT10\r
#define   EFI_AHCI_PORT_SERR_IE           BIT11\r
#define   EFI_AHCI_PORT_SERR_PRC          BIT16\r
#define   EFI_AHCI_PORT_SERR_PIE          BIT17\r
#define   EFI_AHCI_PORT_SERR_CW           BIT18\r
#define   EFI_AHCI_PORT_SERR_BDE          BIT19\r
#define   EFI_AHCI_PORT_SERR_DE           BIT20\r
#define   EFI_AHCI_PORT_SERR_CRCE         BIT21\r
#define   EFI_AHCI_PORT_SERR_HE           BIT22\r
#define   EFI_AHCI_PORT_SERR_LSE          BIT23\r
#define   EFI_AHCI_PORT_SERR_TSTE         BIT24\r
#define   EFI_AHCI_PORT_SERR_UFT          BIT25\r
#define   EFI_AHCI_PORT_SERR_EX           BIT26\r
#define   EFI_AHCI_PORT_ERR_CLEAR         0xFFFFFFFF\r
#define EFI_AHCI_PORT_SACT                0x0034\r
#define EFI_AHCI_PORT_CI                  0x0038\r
#define EFI_AHCI_PORT_SNTF                0x003C\r
#define AHCI_PORT_DEVSLP                  0x0044\r
#define   AHCI_PORT_DEVSLP_ADSE           BIT0\r
#define   AHCI_PORT_DEVSLP_DSP            BIT1\r
#define   AHCI_PORT_DEVSLP_DETO_MASK      0x000003FC\r
#define   AHCI_PORT_DEVSLP_MDAT_MASK      0x00007C00\r
#define   AHCI_PORT_DEVSLP_DITO_MASK      0x01FF8000\r
#define   AHCI_PORT_DEVSLP_DM_MASK        0x1E000000\r
\r
#define AHCI_COMMAND_RETRIES  (PcdGet32 (PcdAhciCommandRetryCount))\r
\r
#pragma pack(1)\r
//\r
// Command List structure includes total 32 entries.\r
// The entry data structure is listed at the following.\r
//\r
typedef struct {\r
  UINT32    AhciCmdCfl   : 5; // Command FIS Length\r
  UINT32    AhciCmdA     : 1; // ATAPI\r
  UINT32    AhciCmdW     : 1; // Write\r
  UINT32    AhciCmdP     : 1; // Prefetchable\r
  UINT32    AhciCmdR     : 1; // Reset\r
  UINT32    AhciCmdB     : 1; // BIST\r
  UINT32    AhciCmdC     : 1; // Clear Busy upon R_OK\r
  UINT32    AhciCmdRsvd  : 1;\r
  UINT32    AhciCmdPmp   : 4;  // Port Multiplier Port\r
  UINT32    AhciCmdPrdtl : 16; // Physical Region Descriptor Table Length\r
  UINT32    AhciCmdPrdbc;      // Physical Region Descriptor Byte Count\r
  UINT32    AhciCmdCtba;       // Command Table Descriptor Base Address\r
  UINT32    AhciCmdCtbau;      // Command Table Descriptor Base Address Upper 32-BITs\r
  UINT32    AhciCmdRsvd1[4];\r
} EFI_AHCI_COMMAND_LIST;\r
\r
//\r
// This is a software constructed FIS.\r
// For data transfer operations, this is the H2D Register FIS format as\r
// specified in the Serial ATA Revision 2.6 specification.\r
//\r
typedef struct {\r
  UINT8    AhciCFisType;\r
  UINT8    AhciCFisPmNum  : 4;\r
  UINT8    AhciCFisRsvd   : 1;\r
  UINT8    AhciCFisRsvd1  : 1;\r
  UINT8    AhciCFisRsvd2  : 1;\r
  UINT8    AhciCFisCmdInd : 1;\r
  UINT8    AhciCFisCmd;\r
  UINT8    AhciCFisFeature;\r
  UINT8    AhciCFisSecNum;\r
  UINT8    AhciCFisClyLow;\r
  UINT8    AhciCFisClyHigh;\r
  UINT8    AhciCFisDevHead;\r
  UINT8    AhciCFisSecNumExp;\r
  UINT8    AhciCFisClyLowExp;\r
  UINT8    AhciCFisClyHighExp;\r
  UINT8    AhciCFisFeatureExp;\r
  UINT8    AhciCFisSecCount;\r
  UINT8    AhciCFisSecCountExp;\r
  UINT8    AhciCFisRsvd3;\r
  UINT8    AhciCFisControl;\r
  UINT8    AhciCFisRsvd4[4];\r
  UINT8    AhciCFisRsvd5[44];\r
} EFI_AHCI_COMMAND_FIS;\r
\r
typedef enum {\r
  SataFisD2H = 0,\r
  SataFisPioSetup,\r
  SataFisDmaSetup\r
} SATA_FIS_TYPE;\r
\r
//\r
// ACMD: ATAPI command (12 or 16 bytes)\r
//\r
typedef struct {\r
  UINT8    AtapiCmd[0x10];\r
} EFI_AHCI_ATAPI_COMMAND;\r
\r
//\r
// Physical Region Descriptor Table includes up to 65535 entries\r
// The entry data structure is listed at the following.\r
// the actual entry number comes from the PRDTL field in the command\r
// list entry for this command slot.\r
//\r
typedef struct {\r
  UINT32    AhciPrdtDba;      // Data Base Address\r
  UINT32    AhciPrdtDbau;     // Data Base Address Upper 32-BITs\r
  UINT32    AhciPrdtRsvd;\r
  UINT32    AhciPrdtDbc   : 22; // Data Byte Count\r
  UINT32    AhciPrdtRsvd1 : 9;\r
  UINT32    AhciPrdtIoc   : 1; // Interrupt on Completion\r
} EFI_AHCI_COMMAND_PRDT;\r
\r
//\r
// Command table data structure which is pointed to by the entry in the command list\r
//\r
typedef struct {\r
  EFI_AHCI_COMMAND_FIS      CommandFis;       // A software constructed FIS.\r
  EFI_AHCI_ATAPI_COMMAND    AtapiCmd;         // 12 or 16 bytes ATAPI cmd.\r
  UINT8                     Reserved[0x30];\r
  EFI_AHCI_COMMAND_PRDT     PrdtTable[65535];     // The scatter/gather list for data transfer\r
} EFI_AHCI_COMMAND_TABLE;\r
\r
//\r
// Received FIS structure\r
//\r
typedef struct {\r
  UINT8     AhciDmaSetupFis[0x1C];        // Dma Setup Fis: offset 0x00\r
  UINT8     AhciDmaSetupFisRsvd[0x04];\r
  UINT8     AhciPioSetupFis[0x14];        // Pio Setup Fis: offset 0x20\r
  UINT8     AhciPioSetupFisRsvd[0x0C];\r
  UINT8     AhciD2HRegisterFis[0x14];     // D2H Register Fis: offset 0x40\r
  UINT8     AhciD2HRegisterFisRsvd[0x04];\r
  UINT64    AhciSetDeviceBitsFis;         // Set Device Bits Fix: offset 0x58\r
  UINT8     AhciUnknownFis[0x40];         // Unknown Fis: offset 0x60\r
  UINT8     AhciUnknownFisRsvd[0x60];\r
} EFI_AHCI_RECEIVED_FIS;\r
\r
typedef struct {\r
  UINT8     Madt        : 5;\r
  UINT8     Reserved_5  : 3;\r
  UINT8     Deto;\r
  UINT16    Reserved_16;\r
  UINT32    Reserved_32 : 31;\r
  UINT32    Supported   : 1;\r
} DEVSLP_TIMING_VARIABLES;\r
\r
#pragma pack()\r
\r
typedef struct {\r
  EFI_AHCI_RECEIVED_FIS     *AhciRFis;\r
  EFI_AHCI_COMMAND_LIST     *AhciCmdList;\r
  EFI_AHCI_COMMAND_TABLE    *AhciCommandTable;\r
  EFI_AHCI_RECEIVED_FIS     *AhciRFisPciAddr;\r
  EFI_AHCI_COMMAND_LIST     *AhciCmdListPciAddr;\r
  EFI_AHCI_COMMAND_TABLE    *AhciCommandTablePciAddr;\r
  UINT64                    MaxCommandListSize;\r
  UINT64                    MaxCommandTableSize;\r
  UINT64                    MaxReceiveFisSize;\r
  VOID                      *MapRFis;\r
  VOID                      *MapCmdList;\r
  VOID                      *MapCommandTable;\r
} EFI_AHCI_REGISTERS;\r
\r
/**\r
  This function is used to send out ATAPI commands conforms to the Packet Command\r
  with PIO Protocol.\r
\r
  @param PciIo              The PCI IO protocol instance.\r
  @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.\r
  @param Port               The number of port.\r
  @param PortMultiplier     The number of port multiplier.\r
  @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r
\r
  @retval EFI_SUCCESS       send out the ATAPI packet command successfully\r
                            and device sends data successfully.\r
  @retval EFI_DEVICE_ERROR  the device failed to send data.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
AhciPacketCommandExecute (\r
  IN  EFI_PCI_IO_PROTOCOL                         *PciIo,\r
  IN  EFI_AHCI_REGISTERS                          *AhciRegisters,\r
  IN  UINT8                                       Port,\r
  IN  UINT8                                       PortMultiplier,\r
  IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET  *Packet\r
  );\r
\r
/**\r
  Start command for give slot on specific port.\r
\r
  @param  PciIo              The PCI IO protocol instance.\r
  @param  Port               The number of port.\r
  @param  CommandSlot        The number of CommandSlot.\r
  @param  Timeout            The timeout value of start, uses 100ns as a unit.\r
\r
  @retval EFI_DEVICE_ERROR   The command start unsuccessfully.\r
  @retval EFI_TIMEOUT        The operation is time out.\r
  @retval EFI_SUCCESS        The command start successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
AhciStartCommand (\r
  IN  EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN  UINT8                Port,\r
  IN  UINT8                CommandSlot,\r
  IN  UINT64               Timeout\r
  );\r
\r
/**\r
  Stop command running for giving port\r
\r
  @param  PciIo              The PCI IO protocol instance.\r
  @param  Port               The number of port.\r
  @param  Timeout            The timeout value of stop, uses 100ns as a unit.\r
\r
  @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.\r
  @retval EFI_TIMEOUT        The operation is time out.\r
  @retval EFI_SUCCESS        The command stop successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
AhciStopCommand (\r
  IN  EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN  UINT8                Port,\r
  IN  UINT64               Timeout\r
  );\r
\r
#endif\r
Commit	Line	Data
a41b5272	1	/** @file\r
a41b5272	2	Header file for AHCI mode of ATA host controller.\r
d1102dba	3	\r
cc28ab7a	4	Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>\r
9d510e61	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
a41b5272	6	\r
a41b5272	7	**/\r
1436aea4	8	\r
a41b5272	9	#ifndef __ATA_HC_AHCI_MODE_H__\r
	10	#define __ATA_HC_AHCI_MODE_H__\r
	11	\r
1436aea4	12	#define EFI_AHCI_BAR_INDEX 0x05\r
a41b5272	13	\r
1436aea4 MK	14	#define EFI_AHCI_CAPABILITY_OFFSET 0x0000\r
	15	#define EFI_AHCI_CAP_SAM BIT18\r
	16	#define EFI_AHCI_CAP_SSS BIT27\r
	17	#define EFI_AHCI_CAP_S64A BIT31\r
	18	#define EFI_AHCI_GHC_OFFSET 0x0004\r
	19	#define EFI_AHCI_GHC_RESET BIT0\r
	20	#define EFI_AHCI_GHC_IE BIT1\r
	21	#define EFI_AHCI_GHC_ENABLE BIT31\r
	22	#define EFI_AHCI_IS_OFFSET 0x0008\r
	23	#define EFI_AHCI_PI_OFFSET 0x000C\r
a41b5272	24	\r
1436aea4	25	#define EFI_AHCI_MAX_PORTS 32\r
6b13aa60	26	\r
1436aea4 MK	27	#define AHCI_CAPABILITY2_OFFSET 0x0024\r
	28	#define AHCI_CAP2_SDS BIT3\r
	29	#define AHCI_CAP2_SADM BIT4\r
f3100a1a	30	\r
a41b5272	31	typedef struct {\r
1436aea4 MK	32	UINT32 Lower32;\r
1436aea4 MK	33	UINT32 Upper32;\r
a41b5272	34	} DATA_32;\r
	35	\r
	36	typedef union {\r
1436aea4 MK	37	DATA_32 Uint32;\r
1436aea4 MK	38	UINT64 Uint64;\r
a41b5272	39	} DATA_64;\r
a41b5272	40	\r
cbd2a4b3	41	//\r
cbd2a4b3	42	// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r
1fb805b1	43	// Add a bit of margin for robustness.\r
cbd2a4b3	44	//\r
1436aea4	45	#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 15\r
cbd2a4b3	46	//\r
	47	// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.\r
	48	//\r
1436aea4	49	#define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)\r
cbd2a4b3	50	//\r
	51	// Refer SATA1.0a spec, the bus reset time should be less than 1s.\r
	52	//\r
1436aea4	53	#define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)\r
cbd2a4b3	54	\r
1436aea4 MK	55	#define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000\r
	56	#define EFI_AHCI_ATA_DEVICE_SIG 0x00000000\r
	57	#define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000\r
	58	#define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000\r
a41b5272	59	\r
	60	//\r
	61	// Each PRDT entry can point to a memory block up to 4M byte\r
	62	//\r
1436aea4 MK	63	#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000\r
	64	\r
	65	#define EFI_AHCI_FIS_REGISTER_H2D 0x27 // Register FIS - Host to Device\r
	66	#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20\r
	67	#define EFI_AHCI_FIS_REGISTER_D2H 0x34 // Register FIS - Device to Host\r
	68	#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20\r
	69	#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 // DMA Activate FIS - Device to Host\r
	70	#define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4\r
	71	#define EFI_AHCI_FIS_DMA_SETUP 0x41 // DMA Setup FIS - Bi-directional\r
	72	#define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28\r
	73	#define EFI_AHCI_FIS_DATA 0x46 // Data FIS - Bi-directional\r
	74	#define EFI_AHCI_FIS_BIST 0x58 // BIST Activate FIS - Bi-directional\r
	75	#define EFI_AHCI_FIS_BIST_LENGTH 12\r
	76	#define EFI_AHCI_FIS_PIO_SETUP 0x5F // PIO Setup FIS - Device to Host\r
	77	#define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20\r
	78	#define EFI_AHCI_FIS_SET_DEVICE 0xA1 // Set Device Bits FIS - Device to Host\r
	79	#define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8\r
	80	\r
	81	#define EFI_AHCI_D2H_FIS_OFFSET 0x40\r
	82	#define EFI_AHCI_DMA_FIS_OFFSET 0x00\r
	83	#define EFI_AHCI_PIO_FIS_OFFSET 0x20\r
	84	#define EFI_AHCI_SDB_FIS_OFFSET 0x58\r
	85	#define EFI_AHCI_FIS_TYPE_MASK 0xFF\r
	86	#define EFI_AHCI_U_FIS_OFFSET 0x60\r
a41b5272	87	\r
	88	//\r
	89	// Port register\r
	90	//\r
1436aea4 MK	91	#define EFI_AHCI_PORT_START 0x0100\r
	92	#define EFI_AHCI_PORT_REG_WIDTH 0x0080\r
	93	#define EFI_AHCI_PORT_CLB 0x0000\r
	94	#define EFI_AHCI_PORT_CLBU 0x0004\r
	95	#define EFI_AHCI_PORT_FB 0x0008\r
	96	#define EFI_AHCI_PORT_FBU 0x000C\r
	97	#define EFI_AHCI_PORT_IS 0x0010\r
	98	#define EFI_AHCI_PORT_IS_DHRS BIT0\r
	99	#define EFI_AHCI_PORT_IS_PSS BIT1\r
	100	#define EFI_AHCI_PORT_IS_DSS BIT2\r
	101	#define EFI_AHCI_PORT_IS_SDBS BIT3\r
	102	#define EFI_AHCI_PORT_IS_UFS BIT4\r
	103	#define EFI_AHCI_PORT_IS_DPS BIT5\r
	104	#define EFI_AHCI_PORT_IS_PCS BIT6\r
	105	#define EFI_AHCI_PORT_IS_DIS BIT7\r
	106	#define EFI_AHCI_PORT_IS_PRCS BIT22\r
	107	#define EFI_AHCI_PORT_IS_IPMS BIT23\r
	108	#define EFI_AHCI_PORT_IS_OFS BIT24\r
	109	#define EFI_AHCI_PORT_IS_INFS BIT26\r
	110	#define EFI_AHCI_PORT_IS_IFS BIT27\r
	111	#define EFI_AHCI_PORT_IS_HBDS BIT28\r
	112	#define EFI_AHCI_PORT_IS_HBFS BIT29\r
	113	#define EFI_AHCI_PORT_IS_TFES BIT30\r
	114	#define EFI_AHCI_PORT_IS_CPDS BIT31\r
	115	#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF\r
	116	#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F\r
	117	#define EFI_AHCI_PORT_IS_ERROR_MASK (EFI_AHCI_PORT_IS_INFS \| EFI_AHCI_PORT_IS_IFS \| EFI_AHCI_PORT_IS_HBDS \| EFI_AHCI_PORT_IS_HBFS \| EFI_AHCI_PORT_IS_TFES)\r
	118	#define EFI_AHCI_PORT_IS_FATAL_ERROR_MASK (EFI_AHCI_PORT_IS_IFS \| EFI_AHCI_PORT_IS_HBDS \| EFI_AHCI_PORT_IS_HBFS \| EFI_AHCI_PORT_IS_TFES)\r
	119	\r
	120	#define EFI_AHCI_PORT_IE 0x0014\r
	121	#define EFI_AHCI_PORT_CMD 0x0018\r
	122	#define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE\r
	123	#define EFI_AHCI_PORT_CMD_ST BIT0\r
	124	#define EFI_AHCI_PORT_CMD_SUD BIT1\r
	125	#define EFI_AHCI_PORT_CMD_POD BIT2\r
	126	#define EFI_AHCI_PORT_CMD_CLO BIT3\r
	127	#define EFI_AHCI_PORT_CMD_FRE BIT4\r
	128	#define EFI_AHCI_PORT_CMD_CCS_MASK (BIT8 \| BIT9 \| BIT10 \| BIT11 \| BIT12)\r
	129	#define EFI_AHCI_PORT_CMD_CCS_SHIFT 8\r
	130	#define EFI_AHCI_PORT_CMD_FR BIT14\r
	131	#define EFI_AHCI_PORT_CMD_CR BIT15\r
	132	#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST \| EFI_AHCI_PORT_CMD_FRE \| EFI_AHCI_PORT_CMD_COL)\r
	133	#define EFI_AHCI_PORT_CMD_PMA BIT17\r
	134	#define EFI_AHCI_PORT_CMD_HPCP BIT18\r
	135	#define EFI_AHCI_PORT_CMD_MPSP BIT19\r
	136	#define EFI_AHCI_PORT_CMD_CPD BIT20\r
	137	#define EFI_AHCI_PORT_CMD_ESP BIT21\r
	138	#define EFI_AHCI_PORT_CMD_ATAPI BIT24\r
	139	#define EFI_AHCI_PORT_CMD_DLAE BIT25\r
	140	#define EFI_AHCI_PORT_CMD_ALPE BIT26\r
	141	#define EFI_AHCI_PORT_CMD_ASP BIT27\r
	142	#define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 \| BIT29 \| BIT30 \| BIT31)\r
	143	#define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )\r
	144	#define EFI_AHCI_PORT_TFD 0x0020\r
	145	#define EFI_AHCI_PORT_TFD_MASK (BIT7 \| BIT3 \| BIT0)\r
	146	#define EFI_AHCI_PORT_TFD_BSY BIT7\r
	147	#define EFI_AHCI_PORT_TFD_DRQ BIT3\r
	148	#define EFI_AHCI_PORT_TFD_ERR BIT0\r
	149	#define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00\r
	150	#define EFI_AHCI_PORT_SIG 0x0024\r
	151	#define EFI_AHCI_PORT_SSTS 0x0028\r
	152	#define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F\r
	153	#define EFI_AHCI_PORT_SSTS_DET 0x0001\r
	154	#define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003\r
155	#define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0\r
156	#define EFI_AHCI_PORT_SCTL 0x002C\r
157	#define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F\r
158	#define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)\r
159	#define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001\r
160	#define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003\r
161	#define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0\r
162	#define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00\r
163	#define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300\r
164	#define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100\r
165	#define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200\r
166	#define EFI_AHCI_PORT_SERR 0x0030\r
167	#define EFI_AHCI_PORT_SERR_RDIE BIT0\r
168	#define EFI_AHCI_PORT_SERR_RCE BIT1\r
169	#define EFI_AHCI_PORT_SERR_TDIE BIT8\r
170	#define EFI_AHCI_PORT_SERR_PCDIE BIT9\r
171	#define EFI_AHCI_PORT_SERR_PE BIT10\r
172	#define EFI_AHCI_PORT_SERR_IE BIT11\r
173	#define EFI_AHCI_PORT_SERR_PRC BIT16\r
174	#define EFI_AHCI_PORT_SERR_PIE BIT17\r
175	#define EFI_AHCI_PORT_SERR_CW BIT18\r
176	#define EFI_AHCI_PORT_SERR_BDE BIT19\r
177	#define EFI_AHCI_PORT_SERR_DE BIT20\r
178	#define EFI_AHCI_PORT_SERR_CRCE BIT21\r
179	#define EFI_AHCI_PORT_SERR_HE BIT22\r
180	#define EFI_AHCI_PORT_SERR_LSE BIT23\r
181	#define EFI_AHCI_PORT_SERR_TSTE BIT24\r
182	#define EFI_AHCI_PORT_SERR_UFT BIT25\r
183	#define EFI_AHCI_PORT_SERR_EX BIT26\r
184	#define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF\r
185	#define EFI_AHCI_PORT_SACT 0x0034\r
186	#define EFI_AHCI_PORT_CI 0x0038\r
187	#define EFI_AHCI_PORT_SNTF 0x003C\r
188	#define AHCI_PORT_DEVSLP 0x0044\r
189	#define AHCI_PORT_DEVSLP_ADSE BIT0\r
190	#define AHCI_PORT_DEVSLP_DSP BIT1\r
191	#define AHCI_PORT_DEVSLP_DETO_MASK 0x000003FC\r
192	#define AHCI_PORT_DEVSLP_MDAT_MASK 0x00007C00\r
193	#define AHCI_PORT_DEVSLP_DITO_MASK 0x01FF8000\r
194	#define AHCI_PORT_DEVSLP_DM_MASK 0x1E000000\r
a41b5272	195	\r
db7afaee	196	#define AHCI_COMMAND_RETRIES (PcdGet32 (PcdAhciCommandRetryCount))\r
64e25d4b	197	\r
a41b5272	198	#pragma pack(1)\r
	199	//\r
	200	// Command List structure includes total 32 entries.\r
	201	// The entry data structure is listed at the following.\r
	202	//\r
	203	typedef struct {\r
1436aea4 MK	204	UINT32 AhciCmdCfl : 5; // Command FIS Length\r
	205	UINT32 AhciCmdA : 1; // ATAPI\r
	206	UINT32 AhciCmdW : 1; // Write\r
	207	UINT32 AhciCmdP : 1; // Prefetchable\r
	208	UINT32 AhciCmdR : 1; // Reset\r
	209	UINT32 AhciCmdB : 1; // BIST\r
	210	UINT32 AhciCmdC : 1; // Clear Busy upon R_OK\r
	211	UINT32 AhciCmdRsvd : 1;\r
	212	UINT32 AhciCmdPmp : 4; // Port Multiplier Port\r
	213	UINT32 AhciCmdPrdtl : 16; // Physical Region Descriptor Table Length\r
	214	UINT32 AhciCmdPrdbc; // Physical Region Descriptor Byte Count\r
	215	UINT32 AhciCmdCtba; // Command Table Descriptor Base Address\r
	216	UINT32 AhciCmdCtbau; // Command Table Descriptor Base Address Upper 32-BITs\r
	217	UINT32 AhciCmdRsvd1[4];\r
a41b5272	218	} EFI_AHCI_COMMAND_LIST;\r
	219	\r
	220	//\r
	221	// This is a software constructed FIS.\r
d1102dba	222	// For data transfer operations, this is the H2D Register FIS format as\r
a41b5272	223	// specified in the Serial ATA Revision 2.6 specification.\r
	224	//\r
	225	typedef struct {\r
	226	UINT8 AhciCFisType;\r
1436aea4 MK	227	UINT8 AhciCFisPmNum : 4;\r
	228	UINT8 AhciCFisRsvd : 1;\r
	229	UINT8 AhciCFisRsvd1 : 1;\r
	230	UINT8 AhciCFisRsvd2 : 1;\r
	231	UINT8 AhciCFisCmdInd : 1;\r
a41b5272	232	UINT8 AhciCFisCmd;\r
	233	UINT8 AhciCFisFeature;\r
	234	UINT8 AhciCFisSecNum;\r
	235	UINT8 AhciCFisClyLow;\r
	236	UINT8 AhciCFisClyHigh;\r
	237	UINT8 AhciCFisDevHead;\r
	238	UINT8 AhciCFisSecNumExp;\r
	239	UINT8 AhciCFisClyLowExp;\r
	240	UINT8 AhciCFisClyHighExp;\r
	241	UINT8 AhciCFisFeatureExp;\r
	242	UINT8 AhciCFisSecCount;\r
	243	UINT8 AhciCFisSecCountExp;\r
	244	UINT8 AhciCFisRsvd3;\r
	245	UINT8 AhciCFisControl;\r
	246	UINT8 AhciCFisRsvd4[4];\r
	247	UINT8 AhciCFisRsvd5[44];\r
	248	} EFI_AHCI_COMMAND_FIS;\r
	249	\r
cc28ab7a AM	250	typedef enum {\r
	251	SataFisD2H = 0,\r
	252	SataFisPioSetup,\r
	253	SataFisDmaSetup\r
	254	} SATA_FIS_TYPE;\r
	255	\r
a41b5272	256	//\r
	257	// ACMD: ATAPI command (12 or 16 bytes)\r
	258	//\r
	259	typedef struct {\r
	260	UINT8 AtapiCmd[0x10];\r
	261	} EFI_AHCI_ATAPI_COMMAND;\r
	262	\r
	263	//\r
	264	// Physical Region Descriptor Table includes up to 65535 entries\r
	265	// The entry data structure is listed at the following.\r
	266	// the actual entry number comes from the PRDTL field in the command\r
d1102dba	267	// list entry for this command slot.\r
a41b5272	268	//\r
a41b5272	269	typedef struct {\r
1436aea4 MK	270	UINT32 AhciPrdtDba; // Data Base Address\r
	271	UINT32 AhciPrdtDbau; // Data Base Address Upper 32-BITs\r
	272	UINT32 AhciPrdtRsvd;\r
	273	UINT32 AhciPrdtDbc : 22; // Data Byte Count\r
	274	UINT32 AhciPrdtRsvd1 : 9;\r
	275	UINT32 AhciPrdtIoc : 1; // Interrupt on Completion\r
a41b5272	276	} EFI_AHCI_COMMAND_PRDT;\r
	277	\r
	278	//\r
8c39253d	279	// Command table data structure which is pointed to by the entry in the command list\r
a41b5272	280	//\r
	281	typedef struct {\r
	282	EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r
	283	EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r
	284	UINT8 Reserved[0x30];\r
	285	EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer\r
	286	} EFI_AHCI_COMMAND_TABLE;\r
	287	\r
	288	//\r
	289	// Received FIS structure\r
	290	//\r
	291	typedef struct {\r
1436aea4 MK	292	UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r
	293	UINT8 AhciDmaSetupFisRsvd[0x04];\r
	294	UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r
	295	UINT8 AhciPioSetupFisRsvd[0x0C];\r
	296	UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r
	297	UINT8 AhciD2HRegisterFisRsvd[0x04];\r
	298	UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r
	299	UINT8 AhciUnknownFis[0x40]; // Unknown Fis: offset 0x60\r
	300	UINT8 AhciUnknownFisRsvd[0x60];\r
d1102dba	301	} EFI_AHCI_RECEIVED_FIS;\r
a41b5272	302	\r
f3100a1a	303	typedef struct {\r
1436aea4 MK	304	UINT8 Madt : 5;\r
	305	UINT8 Reserved_5 : 3;\r
	306	UINT8 Deto;\r
	307	UINT16 Reserved_16;\r
	308	UINT32 Reserved_32 : 31;\r
	309	UINT32 Supported : 1;\r
f3100a1a RN	310	} DEVSLP_TIMING_VARIABLES;\r
f3100a1a RN	311	\r
a41b5272	312	#pragma pack()\r
	313	\r
	314	typedef struct {\r
	315	EFI_AHCI_RECEIVED_FIS *AhciRFis;\r
	316	EFI_AHCI_COMMAND_LIST *AhciCmdList;\r
	317	EFI_AHCI_COMMAND_TABLE *AhciCommandTable;\r
	318	EFI_AHCI_RECEIVED_FIS *AhciRFisPciAddr;\r
	319	EFI_AHCI_COMMAND_LIST *AhciCmdListPciAddr;\r
	320	EFI_AHCI_COMMAND_TABLE *AhciCommandTablePciAddr;\r
	321	UINT64 MaxCommandListSize;\r
	322	UINT64 MaxCommandTableSize;\r
	323	UINT64 MaxReceiveFisSize;\r
	324	VOID *MapRFis;\r
	325	VOID *MapCmdList;\r
	326	VOID *MapCommandTable;\r
	327	} EFI_AHCI_REGISTERS;\r
	328	\r
	329	/**\r
d1102dba	330	This function is used to send out ATAPI commands conforms to the Packet Command\r
a41b5272	331	with PIO Protocol.\r
	332	\r
	333	@param PciIo The PCI IO protocol instance.\r
	334	@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
d1102dba	335	@param Port The number of port.\r
a41b5272	336	@param PortMultiplier The number of port multiplier.\r
	337	@param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r
	338	\r
	339	@retval EFI_SUCCESS send out the ATAPI packet command successfully\r
	340	and device sends data successfully.\r
	341	@retval EFI_DEVICE_ERROR the device failed to send data.\r
	342	\r
	343	**/\r
	344	EFI_STATUS\r
	345	EFIAPI\r
	346	AhciPacketCommandExecute (\r
1436aea4 MK	347	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	348	IN EFI_AHCI_REGISTERS *AhciRegisters,\r
	349	IN UINT8 Port,\r
	350	IN UINT8 PortMultiplier,\r
	351	IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r
a41b5272	352	);\r
	353	\r
	354	/**\r
	355	Start command for give slot on specific port.\r
d1102dba	356	\r
a41b5272	357	@param PciIo The PCI IO protocol instance.\r
	358	@param Port The number of port.\r
	359	@param CommandSlot The number of CommandSlot.\r
8536cc4b	360	@param Timeout The timeout value of start, uses 100ns as a unit.\r
d1102dba	361	\r
a41b5272	362	@retval EFI_DEVICE_ERROR The command start unsuccessfully.\r
	363	@retval EFI_TIMEOUT The operation is time out.\r
	364	@retval EFI_SUCCESS The command start successfully.\r
	365	\r
	366	**/\r
	367	EFI_STATUS\r
	368	EFIAPI\r
	369	AhciStartCommand (\r
1436aea4 MK	370	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	371	IN UINT8 Port,\r
	372	IN UINT8 CommandSlot,\r
	373	IN UINT64 Timeout\r
a41b5272	374	);\r
	375	\r
	376	/**\r
	377	Stop command running for giving port\r
d1102dba	378	\r
a41b5272	379	@param PciIo The PCI IO protocol instance.\r
a41b5272	380	@param Port The number of port.\r
8536cc4b	381	@param Timeout The timeout value of stop, uses 100ns as a unit.\r
d1102dba	382	\r
a41b5272	383	@retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r
	384	@retval EFI_TIMEOUT The operation is time out.\r
	385	@retval EFI_SUCCESS The command stop successfully.\r
	386	\r
	387	**/\r
	388	EFI_STATUS\r
	389	EFIAPI\r
	390	AhciStopCommand (\r
1436aea4 MK	391	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	392	IN UINT8 Port,\r
	393	IN UINT64 Timeout\r
a41b5272	394	);\r
a41b5272	395	\r
a41b5272	396	#endif\r