[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / AhciMode.h

/** @file\r
  Header file for AHCI mode of ATA host controller.\r
  \r
  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
#ifndef __ATA_HC_AHCI_MODE_H__\r
#define __ATA_HC_AHCI_MODE_H__\r
\r
#define EFI_AHCI_BAR_INDEX                     0x05\r
\r
#define EFI_AHCI_CAPABILITY_OFFSET             0x0000\r
#define EFI_AHCI_GHC_OFFSET                    0x0004\r
#define   EFI_AHCI_GHC_RESET                   BIT0\r
#define   EFI_AHCI_GHC_IE                      BIT1\r
#define   EFI_AHCI_GHC_ENABLE                  BIT31\r
#define EFI_AHCI_IS_OFFSET                     0x0008\r
#define EFI_AHCI_PI_OFFSET                     0x000C\r
\r
typedef struct {\r
  UINT32  Lower32;\r
  UINT32  Upper32;\r
} DATA_32;\r
\r
typedef union {\r
  DATA_32   Uint32;\r
  UINT64    Uint64;\r
} DATA_64;\r
\r
#define  EFI_AHCI_ATAPI_DEVICE_SIG             0xEB140000\r
#define  EFI_AHCI_ATA_DEVICE_SIG               0x00000000\r
#define  EFI_AHCI_PORT_MULTIPLIER_SIG          0x96690000\r
#define  EFI_AHCI_ATAPI_SIG_MASK               0xFFFF0000\r
\r
//\r
// Each PRDT entry can point to a memory block up to 4M byte\r
//\r
#define EFI_AHCI_MAX_DATA_PER_PRDT             0x400000\r
\r
#define EFI_AHCI_FIS_REGISTER_H2D              0x27      //Register FIS - Host to Device\r
#define   EFI_AHCI_FIS_REGISTER_H2D_LENGTH     20 \r
#define EFI_AHCI_FIS_REGISTER_D2H              0x34      //Register FIS - Device to Host\r
#define   EFI_AHCI_FIS_REGISTER_D2H_LENGTH     20\r
#define EFI_AHCI_FIS_DMA_ACTIVATE              0x39      //DMA Activate FIS - Device to Host\r
#define   EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH     4\r
#define EFI_AHCI_FIS_DMA_SETUP                 0x41      //DMA Setup FIS - Bi-directional\r
#define   EFI_AHCI_FIS_DMA_SETUP_LENGTH        28\r
#define EFI_AHCI_FIS_DATA                      0x46      //Data FIS - Bi-directional\r
#define EFI_AHCI_FIS_BIST                      0x58      //BIST Activate FIS - Bi-directional\r
#define   EFI_AHCI_FIS_BIST_LENGTH             12\r
#define EFI_AHCI_FIS_PIO_SETUP                 0x5F      //PIO Setup FIS - Device to Host\r
#define   EFI_AHCI_FIS_PIO_SETUP_LENGTH        20\r
#define EFI_AHCI_FIS_SET_DEVICE                0xA1      //Set Device Bits FIS - Device to Host\r
#define   EFI_AHCI_FIS_SET_DEVICE_LENGTH       8\r
\r
#define EFI_AHCI_D2H_FIS_OFFSET                0x40\r
#define EFI_AHCI_DMA_FIS_OFFSET                0x00\r
#define EFI_AHCI_PIO_FIS_OFFSET                0x20\r
#define EFI_AHCI_SDB_FIS_OFFSET                0x58\r
#define EFI_AHCI_FIS_TYPE_MASK                 0xFF\r
#define EFI_AHCI_U_FIS_OFFSET                  0x60\r
\r
//\r
// Port register\r
//\r
#define EFI_AHCI_PORT_START                    0x0100\r
#define EFI_AHCI_PORT_REG_WIDTH                0x0080\r
#define EFI_AHCI_PORT_CLB                      0x0000\r
#define EFI_AHCI_PORT_CLBU                     0x0004\r
#define EFI_AHCI_PORT_FB                       0x0008\r
#define EFI_AHCI_PORT_FBU                      0x000C\r
#define EFI_AHCI_PORT_IS                       0x0010\r
#define   EFI_AHCI_PORT_IS_DHRS                BIT0\r
#define   EFI_AHCI_PORT_IS_PSS                 BIT1\r
#define   EFI_AHCI_PORT_IS_SSS                 BIT2\r
#define   EFI_AHCI_PORT_IS_SDBS                BIT3\r
#define   EFI_AHCI_PORT_IS_UFS                 BIT4\r
#define   EFI_AHCI_PORT_IS_DPS                 BIT5\r
#define   EFI_AHCI_PORT_IS_PCS                 BIT6\r
#define   EFI_AHCI_PORT_IS_DIS                 BIT7\r
#define   EFI_AHCI_PORT_IS_PRCS                BIT22\r
#define   EFI_AHCI_PORT_IS_IPMS                BIT23\r
#define   EFI_AHCI_PORT_IS_OFS                 BIT24\r
#define   EFI_AHCI_PORT_IS_INFS                BIT26\r
#define   EFI_AHCI_PORT_IS_IFS                 BIT27\r
#define   EFI_AHCI_PORT_IS_HBDS                BIT28\r
#define   EFI_AHCI_PORT_IS_HBFS                BIT29\r
#define   EFI_AHCI_PORT_IS_TFES                BIT30\r
#define   EFI_AHCI_PORT_IS_CPDS                BIT31\r
#define   EFI_AHCI_PORT_IS_CLEAR               0xFFFFFFFF\r
#define   EFI_AHCI_PORT_IS_FIS_CLEAR           0x0000000F\r
\r
#define EFI_AHCI_PORT_IE                       0x0014\r
#define EFI_AHCI_PORT_CMD                      0x0018\r
#define   EFI_AHCI_PORT_CMD_ST_MASK            0xFFFFFFFE\r
#define   EFI_AHCI_PORT_CMD_ST                 BIT0\r
#define   EFI_AHCI_PORT_CMD_SUD                BIT1\r
#define   EFI_AHCI_PORT_CMD_POD                BIT2\r
#define   EFI_AHCI_PORT_CMD_COL                BIT3\r
#define   EFI_AHCI_PORT_CMD_CR                 BIT15\r
#define   EFI_AHCI_PORT_CMD_FRE                BIT4\r
#define   EFI_AHCI_PORT_CMD_FR                 BIT14\r
#define   EFI_AHCI_PORT_CMD_MASK               ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)\r
#define   EFI_AHCI_PORT_CMD_PMA                BIT17\r
#define   EFI_AHCI_PORT_CMD_HPCP               BIT18\r
#define   EFI_AHCI_PORT_CMD_MPSP               BIT19\r
#define   EFI_AHCI_PORT_CMD_CPD                BIT20\r
#define   EFI_AHCI_PORT_CMD_ESP                BIT21\r
#define   EFI_AHCI_PORT_CMD_ATAPI              BIT24\r
#define   EFI_AHCI_PORT_CMD_DLAE               BIT25\r
#define   EFI_AHCI_PORT_CMD_ALPE               BIT26\r
#define   EFI_AHCI_PORT_CMD_ASP                BIT27\r
#define   EFI_AHCI_PORT_CMD_ICC_MASK           (BIT28 | BIT29 | BIT30 | BIT31)\r
#define   EFI_AHCI_PORT_CMD_ACTIVE             (1 << 28 )\r
#define EFI_AHCI_PORT_TFD                      0x0020\r
#define   EFI_AHCI_PORT_TFD_MASK               (BIT7 | BIT3 | BIT0)\r
#define   EFI_AHCI_PORT_TFD_BSY                BIT7\r
#define   EFI_AHCI_PORT_TFD_DRQ                BIT3\r
#define   EFI_AHCI_PORT_TFD_ERR                BIT0\r
#define   EFI_AHCI_PORT_TFD_ERR_MASK           0x00FF00\r
#define EFI_AHCI_PORT_SIG                      0x0024\r
#define EFI_AHCI_PORT_SSTS                     0x0028\r
#define   EFI_AHCI_PORT_SSTS_DET_MASK          0x000F\r
#define   EFI_AHCI_PORT_SSTS_DET               0x0001\r
#define   EFI_AHCI_PORT_SSTS_DET_PCE           0x0003\r
#define   EFI_AHCI_PORT_SSTS_SPD_MASK          0x00F0\r
#define EFI_AHCI_PORT_SCTL                     0x002C\r
#define   EFI_AHCI_PORT_SCTL_DET_MASK          0x000F\r
#define   EFI_AHCI_PORT_SCTL_MASK              (~EFI_AHCI_PORT_SCTL_DET_MASK)\r
#define   EFI_AHCI_PORT_SCTL_DET_INIT          0x0001\r
#define   EFI_AHCI_PORT_SCTL_DET_PHYCOMM       0x0003\r
#define   EFI_AHCI_PORT_SCTL_SPD_MASK          0x00F0\r
#define   EFI_AHCI_PORT_SCTL_IPM_MASK          0x0F00\r
#define   EFI_AHCI_PORT_SCTL_IPM_INIT          0x0300\r
#define   EFI_AHCI_PORT_SCTL_IPM_PSD           0x0100\r
#define   EFI_AHCI_PORT_SCTL_IPM_SSD           0x0200\r
#define EFI_AHCI_PORT_SERR                     0x0030\r
#define   EFI_AHCI_PORT_SERR_RDIE              BIT0\r
#define   EFI_AHCI_PORT_SERR_RCE               BIT1\r
#define   EFI_AHCI_PORT_SERR_TDIE              BIT8\r
#define   EFI_AHCI_PORT_SERR_PCDIE             BIT9\r
#define   EFI_AHCI_PORT_SERR_PE                BIT10\r
#define   EFI_AHCI_PORT_SERR_IE                BIT11\r
#define   EFI_AHCI_PORT_SERR_PRC               BIT16\r
#define   EFI_AHCI_PORT_SERR_PIE               BIT17\r
#define   EFI_AHCI_PORT_SERR_CW                BIT18\r
#define   EFI_AHCI_PORT_SERR_BDE               BIT19\r
#define   EFI_AHCI_PORT_SERR_DE                BIT20\r
#define   EFI_AHCI_PORT_SERR_CRCE              BIT21\r
#define   EFI_AHCI_PORT_SERR_HE                BIT22\r
#define   EFI_AHCI_PORT_SERR_LSE               BIT23\r
#define   EFI_AHCI_PORT_SERR_TSTE              BIT24\r
#define   EFI_AHCI_PORT_SERR_UFT               BIT25\r
#define   EFI_AHCI_PORT_SERR_EX                BIT26\r
#define   EFI_AHCI_PORT_ERR_CLEAR              0xFFFFFFFF\r
#define EFI_AHCI_PORT_SACT                     0x0034\r
#define EFI_AHCI_PORT_CI                       0x0038\r
#define EFI_AHCI_PORT_SNTF                     0x003C\r
\r
\r
#pragma pack(1)\r
//\r
// Command List structure includes total 32 entries.\r
// The entry data structure is listed at the following.\r
//\r
typedef struct {\r
  UINT32   AhciCmdCfl:5;      //Command FIS Length\r
  UINT32   AhciCmdA:1;        //ATAPI\r
  UINT32   AhciCmdW:1;        //Write\r
  UINT32   AhciCmdP:1;        //Prefetchable\r
  UINT32   AhciCmdR:1;        //Reset\r
  UINT32   AhciCmdB:1;        //BIST\r
  UINT32   AhciCmdC:1;        //Clear Busy upon R_OK\r
  UINT32   AhciCmdRsvd:1;\r
  UINT32   AhciCmdPmp:4;      //Port Multiplier Port\r
  UINT32   AhciCmdPrdtl:16;   //Physical Region Descriptor Table Length\r
  UINT32   AhciCmdPrdbc;      //Physical Region Descriptor Byte Count\r
  UINT32   AhciCmdCtba;       //Command Table Descriptor Base Address\r
  UINT32   AhciCmdCtbau;      //Command Table Descriptor Base Address Upper 32-BITs\r
  UINT32   AhciCmdRsvd1[4]; \r
} EFI_AHCI_COMMAND_LIST;\r
\r
//\r
// This is a software constructed FIS.\r
// For data transfer operations, this is the H2D Register FIS format as \r
// specified in the Serial ATA Revision 2.6 specification.\r
//\r
typedef struct {\r
  UINT8    AhciCFisType;\r
  UINT8    AhciCFisPmNum:4;\r
  UINT8    AhciCFisRsvd:1;\r
  UINT8    AhciCFisRsvd1:1;\r
  UINT8    AhciCFisRsvd2:1;\r
  UINT8    AhciCFisCmdInd:1;\r
  UINT8    AhciCFisCmd;\r
  UINT8    AhciCFisFeature;\r
  UINT8    AhciCFisSecNum;\r
  UINT8    AhciCFisClyLow;\r
  UINT8    AhciCFisClyHigh;\r
  UINT8    AhciCFisDevHead;\r
  UINT8    AhciCFisSecNumExp;\r
  UINT8    AhciCFisClyLowExp;\r
  UINT8    AhciCFisClyHighExp;\r
  UINT8    AhciCFisFeatureExp;\r
  UINT8    AhciCFisSecCount;\r
  UINT8    AhciCFisSecCountExp;\r
  UINT8    AhciCFisRsvd3;\r
  UINT8    AhciCFisControl;\r
  UINT8    AhciCFisRsvd4[4];\r
  UINT8    AhciCFisRsvd5[44];\r
} EFI_AHCI_COMMAND_FIS;\r
\r
//\r
// ACMD: ATAPI command (12 or 16 bytes)\r
//\r
typedef struct {\r
  UINT8    AtapiCmd[0x10];\r
} EFI_AHCI_ATAPI_COMMAND;\r
\r
//\r
// Physical Region Descriptor Table includes up to 65535 entries\r
// The entry data structure is listed at the following.\r
// the actual entry number comes from the PRDTL field in the command\r
// list entry for this command slot. \r
//\r
typedef struct {\r
  UINT32   AhciPrdtDba;       //Data Base Address\r
  UINT32   AhciPrdtDbau;      //Data Base Address Upper 32-BITs\r
  UINT32   AhciPrdtRsvd;\r
  UINT32   AhciPrdtDbc:22;    //Data Byte Count\r
  UINT32   AhciPrdtRsvd1:9;\r
  UINT32   AhciPrdtIoc:1;     //Interrupt on Completion\r
} EFI_AHCI_COMMAND_PRDT;\r
\r
//\r
// Command table data strucute which is pointed to by the entry in the command list\r
//\r
typedef struct {\r
  EFI_AHCI_COMMAND_FIS      CommandFis;       // A software constructed FIS.\r
  EFI_AHCI_ATAPI_COMMAND    AtapiCmd;         // 12 or 16 bytes ATAPI cmd.\r
  UINT8                     Reserved[0x30];\r
  EFI_AHCI_COMMAND_PRDT     PrdtTable[65535];     // The scatter/gather list for data transfer\r
} EFI_AHCI_COMMAND_TABLE;\r
\r
//\r
// Received FIS structure\r
//\r
typedef struct {\r
  UINT8    AhciDmaSetupFis[0x1C];         // Dma Setup Fis: offset 0x00\r
  UINT8    AhciDmaSetupFisRsvd[0x04];\r
  UINT8    AhciPioSetupFis[0x14];         // Pio Setup Fis: offset 0x20\r
  UINT8    AhciPioSetupFisRsvd[0x0C];     \r
  UINT8    AhciD2HRegisterFis[0x14];      // D2H Register Fis: offset 0x40\r
  UINT8    AhciD2HRegisterFisRsvd[0x04];\r
  UINT64   AhciSetDeviceBitsFis;          // Set Device Bits Fix: offset 0x58\r
  UINT8    AhciUnknownFis[0x40];          // Unkonwn Fis: offset 0x60\r
  UINT8    AhciUnknownFisRsvd[0x60];      \r
} EFI_AHCI_RECEIVED_FIS; \r
\r
#pragma pack()\r
\r
typedef struct {\r
  EFI_AHCI_RECEIVED_FIS     *AhciRFis;\r
  EFI_AHCI_COMMAND_LIST     *AhciCmdList;\r
  EFI_AHCI_COMMAND_TABLE    *AhciCommandTable;\r
  EFI_AHCI_RECEIVED_FIS     *AhciRFisPciAddr;\r
  EFI_AHCI_COMMAND_LIST     *AhciCmdListPciAddr;\r
  EFI_AHCI_COMMAND_TABLE    *AhciCommandTablePciAddr;\r
  UINT64                    MaxCommandListSize;\r
  UINT64                    MaxCommandTableSize;\r
  UINT64                    MaxReceiveFisSize;\r
  VOID                      *MapRFis;\r
  VOID                      *MapCmdList;\r
  VOID                      *MapCommandTable;\r
} EFI_AHCI_REGISTERS;\r
\r
/**\r
  This function is used to send out ATAPI commands conforms to the Packet Command \r
  with PIO Protocol.\r
\r
  @param PciIo              The PCI IO protocol instance.\r
  @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.\r
  @param Port               The number of port.     \r
  @param PortMultiplier     The number of port multiplier.\r
  @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r
\r
  @retval EFI_SUCCESS       send out the ATAPI packet command successfully\r
                            and device sends data successfully.\r
  @retval EFI_DEVICE_ERROR  the device failed to send data.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
AhciPacketCommandExecute (\r
  IN  EFI_PCI_IO_PROTOCOL                           *PciIo,\r
  IN  EFI_AHCI_REGISTERS                            *AhciRegisters,\r
  IN  UINT8                                         Port,\r
  IN  UINT8                                         PortMultiplier,\r
  IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet\r
  );\r
\r
/**\r
  Start command for give slot on specific port.\r
    \r
  @param  PciIo              The PCI IO protocol instance.\r
  @param  Port               The number of port.\r
  @param  CommandSlot        The number of CommandSlot.\r
  @param  Timeout            The timeout value of start.\r
   \r
  @retval EFI_DEVICE_ERROR   The command start unsuccessfully.\r
  @retval EFI_TIMEOUT        The operation is time out.\r
  @retval EFI_SUCCESS        The command start successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
AhciStartCommand (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     Port,\r
  IN  UINT8                     CommandSlot,\r
  IN  UINT64                    Timeout\r
  );\r
\r
/**\r
  Stop command running for giving port\r
    \r
  @param  PciIo              The PCI IO protocol instance.\r
  @param  Port               The number of port.\r
  @param  Timeout            The timeout value of stop.\r
   \r
  @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.\r
  @retval EFI_TIMEOUT        The operation is time out.\r
  @retval EFI_SUCCESS        The command stop successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
AhciStopCommand (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     Port,\r
  IN  UINT64                    Timeout\r
  );\r
\r
#endif\r
\r
Commit	Line	Data
a41b5272	1	/** @file\r
	2	Header file for AHCI mode of ATA host controller.\r
	3	\r
490b5ea1	4	Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
a41b5272	5	This program and the accompanying materials \r
	6	are licensed and made available under the terms and conditions of the BSD License \r
	7	which accompanies this distribution. The full text of the license may be found at \r
	8	http://opensource.org/licenses/bsd-license.php \r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	\r
	13	**/\r
	14	#ifndef __ATA_HC_AHCI_MODE_H__\r
	15	#define __ATA_HC_AHCI_MODE_H__\r
	16	\r
	17	#define EFI_AHCI_BAR_INDEX 0x05\r
	18	\r
	19	#define EFI_AHCI_CAPABILITY_OFFSET 0x0000\r
	20	#define EFI_AHCI_GHC_OFFSET 0x0004\r
	21	#define EFI_AHCI_GHC_RESET BIT0\r
	22	#define EFI_AHCI_GHC_IE BIT1\r
	23	#define EFI_AHCI_GHC_ENABLE BIT31\r
	24	#define EFI_AHCI_IS_OFFSET 0x0008\r
	25	#define EFI_AHCI_PI_OFFSET 0x000C\r
	26	\r
	27	typedef struct {\r
	28	UINT32 Lower32;\r
	29	UINT32 Upper32;\r
	30	} DATA_32;\r
	31	\r
	32	typedef union {\r
	33	DATA_32 Uint32;\r
	34	UINT64 Uint64;\r
	35	} DATA_64;\r
	36	\r
	37	#define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000\r
	38	#define EFI_AHCI_ATA_DEVICE_SIG 0x00000000\r
	39	#define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000\r
	40	#define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000\r
	41	\r
	42	//\r
	43	// Each PRDT entry can point to a memory block up to 4M byte\r
	44	//\r
	45	#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000\r
	46	\r
	47	#define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r
	48	#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20 \r
	49	#define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r
	50	#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20\r
	51	#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host\r
	52	#define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4\r
	53	#define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional\r
	54	#define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28\r
	55	#define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional\r
	56	#define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional\r
	57	#define EFI_AHCI_FIS_BIST_LENGTH 12\r
	58	#define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host\r
	59	#define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20\r
	60	#define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host\r
	61	#define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8\r
	62	\r
	63	#define EFI_AHCI_D2H_FIS_OFFSET 0x40\r
	64	#define EFI_AHCI_DMA_FIS_OFFSET 0x00\r
	65	#define EFI_AHCI_PIO_FIS_OFFSET 0x20\r
	66	#define EFI_AHCI_SDB_FIS_OFFSET 0x58\r
	67	#define EFI_AHCI_FIS_TYPE_MASK 0xFF\r
	68	#define EFI_AHCI_U_FIS_OFFSET 0x60\r
69	\r
70	//\r
71	// Port register\r
72	//\r
73	#define EFI_AHCI_PORT_START 0x0100\r
74	#define EFI_AHCI_PORT_REG_WIDTH 0x0080\r
75	#define EFI_AHCI_PORT_CLB 0x0000\r
76	#define EFI_AHCI_PORT_CLBU 0x0004\r
77	#define EFI_AHCI_PORT_FB 0x0008\r
78	#define EFI_AHCI_PORT_FBU 0x000C\r
79	#define EFI_AHCI_PORT_IS 0x0010\r
80	#define EFI_AHCI_PORT_IS_DHRS BIT0\r
81	#define EFI_AHCI_PORT_IS_PSS BIT1\r
82	#define EFI_AHCI_PORT_IS_SSS BIT2\r
83	#define EFI_AHCI_PORT_IS_SDBS BIT3\r
84	#define EFI_AHCI_PORT_IS_UFS BIT4\r
85	#define EFI_AHCI_PORT_IS_DPS BIT5\r
86	#define EFI_AHCI_PORT_IS_PCS BIT6\r
87	#define EFI_AHCI_PORT_IS_DIS BIT7\r
88	#define EFI_AHCI_PORT_IS_PRCS BIT22\r
89	#define EFI_AHCI_PORT_IS_IPMS BIT23\r
90	#define EFI_AHCI_PORT_IS_OFS BIT24\r
91	#define EFI_AHCI_PORT_IS_INFS BIT26\r
92	#define EFI_AHCI_PORT_IS_IFS BIT27\r
93	#define EFI_AHCI_PORT_IS_HBDS BIT28\r
94	#define EFI_AHCI_PORT_IS_HBFS BIT29\r
95	#define EFI_AHCI_PORT_IS_TFES BIT30\r
96	#define EFI_AHCI_PORT_IS_CPDS BIT31\r
97	#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF\r
98	#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F\r
99	\r
100	#define EFI_AHCI_PORT_IE 0x0014\r
101	#define EFI_AHCI_PORT_CMD 0x0018\r
102	#define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE\r
103	#define EFI_AHCI_PORT_CMD_ST BIT0\r
104	#define EFI_AHCI_PORT_CMD_SUD BIT1\r
105	#define EFI_AHCI_PORT_CMD_POD BIT2\r
106	#define EFI_AHCI_PORT_CMD_COL BIT3\r
107	#define EFI_AHCI_PORT_CMD_CR BIT15\r
108	#define EFI_AHCI_PORT_CMD_FRE BIT4\r
109	#define EFI_AHCI_PORT_CMD_FR BIT14\r
110	#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST \| EFI_AHCI_PORT_CMD_FRE \| EFI_AHCI_PORT_CMD_COL)\r
111	#define EFI_AHCI_PORT_CMD_PMA BIT17\r
112	#define EFI_AHCI_PORT_CMD_HPCP BIT18\r
113	#define EFI_AHCI_PORT_CMD_MPSP BIT19\r
114	#define EFI_AHCI_PORT_CMD_CPD BIT20\r
115	#define EFI_AHCI_PORT_CMD_ESP BIT21\r
116	#define EFI_AHCI_PORT_CMD_ATAPI BIT24\r
117	#define EFI_AHCI_PORT_CMD_DLAE BIT25\r
118	#define EFI_AHCI_PORT_CMD_ALPE BIT26\r
119	#define EFI_AHCI_PORT_CMD_ASP BIT27\r
120	#define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 \| BIT29 \| BIT30 \| BIT31)\r
121	#define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )\r
122	#define EFI_AHCI_PORT_TFD 0x0020\r
123	#define EFI_AHCI_PORT_TFD_MASK (BIT7 \| BIT3 \| BIT0)\r
124	#define EFI_AHCI_PORT_TFD_BSY BIT7\r
125	#define EFI_AHCI_PORT_TFD_DRQ BIT3\r
126	#define EFI_AHCI_PORT_TFD_ERR BIT0\r
127	#define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00\r
128	#define EFI_AHCI_PORT_SIG 0x0024\r
129	#define EFI_AHCI_PORT_SSTS 0x0028\r
130	#define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F\r
131	#define EFI_AHCI_PORT_SSTS_DET 0x0001\r
132	#define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003\r
133	#define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0\r
134	#define EFI_AHCI_PORT_SCTL 0x002C\r
135	#define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F\r
136	#define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)\r
137	#define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001\r
138	#define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003\r
139	#define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0\r
140	#define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00\r
141	#define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300\r
142	#define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100\r
143	#define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200\r
144	#define EFI_AHCI_PORT_SERR 0x0030\r
145	#define EFI_AHCI_PORT_SERR_RDIE BIT0\r
146	#define EFI_AHCI_PORT_SERR_RCE BIT1\r
147	#define EFI_AHCI_PORT_SERR_TDIE BIT8\r
148	#define EFI_AHCI_PORT_SERR_PCDIE BIT9\r
149	#define EFI_AHCI_PORT_SERR_PE BIT10\r
150	#define EFI_AHCI_PORT_SERR_IE BIT11\r
151	#define EFI_AHCI_PORT_SERR_PRC BIT16\r
152	#define EFI_AHCI_PORT_SERR_PIE BIT17\r
153	#define EFI_AHCI_PORT_SERR_CW BIT18\r
154	#define EFI_AHCI_PORT_SERR_BDE BIT19\r
155	#define EFI_AHCI_PORT_SERR_DE BIT20\r
156	#define EFI_AHCI_PORT_SERR_CRCE BIT21\r
490b5ea1	157	#define EFI_AHCI_PORT_SERR_HE BIT22\r
a41b5272	158	#define EFI_AHCI_PORT_SERR_LSE BIT23\r
	159	#define EFI_AHCI_PORT_SERR_TSTE BIT24\r
	160	#define EFI_AHCI_PORT_SERR_UFT BIT25\r
	161	#define EFI_AHCI_PORT_SERR_EX BIT26\r
	162	#define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF\r
	163	#define EFI_AHCI_PORT_SACT 0x0034\r
	164	#define EFI_AHCI_PORT_CI 0x0038\r
	165	#define EFI_AHCI_PORT_SNTF 0x003C\r
	166	\r
	167	\r
	168	#pragma pack(1)\r
	169	//\r
	170	// Command List structure includes total 32 entries.\r
	171	// The entry data structure is listed at the following.\r
	172	//\r
	173	typedef struct {\r
	174	UINT32 AhciCmdCfl:5; //Command FIS Length\r
	175	UINT32 AhciCmdA:1; //ATAPI\r
	176	UINT32 AhciCmdW:1; //Write\r
	177	UINT32 AhciCmdP:1; //Prefetchable\r
	178	UINT32 AhciCmdR:1; //Reset\r
	179	UINT32 AhciCmdB:1; //BIST\r
	180	UINT32 AhciCmdC:1; //Clear Busy upon R_OK\r
	181	UINT32 AhciCmdRsvd:1;\r
	182	UINT32 AhciCmdPmp:4; //Port Multiplier Port\r
	183	UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length\r
	184	UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r
	185	UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r
	186	UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r
	187	UINT32 AhciCmdRsvd1[4]; \r
	188	} EFI_AHCI_COMMAND_LIST;\r
	189	\r
	190	//\r
	191	// This is a software constructed FIS.\r
	192	// For data transfer operations, this is the H2D Register FIS format as \r
	193	// specified in the Serial ATA Revision 2.6 specification.\r
	194	//\r
	195	typedef struct {\r
	196	UINT8 AhciCFisType;\r
	197	UINT8 AhciCFisPmNum:4;\r
	198	UINT8 AhciCFisRsvd:1;\r
	199	UINT8 AhciCFisRsvd1:1;\r
	200	UINT8 AhciCFisRsvd2:1;\r
	201	UINT8 AhciCFisCmdInd:1;\r
	202	UINT8 AhciCFisCmd;\r
	203	UINT8 AhciCFisFeature;\r
	204	UINT8 AhciCFisSecNum;\r
	205	UINT8 AhciCFisClyLow;\r
	206	UINT8 AhciCFisClyHigh;\r
	207	UINT8 AhciCFisDevHead;\r
	208	UINT8 AhciCFisSecNumExp;\r
	209	UINT8 AhciCFisClyLowExp;\r
	210	UINT8 AhciCFisClyHighExp;\r
	211	UINT8 AhciCFisFeatureExp;\r
	212	UINT8 AhciCFisSecCount;\r
	213	UINT8 AhciCFisSecCountExp;\r
	214	UINT8 AhciCFisRsvd3;\r
	215	UINT8 AhciCFisControl;\r
	216	UINT8 AhciCFisRsvd4[4];\r
	217	UINT8 AhciCFisRsvd5[44];\r
	218	} EFI_AHCI_COMMAND_FIS;\r
	219	\r
	220	//\r
	221	// ACMD: ATAPI command (12 or 16 bytes)\r
222	//\r
223	typedef struct {\r
224	UINT8 AtapiCmd[0x10];\r
225	} EFI_AHCI_ATAPI_COMMAND;\r
226	\r
227	//\r
228	// Physical Region Descriptor Table includes up to 65535 entries\r
229	// The entry data structure is listed at the following.\r
230	// the actual entry number comes from the PRDTL field in the command\r
231	// list entry for this command slot. \r
232	//\r
233	typedef struct {\r
234	UINT32 AhciPrdtDba; //Data Base Address\r
235	UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs\r
236	UINT32 AhciPrdtRsvd;\r
237	UINT32 AhciPrdtDbc:22; //Data Byte Count\r
238	UINT32 AhciPrdtRsvd1:9;\r
239	UINT32 AhciPrdtIoc:1; //Interrupt on Completion\r
240	} EFI_AHCI_COMMAND_PRDT;\r
241	\r
242	//\r
243	// Command table data strucute which is pointed to by the entry in the command list\r
244	//\r
245	typedef struct {\r
246	EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r
247	EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r
248	UINT8 Reserved[0x30];\r
249	EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer\r
250	} EFI_AHCI_COMMAND_TABLE;\r
251	\r
252	//\r
253	// Received FIS structure\r
254	//\r
255	typedef struct {\r
256	UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r
257	UINT8 AhciDmaSetupFisRsvd[0x04];\r
258	UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r
259	UINT8 AhciPioSetupFisRsvd[0x0C]; \r
260	UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r
261	UINT8 AhciD2HRegisterFisRsvd[0x04];\r
262	UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r
263	UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r
264	UINT8 AhciUnknownFisRsvd[0x60]; \r
265	} EFI_AHCI_RECEIVED_FIS; \r
266	\r
267	#pragma pack()\r
268	\r
269	typedef struct {\r
270	EFI_AHCI_RECEIVED_FIS *AhciRFis;\r
271	EFI_AHCI_COMMAND_LIST *AhciCmdList;\r
272	EFI_AHCI_COMMAND_TABLE *AhciCommandTable;\r
273	EFI_AHCI_RECEIVED_FIS *AhciRFisPciAddr;\r
274	EFI_AHCI_COMMAND_LIST *AhciCmdListPciAddr;\r
275	EFI_AHCI_COMMAND_TABLE *AhciCommandTablePciAddr;\r
276	UINT64 MaxCommandListSize;\r
277	UINT64 MaxCommandTableSize;\r
278	UINT64 MaxReceiveFisSize;\r
279	VOID *MapRFis;\r
280	VOID *MapCmdList;\r
281	VOID *MapCommandTable;\r
282	} EFI_AHCI_REGISTERS;\r
283	\r
284	/**\r
285	This function is used to send out ATAPI commands conforms to the Packet Command \r
286	with PIO Protocol.\r
287	\r
288	@param PciIo The PCI IO protocol instance.\r
289	@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
290	@param Port The number of port. \r
291	@param PortMultiplier The number of port multiplier.\r
292	@param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r
293	\r
294	@retval EFI_SUCCESS send out the ATAPI packet command successfully\r
295	and device sends data successfully.\r
296	@retval EFI_DEVICE_ERROR the device failed to send data.\r
297	\r
298	**/\r
299	EFI_STATUS\r
300	EFIAPI\r
301	AhciPacketCommandExecute (\r
302	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
303	IN EFI_AHCI_REGISTERS *AhciRegisters,\r
304	IN UINT8 Port,\r
305	IN UINT8 PortMultiplier,\r
306	IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r
307	);\r
308	\r
309	/**\r
310	Start command for give slot on specific port.\r
311	\r
312	@param PciIo The PCI IO protocol instance.\r
313	@param Port The number of port.\r
314	@param CommandSlot The number of CommandSlot.\r
315	@param Timeout The timeout value of start.\r
316	\r
317	@retval EFI_DEVICE_ERROR The command start unsuccessfully.\r
318	@retval EFI_TIMEOUT The operation is time out.\r
319	@retval EFI_SUCCESS The command start successfully.\r
320	\r
321	**/\r
322	EFI_STATUS\r
323	EFIAPI\r
324	AhciStartCommand (\r
325	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
326	IN UINT8 Port,\r
327	IN UINT8 CommandSlot,\r
328	IN UINT64 Timeout\r
329	);\r
330	\r
331	/**\r
332	Stop command running for giving port\r
333	\r
334	@param PciIo The PCI IO protocol instance.\r
335	@param Port The number of port.\r
336	@param Timeout The timeout value of stop.\r
337	\r
338	@retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r
339	@retval EFI_TIMEOUT The operation is time out.\r
340	@retval EFI_SUCCESS The command stop successfully.\r
341	\r
342	**/\r
343	EFI_STATUS\r
344	EFIAPI\r
345	AhciStopCommand (\r
346	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
347	IN UINT8 Port,\r
348	IN UINT64 Timeout\r
349	);\r
350	\r
a41b5272	351	#endif\r
a41b5272	352	\r