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913cb9dc 1/** @file\r
2\r
78c2ffb5 3 Provides some data struct used by EHCI controller driver.\r
4\r
913cb9dc 5Copyright (c) 2006 - 2007, Intel Corporation\r
6All rights reserved. This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
913cb9dc 14**/\r
15\r
16#ifndef _EFI_EHCI_H_\r
17#define _EFI_EHCI_H_\r
18\r
ed7748fe 19\r
60c93673 20#include <Uefi.h>\r
ed7748fe 21\r
913cb9dc 22#include <Protocol/Usb2HostController.h>\r
23#include <Protocol/PciIo.h>\r
ed7748fe 24\r
913cb9dc 25#include <Library/DebugLib.h>\r
26#include <Library/BaseMemoryLib.h>\r
27#include <Library/UefiDriverEntryPoint.h>\r
28#include <Library/UefiBootServicesTableLib.h>\r
29#include <Library/UefiLib.h>\r
30#include <Library/BaseLib.h>\r
31#include <Library/MemoryAllocationLib.h>\r
dd4047a5 32#include <Library/PcdLib.h>\r
913cb9dc 33\r
34#include <IndustryStandard/Pci22.h>\r
35\r
36typedef struct _USB2_HC_DEV USB2_HC_DEV;\r
37\r
38#include "UsbHcMem.h"\r
39#include "EhciReg.h"\r
40#include "EhciUrb.h"\r
41#include "EhciSched.h"\r
42#include "EhciDebug.h"\r
43\r
78c2ffb5 44typedef enum {\r
41e8ff27 45 EHC_1_MICROSECOND = 1,\r
46 EHC_1_MILLISECOND = 1000 * EHC_1_MICROSECOND,\r
47 EHC_1_SECOND = 1000 * EHC_1_MILLISECOND,\r
48\r
49 //\r
50 // EHCI register operation timeout, set by experience\r
51 //\r
52 EHC_RESET_TIMEOUT = 1 * EHC_1_SECOND,\r
53 EHC_GENERIC_TIMEOUT = 10 * EHC_1_MILLISECOND,\r
54\r
55 //\r
56 // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
57 //\r
58 EHC_ROOT_PORT_RECOVERY_STALL = 20 * EHC_1_MILLISECOND,\r
59\r
60 //\r
68246fa8 61 // Sync and Async transfer polling interval, set by experience,\r
41e8ff27 62 // and the unit of Async is 100us, means 50ms as interval.\r
63 //\r
64 EHC_SYNC_POLL_INTERVAL = 20 * EHC_1_MICROSECOND,\r
78c2ffb5 65 EHC_ASYNC_POLL_INTERVAL = 50 * 10000U\r
66} EHC_TIMEOUT_EXPERIENCE_VALUE;\r
67\r
41e8ff27 68\r
69 //\r
70 // EHC raises TPL to TPL_NOTIFY to serialize all its operations\r
71 // to protect shared data structures.\r
72 //\r
78c2ffb5 73#define EHC_TPL TPL_NOTIFY\r
41e8ff27 74\r
78c2ffb5 75#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
913cb9dc 76\r
77//\r
78//Iterate through the doule linked list. NOT delete safe\r
79//\r
80#define EFI_LIST_FOR_EACH(Entry, ListHead) \\r
81 for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)\r
82\r
83//\r
84//Iterate through the doule linked list. This is delete-safe.\r
85//Don't touch NextEntry\r
86//\r
87#define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \\r
88 for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\\r
89 Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)\r
90\r
91#define EFI_LIST_CONTAINER(Entry, Type, Field) _CR(Entry, Type, Field)\r
92\r
93\r
94#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
95#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
96#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
97\r
98#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r
99 (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r
100\r
101#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
102\r
c52fa98c 103struct _USB2_HC_DEV {\r
913cb9dc 104 UINTN Signature;\r
105 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
106\r
107 EFI_PCI_IO_PROTOCOL *PciIo;\r
68246fa8 108 UINT64 OriginalPciAttributes;\r
913cb9dc 109 USBHC_MEM_POOL *MemPool;\r
110\r
111 //\r
112 // Schedule data shared between asynchronous and periodic\r
113 // transfers:\r
114 // ShortReadStop, as its name indicates, is used to terminate\r
115 // the short read except the control transfer. EHCI follows\r
116 // the alternative next QTD point when a short read happens.\r
117 // For control transfer, even the short read happens, try the\r
118 // status stage.\r
119 //\r
120 EHC_QTD *ShortReadStop;\r
121 EFI_EVENT PollTimer;\r
122\r
123 //\r
124 // Asynchronous(bulk and control) transfer schedule data:\r
125 // ReclaimHead is used as the head of the asynchronous transfer\r
126 // list. It acts as the reclamation header.\r
127 //\r
128 EHC_QH *ReclaimHead;\r
129\r
130 //\r
131 // Peroidic (interrupt) transfer schedule data:\r
132 //\r
133 VOID *PeriodFrame; // Mapped as common buffer\r
134 VOID *PeriodFrameHost;\r
135 VOID *PeriodFrameMap;\r
136\r
137 EHC_QH *PeriodOne;\r
138 LIST_ENTRY AsyncIntTransfers;\r
139\r
140 //\r
141 // EHCI configuration data\r
142 //\r
143 UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r
144 UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r
145 UINT32 CapLen; // Capability length\r
146 UINT32 High32bitAddr;\r
147\r
148 //\r
149 // Misc\r
150 //\r
151 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
c52fa98c 152};\r
913cb9dc 153\r
154\r
f527bce3 155extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
156extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
157extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;\r
913cb9dc 158\r
159#endif\r