[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h

/** @file\r
\r
  This file contains the definination for host controller register operation routines.\r
\r
Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
//\r
// EHCI register offset\r
//\r
\r
\r
//\r
// Capability register offset\r
//\r
#define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset\r
#define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h\r
#define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset\r
\r
//\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS             0x0F // Number of root hub port\r
#define HCSP_PPC                0x10 // Port Power Control\r
#define HCCP_64BIT              0x01 // 64-bit addressing capability\r
\r
//\r
// Operational register offset\r
//\r
#define EHC_USBCMD_OFFSET       0x0  // USB command register offset\r
#define EHC_USBSTS_OFFSET       0x04 // Statue register offset\r
#define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset\r
#define EHC_FRINDEX_OFFSET      0x0C // Frame index offset\r
#define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset\r
#define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset\r
#define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset\r
#define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset\r
#define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset\r
\r
#define EHC_FRAME_LEN           1024\r
\r
//\r
// Register bit definition\r
//\r
#define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC\r
\r
#define USBCMD_RUN              0x01   // Run/stop\r
#define USBCMD_RESET            0x02   // Start the host controller reset\r
#define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule\r
#define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule\r
#define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell\r
\r
#define USBSTS_IAA              0x20   // Interrupt on async advance\r
#define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status\r
#define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status\r
#define USBSTS_HALT             0x1000 // Host controller halted\r
#define USBSTS_SYS_ERROR        0x10   // Host system error\r
#define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC\r
                                       // (write clean) bits in USBSTS register\r
\r
#define PORTSC_CONN             0x01   // Current Connect Status\r
#define PORTSC_CONN_CHANGE      0x02   // Connect Status Change\r
#define PORTSC_ENABLED          0x04   // Port Enable / Disable\r
#define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change\r
#define PORTSC_OVERCUR          0x10   // Over current Active\r
#define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change\r
#define PORSTSC_RESUME          0x40   // Force Port Resume\r
#define PORTSC_SUSPEND          0x80   // Port Suspend State\r
#define PORTSC_RESET            0x100  // Port Reset\r
#define PORTSC_LINESTATE_K      0x400  // Line Status K-state\r
#define PORTSC_LINESTATE_J      0x800  // Line Status J-state\r
#define PORTSC_POWER            0x1000 // Port Power\r
#define PORTSC_OWNER            0x2000 // Port Owner\r
#define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,\r
                                       // they are WC (write clean)\r
//\r
// PCI Configuration Registers\r
//\r
#define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10\r
\r
//\r
// Debug port capability id\r
//\r
#define EHC_DEBUG_PORT_CAP_ID   0x0A\r
\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32)   \\r
        ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT16                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Ehci Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   ProgInterface;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc     The EHCI device.\r
  @param  Offset  Capability register address.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Check whether the host controller has an in-use debug port.\r
\r
  @param[in] Ehc         The Enhanced Host Controller to query.\r
\r
  @param[in] PortNumber  If PortNumber is not NULL, then query whether\r
                         PortNumber is an in-use debug port on Ehc. (PortNumber\r
                         is taken in UEFI notation, i.e., zero-based.)\r
                         Otherwise, query whether Ehc has any in-use debug\r
                         port.\r
\r
  @retval TRUE   PortNumber is an in-use debug port on Ehc (if PortNumber is\r
                 not NULL), or some port on Ehc is an in-use debug port\r
                 (otherwise).\r
\r
  @retval FALSE  PortNumber is not an in-use debug port on Ehc (if PortNumber\r
                 is not NULL), or no port on Ehc is an in-use debug port\r
                 (otherwise).\r
**/\r
BOOLEAN\r
EhcIsDebugPortInUse (\r
  IN CONST USB2_HC_DEV *Ehc,\r
  IN CONST UINT8       *PortNumber OPTIONAL\r
  );\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   The operation register offset.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   EHCI operation register offset.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
EhcSetOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
EhcClearOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits are Write-Clean.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV         *Ehc\r
  );\r
\r
\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc     The EHCI device.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is halt.\r
  @return EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV         *Ehc,\r
  IN UINT32              Timeout\r
  );\r
\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
#endif\r
Commit	Line	Data
913cb9dc	1	/** @file\r
913cb9dc	2	\r
78c2ffb5	3	This file contains the definination for host controller register operation routines.\r
78c2ffb5	4	\r
09943f5e	5	Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
9d510e61	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
913cb9dc	7	\r
913cb9dc	8	**/\r
	9	\r
	10	#ifndef _EFI_EHCI_REG_H_\r
	11	#define _EFI_EHCI_REG_H_\r
	12	\r
1ccdbf2a	13	//\r
	14	// EHCI register offset\r
	15	//\r
	16	\r
	17	\r
	18	//\r
	19	// Capability register offset\r
	20	//\r
	21	#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
	22	#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
	23	#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
	24	\r
	25	//\r
	26	// Capability register bit definition\r
	27	//\r
	28	#define HCSP_NPORTS 0x0F // Number of root hub port\r
f01219e8	29	#define HCSP_PPC 0x10 // Port Power Control\r
1ccdbf2a	30	#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
	31	\r
	32	//\r
	33	// Operational register offset\r
	34	//\r
	35	#define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r
	36	#define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r
	37	#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r
	38	#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r
	39	#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r
	40	#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r
	41	#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r
	42	#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r
	43	#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r
	44	\r
	45	#define EHC_FRAME_LEN 1024\r
913cb9dc	46	\r
1ccdbf2a	47	//\r
	48	// Register bit definition\r
	49	//\r
	50	#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
	51	\r
	52	#define USBCMD_RUN 0x01 // Run/stop\r
	53	#define USBCMD_RESET 0x02 // Start the host controller reset\r
	54	#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
	55	#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
	56	#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
	57	\r
	58	#define USBSTS_IAA 0x20 // Interrupt on async advance\r
	59	#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
	60	#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
	61	#define USBSTS_HALT 0x1000 // Host controller halted\r
	62	#define USBSTS_SYS_ERROR 0x10 // Host system error\r
	63	#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
	64	// (write clean) bits in USBSTS register\r
	65	\r
	66	#define PORTSC_CONN 0x01 // Current Connect Status\r
	67	#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
	68	#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
	69	#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
	70	#define PORTSC_OVERCUR 0x10 // Over current Active\r
	71	#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
	72	#define PORSTSC_RESUME 0x40 // Force Port Resume\r
	73	#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
	74	#define PORTSC_RESET 0x100 // Port Reset\r
	75	#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
	76	#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
	77	#define PORTSC_POWER 0x1000 // Port Power\r
	78	#define PORTSC_OWNER 0x2000 // Port Owner\r
	79	#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
	80	// they are WC (write clean)\r
	81	//\r
	82	// PCI Configuration Registers\r
	83	//\r
	84	#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
913cb9dc	85	\r
09943f5e	86	//\r
	87	// Debug port capability id\r
	88	//\r
	89	#define EHC_DEBUG_PORT_CAP_ID 0x0A\r
	90	\r
913cb9dc	91	#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
	92	\r
	93	#define EHC_ADDR(High, QhHw32) \\r
	94	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))\r
	95	\r
	96	#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
	97	\r
	98	//\r
	99	// Structure to map the hardware port states to the\r
	100	// UEFI's port states.\r
	101	//\r
	102	typedef struct {\r
	103	UINT16 HwState;\r
	104	UINT16 UefiState;\r
	105	} USB_PORT_STATE_MAP;\r
	106	\r
	107	//\r
	108	// Ehci Data and Ctrl Structures\r
	109	//\r
	110	#pragma pack(1)\r
	111	typedef struct {\r
1ccdbf2a	112	UINT8 ProgInterface;\r
913cb9dc	113	UINT8 SubClassCode;\r
	114	UINT8 BaseCode;\r
	115	} USB_CLASSC;\r
	116	#pragma pack()\r
	117	\r
78c2ffb5	118	/**\r
	119	Read EHCI capability register.\r
	120	\r
	121	@param Ehc The EHCI device.\r
	122	@param Offset Capability register address.\r
	123	\r
	124	@return The register content.\r
913cb9dc	125	\r
78c2ffb5	126	**/\r
913cb9dc	127	UINT32\r
	128	EhcReadCapRegister (\r
	129	IN USB2_HC_DEV *Ehc,\r
	130	IN UINT32 Offset\r
ed66e1bc	131	);\r
913cb9dc	132	\r
09943f5e	133	/**\r
b48ec0e8	134	Check whether the host controller has an in-use debug port.\r
09943f5e	135	\r
b48ec0e8	136	@param[in] Ehc The Enhanced Host Controller to query.\r
09943f5e	137	\r
b48ec0e8 LE	138	@param[in] PortNumber If PortNumber is not NULL, then query whether\r
	139	PortNumber is an in-use debug port on Ehc. (PortNumber\r
	140	is taken in UEFI notation, i.e., zero-based.)\r
	141	Otherwise, query whether Ehc has any in-use debug\r
	142	port.\r
09943f5e	143	\r
b48ec0e8 LE	144	@retval TRUE PortNumber is an in-use debug port on Ehc (if PortNumber is\r
	145	not NULL), or some port on Ehc is an in-use debug port\r
	146	(otherwise).\r
	147	\r
	148	@retval FALSE PortNumber is not an in-use debug port on Ehc (if PortNumber\r
	149	is not NULL), or no port on Ehc is an in-use debug port\r
	150	(otherwise).\r
09943f5e	151	**/\r
b48ec0e8 LE	152	BOOLEAN\r
	153	EhcIsDebugPortInUse (\r
	154	IN CONST USB2_HC_DEV *Ehc,\r
	155	IN CONST UINT8 *PortNumber OPTIONAL\r
09943f5e	156	);\r
913cb9dc	157	\r
913cb9dc	158	/**\r
78c2ffb5	159	Read EHCI Operation register.\r
913cb9dc	160	\r
78c2ffb5	161	@param Ehc The EHCI device.\r
78c2ffb5	162	@param Offset The operation register offset.\r
913cb9dc	163	\r
78c2ffb5	164	@return The register content.\r
913cb9dc	165	\r
	166	**/\r
	167	UINT32\r
	168	EhcReadOpReg (\r
	169	IN USB2_HC_DEV *Ehc,\r
	170	IN UINT32 Offset\r
ed66e1bc	171	);\r
913cb9dc	172	\r
	173	\r
	174	/**\r
78c2ffb5	175	Write the data to the EHCI operation register.\r
913cb9dc	176	\r
78c2ffb5	177	@param Ehc The EHCI device.\r
	178	@param Offset EHCI operation register offset.\r
	179	@param Data The data to write.\r
913cb9dc	180	\r
913cb9dc	181	**/\r
	182	VOID\r
	183	EhcWriteOpReg (\r
	184	IN USB2_HC_DEV *Ehc,\r
	185	IN UINT32 Offset,\r
	186	IN UINT32 Data\r
ed66e1bc	187	);\r
913cb9dc	188	\r
efe9186f	189	/**\r
	190	Set one bit of the operational register while keeping other bits.\r
	191	\r
	192	@param Ehc The EHCI device.\r
	193	@param Offset The offset of the operational register.\r
	194	@param Bit The bit mask of the register to set.\r
	195	\r
	196	**/\r
	197	VOID\r
	198	EhcSetOpRegBit (\r
	199	IN USB2_HC_DEV *Ehc,\r
	200	IN UINT32 Offset,\r
	201	IN UINT32 Bit\r
	202	);\r
	203	\r
	204	/**\r
	205	Clear one bit of the operational register while keeping other bits.\r
	206	\r
	207	@param Ehc The EHCI device.\r
	208	@param Offset The offset of the operational register.\r
	209	@param Bit The bit mask of the register to clear.\r
	210	\r
	211	**/\r
	212	VOID\r
	213	EhcClearOpRegBit (\r
	214	IN USB2_HC_DEV *Ehc,\r
	215	IN UINT32 Offset,\r
	216	IN UINT32 Bit\r
	217	);\r
913cb9dc	218	\r
	219	/**\r
	220	Add support for UEFI Over Legacy (UoL) feature, stop\r
78c2ffb5	221	the legacy USB SMI support.\r
913cb9dc	222	\r
	223	@param Ehc The EHCI device.\r
	224	\r
913cb9dc	225	**/\r
	226	VOID\r
	227	EhcClearLegacySupport (\r
	228	IN USB2_HC_DEV *Ehc\r
ed66e1bc	229	);\r
913cb9dc	230	\r
	231	\r
	232	\r
	233	/**\r
	234	Set door bell and wait it to be ACKed by host controller.\r
	235	This function is used to synchronize with the hardware.\r
	236	\r
78c2ffb5	237	@param Ehc The EHCI device.\r
78c2ffb5	238	@param Timeout The time to wait before abort (in millisecond, ms).\r
913cb9dc	239	\r
78c2ffb5	240	@retval EFI_SUCCESS Synchronized with the hardware.\r
78c2ffb5	241	@retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
913cb9dc	242	\r
	243	**/\r
	244	EFI_STATUS\r
	245	EhcSetAndWaitDoorBell (\r
	246	IN USB2_HC_DEV *Ehc,\r
	247	IN UINT32 Timeout\r
ed66e1bc	248	);\r
913cb9dc	249	\r
	250	\r
	251	/**\r
78c2ffb5	252	Clear all the interrutp status bits, these bits are Write-Clean.\r
913cb9dc	253	\r
78c2ffb5	254	@param Ehc The EHCI device.\r
913cb9dc	255	\r
913cb9dc	256	**/\r
	257	VOID\r
	258	EhcAckAllInterrupt (\r
	259	IN USB2_HC_DEV *Ehc\r
ed66e1bc	260	);\r
913cb9dc	261	\r
	262	\r
	263	\r
	264	/**\r
78c2ffb5	265	Whether Ehc is halted.\r
913cb9dc	266	\r
78c2ffb5	267	@param Ehc The EHCI device.\r
913cb9dc	268	\r
78c2ffb5	269	@retval TRUE The controller is halted.\r
78c2ffb5	270	@retval FALSE It isn't halted.\r
913cb9dc	271	\r
	272	**/\r
	273	BOOLEAN\r
	274	EhcIsHalt (\r
	275	IN USB2_HC_DEV *Ehc\r
ed66e1bc	276	);\r
913cb9dc	277	\r
	278	\r
	279	/**\r
78c2ffb5	280	Whether system error occurred.\r
913cb9dc	281	\r
78c2ffb5	282	@param Ehc The EHCI device.\r
913cb9dc	283	\r
78c2ffb5	284	@retval TRUE System error happened.\r
78c2ffb5	285	@retval FALSE No system error.\r
913cb9dc	286	\r
	287	**/\r
	288	BOOLEAN\r
	289	EhcIsSysError (\r
	290	IN USB2_HC_DEV *Ehc\r
ed66e1bc	291	);\r
913cb9dc	292	\r
913cb9dc	293	\r
913cb9dc	294	/**\r
78c2ffb5	295	Reset the host controller.\r
913cb9dc	296	\r
78c2ffb5	297	@param Ehc The EHCI device.\r
78c2ffb5	298	@param Timeout Time to wait before abort (in millisecond, ms).\r
913cb9dc	299	\r
78c2ffb5	300	@retval EFI_SUCCESS The host controller is reset.\r
78c2ffb5	301	@return Others Failed to reset the host.\r
913cb9dc	302	\r
	303	**/\r
	304	EFI_STATUS\r
	305	EhcResetHC (\r
	306	IN USB2_HC_DEV *Ehc,\r
	307	IN UINT32 Timeout\r
ed66e1bc	308	);\r
913cb9dc	309	\r
913cb9dc	310	\r
913cb9dc	311	/**\r
78c2ffb5	312	Halt the host controller.\r
913cb9dc	313	\r
78c2ffb5	314	@param Ehc The EHCI device.\r
78c2ffb5	315	@param Timeout Time to wait before abort.\r
913cb9dc	316	\r
78c2ffb5	317	@return EFI_SUCCESS The EHCI is halt.\r
78c2ffb5	318	@return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
913cb9dc	319	\r
	320	**/\r
	321	EFI_STATUS\r
	322	EhcHaltHC (\r
	323	IN USB2_HC_DEV *Ehc,\r
	324	IN UINT32 Timeout\r
ed66e1bc	325	);\r
913cb9dc	326	\r
913cb9dc	327	\r
913cb9dc	328	/**\r
78c2ffb5	329	Set the EHCI to run.\r
913cb9dc	330	\r
78c2ffb5	331	@param Ehc The EHCI device.\r
78c2ffb5	332	@param Timeout Time to wait before abort.\r
913cb9dc	333	\r
78c2ffb5	334	@return EFI_SUCCESS The EHCI is running.\r
78c2ffb5	335	@return Others Failed to set the EHCI to run.\r
913cb9dc	336	\r
	337	**/\r
	338	EFI_STATUS\r
	339	EhcRunHC (\r
	340	IN USB2_HC_DEV *Ehc,\r
	341	IN UINT32 Timeout\r
ed66e1bc	342	);\r
913cb9dc	343	\r
	344	\r
	345	\r
	346	/**\r
	347	Initialize the HC hardware.\r
78c2ffb5	348	EHCI spec lists the five things to do to initialize the hardware:\r
913cb9dc	349	1. Program CTRLDSSEGMENT\r
	350	2. Set USBINTR to enable interrupts\r
	351	3. Set periodic list base\r
	352	4. Set USBCMD, interrupt threshold, frame list size etc\r
	353	5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
	354	\r
78c2ffb5	355	@param Ehc The EHCI device.\r
913cb9dc	356	\r
78c2ffb5	357	@return EFI_SUCCESS The EHCI has come out of halt state.\r
78c2ffb5	358	@return EFI_TIMEOUT Time out happened.\r
913cb9dc	359	\r
	360	**/\r
	361	EFI_STATUS\r
	362	EhcInitHC (\r
	363	IN USB2_HC_DEV *Ehc\r
ed66e1bc	364	);\r
913cb9dc	365	\r
913cb9dc	366	#endif\r