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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciUrb.h
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913cb9dc 1/** @file\r
2\r
78c2ffb5 3 This file contains URB request, each request is warpped in a\r
4 URB (Usb Request Block).\r
5\r
f87db256 6Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
9d510e61 7SPDX-License-Identifier: BSD-2-Clause-Patent\r
913cb9dc 8\r
913cb9dc 9**/\r
10\r
11#ifndef _EFI_EHCI_URB_H_\r
12#define _EFI_EHCI_URB_H_\r
13\r
913cb9dc 14typedef struct _EHC_QTD EHC_QTD;\r
15typedef struct _EHC_QH EHC_QH;\r
16typedef struct _URB URB;\r
17\r
1ccdbf2a 18//\r
19// Transfer types, used in URB to identify the transfer type\r
20//\r
21#define EHC_CTRL_TRANSFER 0x01\r
22#define EHC_BULK_TRANSFER 0x02\r
23#define EHC_INT_TRANSFER_SYNC 0x04\r
24#define EHC_INT_TRANSFER_ASYNC 0x08\r
913cb9dc 25\r
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26#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')\r
27#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')\r
28#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
913cb9dc 29\r
1ccdbf2a 30//\r
31// Hardware related bit definitions\r
32//\r
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33#define EHC_TYPE_ITD 0x00\r
34#define EHC_TYPE_QH 0x02\r
35#define EHC_TYPE_SITD 0x04\r
36#define EHC_TYPE_FSTN 0x06\r
37\r
38#define QH_NAK_RELOAD 3\r
39#define QH_HSHBW_MULTI 1\r
40\r
41#define QTD_MAX_ERR 3\r
42#define QTD_PID_OUTPUT 0x00\r
43#define QTD_PID_INPUT 0x01\r
44#define QTD_PID_SETUP 0x02\r
45\r
46#define QTD_STAT_DO_OUT 0\r
47#define QTD_STAT_DO_SS 0\r
48#define QTD_STAT_DO_PING 0x01\r
49#define QTD_STAT_DO_CS 0x02\r
50#define QTD_STAT_TRANS_ERR 0x08\r
51#define QTD_STAT_BABBLE_ERR 0x10\r
52#define QTD_STAT_BUFF_ERR 0x20\r
53#define QTD_STAT_HALTED 0x40\r
54#define QTD_STAT_ACTIVE 0x80\r
55#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)\r
56\r
57#define QTD_MAX_BUFFER 4\r
58#define QTD_BUF_LEN 4096\r
59#define QTD_BUF_MASK 0x0FFF\r
60\r
61#define QH_MICROFRAME_0 0x01\r
62#define QH_MICROFRAME_1 0x02\r
63#define QH_MICROFRAME_2 0x04\r
64#define QH_MICROFRAME_3 0x08\r
65#define QH_MICROFRAME_4 0x10\r
66#define QH_MICROFRAME_5 0x20\r
67#define QH_MICROFRAME_6 0x40\r
68#define QH_MICROFRAME_7 0x80\r
69\r
70#define USB_ERR_SHORT_PACKET 0x200\r
913cb9dc 71\r
72//\r
73// Fill in the hardware link point: pass in a EHC_QH/QH_HW\r
74// pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK\r
75//\r
76#define QH_LINK(Addr, Type, Term) \\r
77 ((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))\r
78\r
1436aea4 79#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))\r
913cb9dc 80\r
81//\r
82// The defination of EHCI hardware used data structure for\r
83// little endian architecture. The QTD and QH structures\r
84// are required to be 32 bytes aligned. Don't add members\r
85// to the head of the associated software strucuture.\r
86//\r
87#pragma pack(1)\r
88typedef struct {\r
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89 UINT32 NextQtd;\r
90 UINT32 AltNext;\r
91\r
92 UINT32 Status : 8;\r
93 UINT32 Pid : 2;\r
94 UINT32 ErrCnt : 2;\r
95 UINT32 CurPage : 3;\r
96 UINT32 Ioc : 1;\r
97 UINT32 TotalBytes : 15;\r
98 UINT32 DataToggle : 1;\r
99\r
100 UINT32 Page[5];\r
101 UINT32 PageHigh[5];\r
913cb9dc 102} QTD_HW;\r
103\r
104typedef struct {\r
1436aea4 105 UINT32 HorizonLink;\r
913cb9dc 106 //\r
107 // Endpoint capabilities/Characteristics DWord 1 and DWord 2\r
108 //\r
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109 UINT32 DeviceAddr : 7;\r
110 UINT32 Inactive : 1;\r
111 UINT32 EpNum : 4;\r
112 UINT32 EpSpeed : 2;\r
113 UINT32 DtCtrl : 1;\r
114 UINT32 ReclaimHead : 1;\r
115 UINT32 MaxPacketLen : 11;\r
116 UINT32 CtrlEp : 1;\r
117 UINT32 NakReload : 4;\r
118\r
119 UINT32 SMask : 8;\r
120 UINT32 CMask : 8;\r
121 UINT32 HubAddr : 7;\r
122 UINT32 PortNum : 7;\r
123 UINT32 Multiplier : 2;\r
913cb9dc 124\r
125 //\r
126 // Transaction execution overlay area\r
127 //\r
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128 UINT32 CurQtd;\r
129 UINT32 NextQtd;\r
130 UINT32 AltQtd;\r
131\r
132 UINT32 Status : 8;\r
133 UINT32 Pid : 2;\r
134 UINT32 ErrCnt : 2;\r
135 UINT32 CurPage : 3;\r
136 UINT32 Ioc : 1;\r
137 UINT32 TotalBytes : 15;\r
138 UINT32 DataToggle : 1;\r
139\r
140 UINT32 Page[5];\r
141 UINT32 PageHigh[5];\r
913cb9dc 142} QH_HW;\r
143#pragma pack()\r
144\r
913cb9dc 145//\r
146// Endpoint address and its capabilities\r
147//\r
148typedef struct _USB_ENDPOINT {\r
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149 UINT8 DevAddr;\r
150 UINT8 EpAddr; // Endpoint address, no direction encoded in\r
151 EFI_USB_DATA_DIRECTION Direction;\r
152 UINT8 DevSpeed;\r
153 UINTN MaxPacket;\r
154 UINT8 HubAddr;\r
155 UINT8 HubPort;\r
156 UINT8 Toggle; // Data toggle, not used for control transfer\r
157 UINTN Type;\r
158 UINTN PollRate; // Polling interval used by EHCI\r
913cb9dc 159} USB_ENDPOINT;\r
160\r
161//\r
162// Software QTD strcture, this is used to manage all the\r
163// QTD generated from a URB. Don't add fields before QtdHw.\r
164//\r
c52fa98c 165struct _EHC_QTD {\r
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166 QTD_HW QtdHw;\r
167 UINT32 Signature;\r
168 LIST_ENTRY QtdList; // The list of QTDs to one end point\r
169 UINT8 *Data; // Buffer of the original data\r
170 UINTN DataLen; // Original amount of data in this QTD\r
c52fa98c 171};\r
913cb9dc 172\r
173//\r
174// Software QH structure. All three different transaction types\r
175// supported by UEFI USB, that is the control/bulk/interrupt\r
176// transfers use the queue head and queue token strcuture.\r
177//\r
178// Interrupt QHs are linked to periodic frame list in the reversed\r
179// 2^N tree. Each interrupt QH is linked to the list starting at\r
180// frame 0. There is a dummy interrupt QH linked to each frame as\r
181// a sentinental whose polling interval is 1. Synchronous interrupt\r
182// transfer is linked after this dummy QH.\r
183//\r
184// For control/bulk transfer, only synchronous (in the sense of UEFI)\r
185// transfer is supported. A dummy QH is linked to EHCI AsyncListAddr\r
186// as the reclamation header. New transfer is inserted after this QH.\r
187//\r
c52fa98c 188struct _EHC_QH {\r
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189 QH_HW QhHw;\r
190 UINT32 Signature;\r
191 EHC_QH *NextQh; // The queue head pointed to by horizontal link\r
192 LIST_ENTRY Qtds; // The list of QTDs to this queue head\r
193 UINTN Interval;\r
c52fa98c 194};\r
913cb9dc 195\r
196//\r
197// URB (Usb Request Block) contains information for all kinds of\r
198// usb requests.\r
199//\r
c52fa98c 200struct _URB {\r
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201 UINT32 Signature;\r
202 LIST_ENTRY UrbList;\r
913cb9dc 203\r
204 //\r
205 // Transaction information\r
206 //\r
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207 USB_ENDPOINT Ep;\r
208 EFI_USB_DEVICE_REQUEST *Request; // Control transfer only\r
209 VOID *RequestPhy; // Address of the mapped request\r
210 VOID *RequestMap;\r
211 VOID *Data;\r
212 UINTN DataLen;\r
213 VOID *DataPhy; // Address of the mapped user data\r
214 VOID *DataMap;\r
215 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
216 VOID *Context;\r
913cb9dc 217\r
218 //\r
219 // Schedule data\r
220 //\r
1436aea4 221 EHC_QH *Qh;\r
913cb9dc 222\r
223 //\r
224 // Transaction result\r
225 //\r
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226 UINT32 Result;\r
227 UINTN Completed; // completed data length\r
228 UINT8 DataToggle;\r
c52fa98c 229};\r
913cb9dc 230\r
913cb9dc 231/**\r
78c2ffb5 232 Create a single QTD to hold the data.\r
913cb9dc 233\r
78c2ffb5 234 @param Ehc The EHCI device.\r
739802e4 235 @param Data The cpu memory address of current data not associated with a QTD.\r
236 @param DataPhy The pci bus address of current data not associated with a QTD.\r
78c2ffb5 237 @param DataLen The length of the data.\r
238 @param PktId Packet ID to use in the QTD.\r
239 @param Toggle Data toggle to use in the QTD.\r
240 @param MaxPacket Maximu packet length of the endpoint.\r
913cb9dc 241\r
78c2ffb5 242 @return Created QTD or NULL if failed to create one.\r
913cb9dc 243\r
244**/\r
245EHC_QTD *\r
246EhcCreateQtd (\r
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247 IN USB2_HC_DEV *Ehc,\r
248 IN UINT8 *Data,\r
249 IN UINT8 *DataPhy,\r
250 IN UINTN DataLen,\r
251 IN UINT8 PktId,\r
252 IN UINT8 Toggle,\r
253 IN UINTN MaxPacket\r
ed66e1bc 254 );\r
913cb9dc 255\r
913cb9dc 256/**\r
78c2ffb5 257 Allocate and initialize a EHCI queue head.\r
913cb9dc 258\r
78c2ffb5 259 @param Ehci The EHCI device.\r
260 @param Ep The endpoint to create queue head for.\r
913cb9dc 261\r
78c2ffb5 262 @return Created queue head or NULL if failed to create one.\r
913cb9dc 263\r
264**/\r
265EHC_QH *\r
266EhcCreateQh (\r
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267 IN USB2_HC_DEV *Ehci,\r
268 IN USB_ENDPOINT *Ep\r
ed66e1bc 269 );\r
913cb9dc 270\r
913cb9dc 271/**\r
272 Free an allocated URB. It is possible for it to be partially inited.\r
273\r
78c2ffb5 274 @param Ehc The EHCI device.\r
275 @param Urb The URB to free.\r
913cb9dc 276\r
913cb9dc 277**/\r
278VOID\r
279EhcFreeUrb (\r
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280 IN USB2_HC_DEV *Ehc,\r
281 IN URB *Urb\r
ed66e1bc 282 );\r
913cb9dc 283\r
913cb9dc 284/**\r
78c2ffb5 285 Create a new URB and its associated QTD.\r
286\r
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287 @param Ehc The EHCI device.\r
288 @param DevAddr The device address.\r
289 @param EpAddr Endpoint addrress & its direction.\r
290 @param DevSpeed The device speed.\r
291 @param Toggle Initial data toggle to use.\r
292 @param MaxPacket The max packet length of the endpoint.\r
293 @param Hub The transaction translator to use.\r
294 @param Type The transaction type.\r
295 @param Request The standard USB request for control transfer.\r
296 @param Data The user data to transfer.\r
297 @param DataLen The length of data buffer.\r
298 @param Callback The function to call when data is transferred.\r
299 @param Context The context to the callback.\r
300 @param Interval The interval for interrupt transfer.\r
78c2ffb5 301\r
302 @return Created URB or NULL.\r
913cb9dc 303\r
304**/\r
305URB *\r
306EhcCreateUrb (\r
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307 IN USB2_HC_DEV *Ehc,\r
308 IN UINT8 DevAddr,\r
309 IN UINT8 EpAddr,\r
310 IN UINT8 DevSpeed,\r
311 IN UINT8 Toggle,\r
312 IN UINTN MaxPacket,\r
313 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r
314 IN UINTN Type,\r
315 IN EFI_USB_DEVICE_REQUEST *Request,\r
316 IN VOID *Data,\r
317 IN UINTN DataLen,\r
318 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
319 IN VOID *Context,\r
320 IN UINTN Interval\r
ed66e1bc 321 );\r
1436aea4 322\r
913cb9dc 323#endif\r