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4b1bf81c | 1 | /** @file\r |
2 | Private Header file for Usb Host Controller PEIM\r | |
3 | \r | |
d1102dba LG |
4 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
5 | \r | |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4b1bf81c | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef _RECOVERY_EHC_H_\r | |
11 | #define _RECOVERY_EHC_H_\r | |
12 | \r | |
13 | #include <PiPei.h>\r | |
14 | \r | |
15 | #include <Ppi/UsbController.h>\r | |
16 | #include <Ppi/Usb2HostController.h>\r | |
2c656af0 SZ |
17 | #include <Ppi/IoMmu.h>\r |
18 | #include <Ppi/EndOfPeiPhase.h>\r | |
4b1bf81c | 19 | \r |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/PeimEntryPoint.h>\r | |
22 | #include <Library/PeiServicesLib.h>\r | |
23 | #include <Library/BaseMemoryLib.h>\r | |
24 | #include <Library/TimerLib.h>\r | |
25 | #include <Library/IoLib.h>\r | |
26 | \r | |
27 | typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;\r | |
28 | \r | |
29 | #define EFI_LIST_ENTRY LIST_ENTRY\r | |
30 | \r | |
31 | #include "UsbHcMem.h"\r | |
32 | #include "EhciReg.h"\r | |
33 | #include "EhciUrb.h"\r | |
34 | #include "EhciSched.h"\r | |
35 | \r | |
36 | #define EFI_USB_SPEED_FULL 0x0000\r | |
37 | #define EFI_USB_SPEED_LOW 0x0001\r | |
38 | #define EFI_USB_SPEED_HIGH 0x0002\r | |
39 | \r | |
40 | #define PAGESIZE 4096\r | |
41 | \r | |
42 | #define EHC_1_MICROSECOND 1\r | |
43 | #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r | |
44 | #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r | |
45 | \r | |
46 | //\r | |
47 | // EHCI register operation timeout, set by experience\r | |
48 | //\r | |
49 | #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r | |
50 | #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r | |
51 | \r | |
52 | \r | |
53 | //\r | |
54 | // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r | |
55 | //\r | |
56 | #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r | |
57 | \r | |
58 | //\r | |
bfe37a77 | 59 | // Sync transfer polling interval, set by experience.\r |
4b1bf81c | 60 | //\r |
61 | #define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)\r | |
62 | \r | |
4b1bf81c | 63 | //\r |
ed356b9e | 64 | //Iterate through the double linked list. NOT delete safe\r |
4b1bf81c | 65 | //\r |
66 | #define EFI_LIST_FOR_EACH(Entry, ListHead) \\r | |
67 | for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)\r | |
68 | \r | |
69 | //\r | |
ed356b9e | 70 | //Iterate through the double linked list. This is delete-safe.\r |
4b1bf81c | 71 | //Don't touch NextEntry\r |
72 | //\r | |
73 | #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \\r | |
74 | for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\\r | |
75 | Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)\r | |
76 | \r | |
77 | #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r | |
78 | \r | |
79 | \r | |
80 | #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r | |
81 | #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r | |
82 | #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r | |
83 | \r | |
84 | #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r | |
85 | (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r | |
86 | \r | |
87 | #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')\r | |
88 | \r | |
89 | struct _PEI_USB2_HC_DEV {\r | |
90 | UINTN Signature;\r | |
91 | PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r | |
2c656af0 SZ |
92 | EDKII_IOMMU_PPI *IoMmu;\r |
93 | EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r | |
94 | //\r | |
c34a5aab | 95 | // EndOfPei callback is used to stop the EHC DMA operation\r |
2c656af0 SZ |
96 | // after exit PEI phase.\r |
97 | //\r | |
98 | EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r | |
4b1bf81c | 99 | UINT32 UsbHostControllerBaseAddress;\r |
100 | PEI_URB *Urb;\r | |
101 | USBHC_MEM_POOL *MemPool;\r | |
102 | \r | |
103 | //\r | |
104 | // Schedule data shared between asynchronous and periodic\r | |
105 | // transfers:\r | |
106 | // ShortReadStop, as its name indicates, is used to terminate\r | |
107 | // the short read except the control transfer. EHCI follows\r | |
108 | // the alternative next QTD point when a short read happens.\r | |
109 | // For control transfer, even the short read happens, try the\r | |
110 | // status stage.\r | |
111 | //\r | |
112 | PEI_EHC_QTD *ShortReadStop;\r | |
113 | EFI_EVENT PollTimer;\r | |
d1102dba | 114 | \r |
4b1bf81c | 115 | //\r |
d1102dba | 116 | // Asynchronous(bulk and control) transfer schedule data:\r |
4b1bf81c | 117 | // ReclaimHead is used as the head of the asynchronous transfer\r |
d1102dba | 118 | // list. It acts as the reclamation header.\r |
4b1bf81c | 119 | //\r |
120 | PEI_EHC_QH *ReclaimHead;\r | |
d1102dba | 121 | \r |
4b1bf81c | 122 | //\r |
ed356b9e | 123 | // Periodic (interrupt) transfer schedule data:\r |
4b1bf81c | 124 | //\r |
d1102dba | 125 | VOID *PeriodFrame; // Mapped as common buffer\r |
4b1bf81c | 126 | VOID *PeriodFrameMap;\r |
d1102dba | 127 | \r |
4b1bf81c | 128 | PEI_EHC_QH *PeriodOne;\r |
129 | EFI_LIST_ENTRY AsyncIntTransfers;\r | |
130 | \r | |
131 | //\r | |
132 | // EHCI configuration data\r | |
133 | //\r | |
134 | UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r | |
135 | UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r | |
136 | UINT32 CapLen; // Capability length\r | |
137 | UINT32 High32bitAddr;\r | |
138 | };\r | |
139 | \r | |
140 | #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)\r | |
2c656af0 | 141 | #define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)\r |
4b1bf81c | 142 | \r |
143 | /**\r | |
144 | @param EhcDev EHCI Device.\r | |
145 | \r | |
146 | @retval EFI_SUCCESS EHCI successfully initialized.\r | |
147 | @retval EFI_ABORTED EHCI was failed to be initialized.\r | |
148 | \r | |
149 | **/\r | |
150 | EFI_STATUS\r | |
151 | InitializeUsbHC (\r | |
d1102dba | 152 | IN PEI_USB2_HC_DEV *EhcDev\r |
4b1bf81c | 153 | );\r |
154 | \r | |
155 | /**\r | |
156 | Initialize the memory management pool for the host controller.\r | |
d1102dba | 157 | \r |
4b1bf81c | 158 | @param Ehc The EHCI device.\r |
d1102dba | 159 | @param Check4G Whether the host controller requires allocated memory\r |
4b1bf81c | 160 | from one 4G address space.\r |
161 | @param Which4G The 4G memory area each memory allocated should be from.\r | |
162 | \r | |
163 | @retval EFI_SUCCESS The memory pool is initialized.\r | |
164 | @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.\r | |
165 | \r | |
166 | **/\r | |
167 | USBHC_MEM_POOL *\r | |
168 | UsbHcInitMemPool (\r | |
169 | IN PEI_USB2_HC_DEV *Ehc,\r | |
170 | IN BOOLEAN Check4G,\r | |
171 | IN UINT32 Which4G\r | |
172 | )\r | |
173 | ;\r | |
d1102dba | 174 | \r |
4b1bf81c | 175 | /**\r |
176 | Release the memory management pool.\r | |
2c656af0 SZ |
177 | \r |
178 | @param Ehc The EHCI device.\r | |
4b1bf81c | 179 | @param Pool The USB memory pool to free.\r |
180 | \r | |
181 | @retval EFI_DEVICE_ERROR Fail to free the memory pool.\r | |
182 | @retval EFI_SUCCESS The memory pool is freed.\r | |
183 | \r | |
184 | **/\r | |
185 | EFI_STATUS\r | |
186 | UsbHcFreeMemPool (\r | |
2c656af0 | 187 | IN PEI_USB2_HC_DEV *Ehc,\r |
4b1bf81c | 188 | IN USBHC_MEM_POOL *Pool\r |
189 | )\r | |
190 | ;\r | |
191 | \r | |
192 | /**\r | |
193 | Allocate some memory from the host controller's memory pool\r | |
194 | which can be used to communicate with host controller.\r | |
d1102dba | 195 | \r |
4b1bf81c | 196 | @param Ehc The EHCI device.\r |
197 | @param Pool The host controller's memory pool.\r | |
198 | @param Size Size of the memory to allocate.\r | |
199 | \r | |
200 | @return The allocated memory or NULL.\r | |
201 | \r | |
202 | **/\r | |
203 | VOID *\r | |
204 | UsbHcAllocateMem (\r | |
205 | IN PEI_USB2_HC_DEV *Ehc,\r | |
206 | IN USBHC_MEM_POOL *Pool,\r | |
207 | IN UINTN Size\r | |
208 | )\r | |
209 | ;\r | |
210 | \r | |
211 | /**\r | |
212 | Free the allocated memory back to the memory pool.\r | |
213 | \r | |
2c656af0 | 214 | @param Ehc The EHCI device.\r |
4b1bf81c | 215 | @param Pool The memory pool of the host controller.\r |
216 | @param Mem The memory to free.\r | |
217 | @param Size The size of the memory to free.\r | |
218 | \r | |
219 | **/\r | |
220 | VOID\r | |
221 | UsbHcFreeMem (\r | |
2c656af0 | 222 | IN PEI_USB2_HC_DEV *Ehc,\r |
4b1bf81c | 223 | IN USBHC_MEM_POOL *Pool,\r |
224 | IN VOID *Mem,\r | |
225 | IN UINTN Size\r | |
226 | )\r | |
227 | ;\r | |
228 | \r | |
2c656af0 SZ |
229 | /**\r |
230 | Provides the controller-specific addresses required to access system memory from a\r | |
231 | DMA bus master.\r | |
232 | \r | |
233 | @param IoMmu Pointer to IOMMU PPI.\r | |
234 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
235 | @param HostAddress The system memory address to map to the PCI controller.\r | |
236 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
237 | that were mapped.\r | |
238 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
239 | access the hosts HostAddress.\r | |
240 | @param Mapping A resulting value to pass to Unmap().\r | |
241 | \r | |
242 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r | |
243 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
244 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
245 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
246 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
247 | \r | |
248 | **/\r | |
249 | EFI_STATUS\r | |
250 | IoMmuMap (\r | |
251 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
252 | IN EDKII_IOMMU_OPERATION Operation,\r | |
253 | IN VOID *HostAddress,\r | |
254 | IN OUT UINTN *NumberOfBytes,\r | |
255 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
256 | OUT VOID **Mapping\r | |
257 | );\r | |
258 | \r | |
259 | /**\r | |
260 | Completes the Map() operation and releases any corresponding resources.\r | |
261 | \r | |
262 | @param IoMmu Pointer to IOMMU PPI.\r | |
263 | @param Mapping The mapping value returned from Map().\r | |
264 | \r | |
265 | **/\r | |
266 | VOID\r | |
267 | IoMmuUnmap (\r | |
268 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
269 | IN VOID *Mapping\r | |
270 | );\r | |
271 | \r | |
272 | /**\r | |
273 | Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r | |
274 | OperationBusMasterCommonBuffer64 mapping.\r | |
275 | \r | |
276 | @param IoMmu Pointer to IOMMU PPI.\r | |
277 | @param Pages The number of pages to allocate.\r | |
278 | @param HostAddress A pointer to store the base system memory address of the\r | |
279 | allocated range.\r | |
280 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
281 | access the hosts HostAddress.\r | |
282 | @param Mapping A resulting value to pass to Unmap().\r | |
283 | \r | |
284 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
285 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
286 | MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r | |
287 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
288 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
289 | \r | |
290 | **/\r | |
291 | EFI_STATUS\r | |
292 | IoMmuAllocateBuffer (\r | |
293 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
294 | IN UINTN Pages,\r | |
295 | OUT VOID **HostAddress,\r | |
296 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
297 | OUT VOID **Mapping\r | |
298 | );\r | |
299 | \r | |
300 | /**\r | |
301 | Frees memory that was allocated with AllocateBuffer().\r | |
302 | \r | |
303 | @param IoMmu Pointer to IOMMU PPI.\r | |
304 | @param Pages The number of pages to free.\r | |
305 | @param HostAddress The base system memory address of the allocated range.\r | |
306 | @param Mapping The mapping value returned from Map().\r | |
307 | \r | |
308 | **/\r | |
309 | VOID\r | |
310 | IoMmuFreeBuffer (\r | |
311 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
312 | IN UINTN Pages,\r | |
313 | IN VOID *HostAddress,\r | |
314 | IN VOID *Mapping\r | |
315 | );\r | |
316 | \r | |
317 | /**\r | |
318 | Initialize IOMMU.\r | |
319 | \r | |
320 | @param IoMmu Pointer to pointer to IOMMU PPI.\r | |
321 | \r | |
322 | **/\r | |
323 | VOID\r | |
324 | IoMmuInit (\r | |
325 | OUT EDKII_IOMMU_PPI **IoMmu\r | |
326 | );\r | |
327 | \r | |
4b1bf81c | 328 | #endif\r |