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4b1bf81c | 1 | /** @file\r |
2 | Private Header file for Usb Host Controller PEIM\r | |
3 | \r | |
4 | Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions\r | |
8 | of the BSD License which accompanies this distribution. The\r | |
9 | full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #ifndef _EFI_EHCI_REG_H_\r | |
18 | #define _EFI_EHCI_REG_H_\r | |
19 | \r | |
20 | \r | |
21 | \r | |
22 | //\r | |
23 | // Capability register offset\r | |
24 | //\r | |
25 | #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r | |
26 | #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r | |
27 | #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r | |
28 | \r | |
29 | //\r | |
30 | // Capability register bit definition\r | |
31 | //\r | |
32 | #define HCSP_NPORTS 0x0F // Number of root hub port\r | |
33 | #define HCCP_64BIT 0x01 // 64-bit addressing capability\r | |
34 | \r | |
35 | //\r | |
36 | // Operational register offset\r | |
37 | //\r | |
38 | #define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r | |
39 | #define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r | |
40 | #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r | |
41 | #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r | |
42 | #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r | |
43 | #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r | |
44 | #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r | |
45 | #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r | |
46 | #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r | |
47 | \r | |
48 | #define EHC_FRAME_LEN 1024\r | |
49 | \r | |
50 | //\r | |
51 | // Register bit definition\r | |
52 | //\r | |
53 | #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r | |
54 | \r | |
55 | #define USBCMD_RUN 0x01 // Run/stop\r | |
56 | #define USBCMD_RESET 0x02 // Start the host controller reset\r | |
57 | #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r | |
58 | #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r | |
59 | #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r | |
60 | \r | |
61 | #define USBSTS_IAA 0x20 // Interrupt on async advance\r | |
62 | #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r | |
63 | #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r | |
64 | #define USBSTS_HALT 0x1000 // Host controller halted\r | |
65 | #define USBSTS_SYS_ERROR 0x10 // Host system error\r | |
66 | #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r | |
67 | // (write clean) bits in USBSTS register\r | |
68 | \r | |
69 | #define PORTSC_CONN 0x01 // Current Connect Status\r | |
70 | #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r | |
71 | #define PORTSC_ENABLED 0x04 // Port Enable / Disable\r | |
72 | #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r | |
73 | #define PORTSC_OVERCUR 0x10 // Over current Active\r | |
74 | #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r | |
75 | #define PORSTSC_RESUME 0x40 // Force Port Resume\r | |
76 | #define PORTSC_SUSPEND 0x80 // Port Suspend State\r | |
77 | #define PORTSC_RESET 0x100 // Port Reset\r | |
78 | #define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r | |
79 | #define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r | |
80 | #define PORTSC_POWER 0x1000 // Port Power\r | |
81 | #define PORTSC_OWNER 0x2000 // Port Owner\r | |
82 | #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r | |
83 | // they are WC (write clean)\r | |
84 | //\r | |
85 | // PCI Configuration Registers\r | |
86 | //\r | |
87 | #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r | |
88 | \r | |
89 | #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r | |
90 | \r | |
91 | #define EHC_ADDR(High, QhHw32) \\r | |
92 | ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r | |
93 | \r | |
94 | #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r | |
95 | \r | |
96 | //\r | |
97 | // Structure to map the hardware port states to the \r | |
98 | // UEFI's port states. \r | |
99 | //\r | |
100 | typedef struct {\r | |
101 | UINT16 HwState;\r | |
102 | UINT16 UefiState;\r | |
103 | } USB_PORT_STATE_MAP;\r | |
104 | \r | |
105 | //\r | |
106 | // Ehci Data and Ctrl Structures\r | |
107 | //\r | |
108 | #pragma pack(1)\r | |
109 | typedef struct {\r | |
110 | UINT8 Pi;\r | |
111 | UINT8 SubClassCode;\r | |
112 | UINT8 BaseCode;\r | |
113 | } USB_CLASSC;\r | |
114 | #pragma pack()\r | |
115 | \r | |
116 | \r | |
117 | /**\r | |
118 | Read EHCI capability register.\r | |
119 | \r | |
120 | @param Ehc The EHCI device.\r | |
121 | @param Offset Capability register address.\r | |
122 | \r | |
123 | @retval the register content read.\r | |
124 | \r | |
125 | **/\r | |
126 | UINT32\r | |
127 | EhcReadCapRegister (\r | |
128 | IN PEI_USB2_HC_DEV *Ehc,\r | |
129 | IN UINT32 Offset\r | |
130 | )\r | |
131 | ;\r | |
132 | \r | |
133 | /**\r | |
134 | Read Ehc Operation register.\r | |
135 | \r | |
136 | @param Ehc The EHCI device.\r | |
137 | @param Offset The operation register offset.\r | |
138 | \r | |
139 | @retval the register content read.\r | |
140 | \r | |
141 | **/\r | |
142 | UINT32\r | |
143 | EhcReadOpReg (\r | |
144 | IN PEI_USB2_HC_DEV *Ehc,\r | |
145 | IN UINT32 Offset\r | |
146 | )\r | |
147 | ;\r | |
148 | \r | |
149 | /**\r | |
150 | Write the data to the EHCI operation register.\r | |
151 | \r | |
152 | @param Ehc The EHCI device.\r | |
153 | @param Offset EHCI operation register offset.\r | |
154 | @param Data The data to write.\r | |
155 | \r | |
156 | **/\r | |
157 | VOID\r | |
158 | EhcWriteOpReg (\r | |
159 | IN PEI_USB2_HC_DEV *Ehc,\r | |
160 | IN UINT32 Offset,\r | |
161 | IN UINT32 Data\r | |
162 | )\r | |
163 | ;\r | |
164 | \r | |
165 | /**\r | |
166 | Stop the legacy USB SMI support.\r | |
167 | \r | |
168 | @param Ehc The EHCI device.\r | |
169 | \r | |
170 | **/\r | |
171 | VOID\r | |
172 | EhcClearLegacySupport (\r | |
173 | IN PEI_USB2_HC_DEV *Ehc\r | |
174 | )\r | |
175 | ;\r | |
176 | \r | |
177 | /**\r | |
178 | Set door bell and wait it to be ACKed by host controller.\r | |
179 | This function is used to synchronize with the hardware.\r | |
180 | \r | |
181 | @param Ehc The EHCI device.\r | |
182 | @param Timeout The time to wait before abort (in millisecond, ms).\r | |
183 | \r | |
184 | @retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r | |
185 | @retval EFI_SUCCESS Synchronized with the hardware.\r | |
186 | \r | |
187 | **/\r | |
188 | EFI_STATUS\r | |
189 | EhcSetAndWaitDoorBell (\r | |
190 | IN PEI_USB2_HC_DEV *Ehc,\r | |
191 | IN UINT32 Timeout\r | |
192 | )\r | |
193 | ;\r | |
194 | \r | |
195 | /**\r | |
196 | Clear all the interrutp status bits, these bits \r | |
197 | are Write-Clean.\r | |
198 | \r | |
199 | @param Ehc The EHCI device.\r | |
200 | \r | |
201 | **/\r | |
202 | VOID\r | |
203 | EhcAckAllInterrupt (\r | |
204 | IN PEI_USB2_HC_DEV *Ehc\r | |
205 | )\r | |
206 | ;\r | |
207 | \r | |
208 | /**\r | |
209 | Check whether Ehc is halted.\r | |
210 | \r | |
211 | @param Ehc The EHCI device.\r | |
212 | \r | |
213 | @retval TRUE The controller is halted.\r | |
214 | @retval FALSE The controller isn't halted.\r | |
215 | \r | |
216 | **/\r | |
217 | BOOLEAN\r | |
218 | EhcIsHalt (\r | |
219 | IN PEI_USB2_HC_DEV *Ehc\r | |
220 | )\r | |
221 | ;\r | |
222 | \r | |
223 | /**\r | |
224 | Check whether system error occurred.\r | |
225 | \r | |
226 | @param Ehc The EHCI device.\r | |
227 | \r | |
228 | @retval TRUE System error happened.\r | |
229 | @retval FALSE No system error.\r | |
230 | \r | |
231 | **/\r | |
232 | BOOLEAN\r | |
233 | EhcIsSysError (\r | |
234 | IN PEI_USB2_HC_DEV *Ehc\r | |
235 | )\r | |
236 | ;\r | |
237 | \r | |
238 | /**\r | |
239 | Reset the host controller.\r | |
240 | \r | |
241 | @param Ehc The EHCI device.\r | |
242 | @param Timeout Time to wait before abort (in millisecond, ms).\r | |
243 | \r | |
244 | @retval EFI_TIMEOUT The transfer failed due to time out.\r | |
245 | @retval Others Failed to reset the host.\r | |
246 | \r | |
247 | **/\r | |
248 | EFI_STATUS\r | |
249 | EhcResetHC (\r | |
250 | IN PEI_USB2_HC_DEV *Ehc,\r | |
251 | IN UINT32 Timeout\r | |
252 | )\r | |
253 | ;\r | |
254 | \r | |
255 | /**\r | |
256 | Halt the host controller.\r | |
257 | \r | |
258 | @param Ehc The EHCI device.\r | |
259 | @param Timeout Time to wait before abort.\r | |
260 | \r | |
261 | @retval EFI_TIMEOUT Failed to halt the controller before Timeout.\r | |
262 | @retval EFI_SUCCESS The EHCI is halt.\r | |
263 | \r | |
264 | **/\r | |
265 | EFI_STATUS\r | |
266 | EhcHaltHC (\r | |
267 | IN PEI_USB2_HC_DEV *Ehc,\r | |
268 | IN UINT32 Timeout\r | |
269 | )\r | |
270 | ;\r | |
271 | \r | |
272 | /**\r | |
273 | Set the EHCI to run\r | |
274 | \r | |
275 | @param Ehc The EHCI device.\r | |
276 | @param Timeout Time to wait before abort.\r | |
277 | \r | |
278 | @retval EFI_SUCCESS The EHCI is running.\r | |
279 | @retval Others Failed to set the EHCI to run.\r | |
280 | \r | |
281 | **/\r | |
282 | EFI_STATUS\r | |
283 | EhcRunHC (\r | |
284 | IN PEI_USB2_HC_DEV *Ehc,\r | |
285 | IN UINT32 Timeout\r | |
286 | )\r | |
287 | ;\r | |
288 | \r | |
289 | /**\r | |
290 | Initialize the HC hardware. \r | |
291 | EHCI spec lists the five things to do to initialize the hardware.\r | |
292 | 1. Program CTRLDSSEGMENT.\r | |
293 | 2. Set USBINTR to enable interrupts.\r | |
294 | 3. Set periodic list base.\r | |
295 | 4. Set USBCMD, interrupt threshold, frame list size etc.\r | |
296 | 5. Write 1 to CONFIGFLAG to route all ports to EHCI.\r | |
297 | \r | |
298 | @param Ehc The EHCI device.\r | |
299 | \r | |
300 | @retval EFI_SUCCESS The EHCI has come out of halt state.\r | |
301 | @retval EFI_TIMEOUT Time out happened.\r | |
302 | \r | |
303 | **/\r | |
304 | EFI_STATUS\r | |
305 | EhcInitHC (\r | |
306 | IN PEI_USB2_HC_DEV *Ehc\r | |
307 | )\r | |
308 | ;\r | |
309 | \r | |
310 | #endif\r |