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4b1bf81c | 1 | /** @file\r |
2 | Private Header file for Usb Host Controller PEIM\r | |
3 | \r | |
d1102dba LG |
4 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
5 | \r | |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4b1bf81c | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef _EFI_EHCI_REG_H_\r | |
11 | #define _EFI_EHCI_REG_H_\r | |
12 | \r | |
4b1bf81c | 13 | //\r |
14 | // Capability register offset\r | |
15 | //\r | |
1436aea4 MK |
16 | #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r |
17 | #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r | |
18 | #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r | |
4b1bf81c | 19 | \r |
20 | //\r | |
21 | // Capability register bit definition\r | |
22 | //\r | |
1436aea4 MK |
23 | #define HCSP_NPORTS 0x0F // Number of root hub port\r |
24 | #define HCCP_64BIT 0x01 // 64-bit addressing capability\r | |
4b1bf81c | 25 | \r |
26 | //\r | |
27 | // Operational register offset\r | |
28 | //\r | |
29 | #define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r | |
30 | #define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r | |
31 | #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r | |
32 | #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r | |
33 | #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r | |
34 | #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r | |
35 | #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r | |
36 | #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r | |
37 | #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r | |
38 | \r | |
1436aea4 | 39 | #define EHC_FRAME_LEN 1024\r |
4b1bf81c | 40 | \r |
41 | //\r | |
42 | // Register bit definition\r | |
43 | //\r | |
1436aea4 MK |
44 | #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r |
45 | \r | |
46 | #define USBCMD_RUN 0x01 // Run/stop\r | |
47 | #define USBCMD_RESET 0x02 // Start the host controller reset\r | |
48 | #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r | |
49 | #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r | |
50 | #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r | |
51 | \r | |
52 | #define USBSTS_IAA 0x20 // Interrupt on async advance\r | |
53 | #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r | |
54 | #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r | |
55 | #define USBSTS_HALT 0x1000 // Host controller halted\r | |
56 | #define USBSTS_SYS_ERROR 0x10 // Host system error\r | |
57 | #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r | |
4b1bf81c | 58 | // (write clean) bits in USBSTS register\r |
59 | \r | |
1436aea4 MK |
60 | #define PORTSC_CONN 0x01 // Current Connect Status\r |
61 | #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r | |
62 | #define PORTSC_ENABLED 0x04 // Port Enable / Disable\r | |
63 | #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r | |
64 | #define PORTSC_OVERCUR 0x10 // Over current Active\r | |
65 | #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r | |
66 | #define PORSTSC_RESUME 0x40 // Force Port Resume\r | |
67 | #define PORTSC_SUSPEND 0x80 // Port Suspend State\r | |
68 | #define PORTSC_RESET 0x100 // Port Reset\r | |
69 | #define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r | |
70 | #define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r | |
71 | #define PORTSC_POWER 0x1000 // Port Power\r | |
72 | #define PORTSC_OWNER 0x2000 // Port Owner\r | |
73 | #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r | |
4b1bf81c | 74 | // they are WC (write clean)\r |
75 | //\r | |
76 | // PCI Configuration Registers\r | |
77 | //\r | |
1436aea4 | 78 | #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r |
4b1bf81c | 79 | \r |
1436aea4 | 80 | #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r |
4b1bf81c | 81 | \r |
82 | #define EHC_ADDR(High, QhHw32) \\r | |
83 | ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r | |
84 | \r | |
1436aea4 | 85 | #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r |
4b1bf81c | 86 | \r |
87 | //\r | |
d1102dba LG |
88 | // Structure to map the hardware port states to the\r |
89 | // UEFI's port states.\r | |
4b1bf81c | 90 | //\r |
91 | typedef struct {\r | |
1436aea4 MK |
92 | UINT16 HwState;\r |
93 | UINT16 UefiState;\r | |
4b1bf81c | 94 | } USB_PORT_STATE_MAP;\r |
95 | \r | |
96 | //\r | |
97 | // Ehci Data and Ctrl Structures\r | |
98 | //\r | |
99 | #pragma pack(1)\r | |
100 | typedef struct {\r | |
1436aea4 MK |
101 | UINT8 Pi;\r |
102 | UINT8 SubClassCode;\r | |
103 | UINT8 BaseCode;\r | |
4b1bf81c | 104 | } USB_CLASSC;\r |
105 | #pragma pack()\r | |
106 | \r | |
4b1bf81c | 107 | /**\r |
108 | Read EHCI capability register.\r | |
d1102dba | 109 | \r |
4b1bf81c | 110 | @param Ehc The EHCI device.\r |
111 | @param Offset Capability register address.\r | |
112 | \r | |
113 | @retval the register content read.\r | |
114 | \r | |
115 | **/\r | |
116 | UINT32\r | |
117 | EhcReadCapRegister (\r | |
1436aea4 MK |
118 | IN PEI_USB2_HC_DEV *Ehc,\r |
119 | IN UINT32 Offset\r | |
4b1bf81c | 120 | )\r |
121 | ;\r | |
122 | \r | |
123 | /**\r | |
124 | Read Ehc Operation register.\r | |
d1102dba | 125 | \r |
4b1bf81c | 126 | @param Ehc The EHCI device.\r |
127 | @param Offset The operation register offset.\r | |
128 | \r | |
129 | @retval the register content read.\r | |
130 | \r | |
131 | **/\r | |
132 | UINT32\r | |
133 | EhcReadOpReg (\r | |
1436aea4 MK |
134 | IN PEI_USB2_HC_DEV *Ehc,\r |
135 | IN UINT32 Offset\r | |
4b1bf81c | 136 | )\r |
137 | ;\r | |
138 | \r | |
139 | /**\r | |
140 | Write the data to the EHCI operation register.\r | |
d1102dba | 141 | \r |
4b1bf81c | 142 | @param Ehc The EHCI device.\r |
143 | @param Offset EHCI operation register offset.\r | |
144 | @param Data The data to write.\r | |
145 | \r | |
146 | **/\r | |
147 | VOID\r | |
148 | EhcWriteOpReg (\r | |
1436aea4 MK |
149 | IN PEI_USB2_HC_DEV *Ehc,\r |
150 | IN UINT32 Offset,\r | |
151 | IN UINT32 Data\r | |
4b1bf81c | 152 | )\r |
153 | ;\r | |
154 | \r | |
155 | /**\r | |
156 | Stop the legacy USB SMI support.\r | |
d1102dba | 157 | \r |
4b1bf81c | 158 | @param Ehc The EHCI device.\r |
159 | \r | |
160 | **/\r | |
161 | VOID\r | |
162 | EhcClearLegacySupport (\r | |
1436aea4 | 163 | IN PEI_USB2_HC_DEV *Ehc\r |
4b1bf81c | 164 | )\r |
165 | ;\r | |
166 | \r | |
167 | /**\r | |
168 | Set door bell and wait it to be ACKed by host controller.\r | |
169 | This function is used to synchronize with the hardware.\r | |
d1102dba | 170 | \r |
4b1bf81c | 171 | @param Ehc The EHCI device.\r |
172 | @param Timeout The time to wait before abort (in millisecond, ms).\r | |
173 | \r | |
174 | @retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r | |
175 | @retval EFI_SUCCESS Synchronized with the hardware.\r | |
176 | \r | |
177 | **/\r | |
178 | EFI_STATUS\r | |
179 | EhcSetAndWaitDoorBell (\r | |
1436aea4 MK |
180 | IN PEI_USB2_HC_DEV *Ehc,\r |
181 | IN UINT32 Timeout\r | |
4b1bf81c | 182 | )\r |
183 | ;\r | |
184 | \r | |
185 | /**\r | |
d1102dba | 186 | Clear all the interrutp status bits, these bits\r |
4b1bf81c | 187 | are Write-Clean.\r |
d1102dba | 188 | \r |
4b1bf81c | 189 | @param Ehc The EHCI device.\r |
190 | \r | |
191 | **/\r | |
192 | VOID\r | |
193 | EhcAckAllInterrupt (\r | |
1436aea4 | 194 | IN PEI_USB2_HC_DEV *Ehc\r |
4b1bf81c | 195 | )\r |
196 | ;\r | |
197 | \r | |
198 | /**\r | |
199 | Check whether Ehc is halted.\r | |
d1102dba | 200 | \r |
4b1bf81c | 201 | @param Ehc The EHCI device.\r |
202 | \r | |
203 | @retval TRUE The controller is halted.\r | |
204 | @retval FALSE The controller isn't halted.\r | |
205 | \r | |
206 | **/\r | |
207 | BOOLEAN\r | |
208 | EhcIsHalt (\r | |
1436aea4 | 209 | IN PEI_USB2_HC_DEV *Ehc\r |
4b1bf81c | 210 | )\r |
211 | ;\r | |
212 | \r | |
213 | /**\r | |
214 | Check whether system error occurred.\r | |
d1102dba | 215 | \r |
4b1bf81c | 216 | @param Ehc The EHCI device.\r |
217 | \r | |
218 | @retval TRUE System error happened.\r | |
219 | @retval FALSE No system error.\r | |
220 | \r | |
221 | **/\r | |
222 | BOOLEAN\r | |
223 | EhcIsSysError (\r | |
1436aea4 | 224 | IN PEI_USB2_HC_DEV *Ehc\r |
4b1bf81c | 225 | )\r |
226 | ;\r | |
227 | \r | |
228 | /**\r | |
229 | Reset the host controller.\r | |
d1102dba | 230 | \r |
4b1bf81c | 231 | @param Ehc The EHCI device.\r |
232 | @param Timeout Time to wait before abort (in millisecond, ms).\r | |
233 | \r | |
234 | @retval EFI_TIMEOUT The transfer failed due to time out.\r | |
235 | @retval Others Failed to reset the host.\r | |
236 | \r | |
237 | **/\r | |
238 | EFI_STATUS\r | |
239 | EhcResetHC (\r | |
1436aea4 MK |
240 | IN PEI_USB2_HC_DEV *Ehc,\r |
241 | IN UINT32 Timeout\r | |
4b1bf81c | 242 | )\r |
243 | ;\r | |
244 | \r | |
245 | /**\r | |
246 | Halt the host controller.\r | |
d1102dba | 247 | \r |
4b1bf81c | 248 | @param Ehc The EHCI device.\r |
249 | @param Timeout Time to wait before abort.\r | |
250 | \r | |
251 | @retval EFI_TIMEOUT Failed to halt the controller before Timeout.\r | |
252 | @retval EFI_SUCCESS The EHCI is halt.\r | |
253 | \r | |
254 | **/\r | |
255 | EFI_STATUS\r | |
256 | EhcHaltHC (\r | |
1436aea4 MK |
257 | IN PEI_USB2_HC_DEV *Ehc,\r |
258 | IN UINT32 Timeout\r | |
4b1bf81c | 259 | )\r |
260 | ;\r | |
261 | \r | |
262 | /**\r | |
263 | Set the EHCI to run\r | |
d1102dba | 264 | \r |
4b1bf81c | 265 | @param Ehc The EHCI device.\r |
266 | @param Timeout Time to wait before abort.\r | |
267 | \r | |
268 | @retval EFI_SUCCESS The EHCI is running.\r | |
269 | @retval Others Failed to set the EHCI to run.\r | |
270 | \r | |
271 | **/\r | |
272 | EFI_STATUS\r | |
273 | EhcRunHC (\r | |
1436aea4 MK |
274 | IN PEI_USB2_HC_DEV *Ehc,\r |
275 | IN UINT32 Timeout\r | |
4b1bf81c | 276 | )\r |
277 | ;\r | |
278 | \r | |
279 | /**\r | |
d1102dba | 280 | Initialize the HC hardware.\r |
4b1bf81c | 281 | EHCI spec lists the five things to do to initialize the hardware.\r |
282 | 1. Program CTRLDSSEGMENT.\r | |
283 | 2. Set USBINTR to enable interrupts.\r | |
284 | 3. Set periodic list base.\r | |
285 | 4. Set USBCMD, interrupt threshold, frame list size etc.\r | |
286 | 5. Write 1 to CONFIGFLAG to route all ports to EHCI.\r | |
d1102dba | 287 | \r |
4b1bf81c | 288 | @param Ehc The EHCI device.\r |
289 | \r | |
290 | @retval EFI_SUCCESS The EHCI has come out of halt state.\r | |
291 | @retval EFI_TIMEOUT Time out happened.\r | |
292 | \r | |
293 | **/\r | |
294 | EFI_STATUS\r | |
295 | EhcInitHC (\r | |
1436aea4 | 296 | IN PEI_USB2_HC_DEV *Ehc\r |
4b1bf81c | 297 | )\r |
298 | ;\r | |
299 | \r | |
300 | #endif\r |