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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h
2 Private Header file for Usb Host Controller PEIM
4 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _EFI_EHCI_REG_H_
11 #define _EFI_EHCI_REG_H_
16 // Capability register offset
18 #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
19 #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
20 #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
23 // Capability register bit definition
25 #define HCSP_NPORTS 0x0F // Number of root hub port
26 #define HCCP_64BIT 0x01 // 64-bit addressing capability
29 // Operational register offset
31 #define EHC_USBCMD_OFFSET 0x0 // USB command register offset
32 #define EHC_USBSTS_OFFSET 0x04 // Statue register offset
33 #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset
34 #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset
35 #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset
36 #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset
37 #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset
38 #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
39 #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
41 #define EHC_FRAME_LEN 1024
44 // Register bit definition
46 #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
48 #define USBCMD_RUN 0x01 // Run/stop
49 #define USBCMD_RESET 0x02 // Start the host controller reset
50 #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
51 #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
52 #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
54 #define USBSTS_IAA 0x20 // Interrupt on async advance
55 #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
56 #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
57 #define USBSTS_HALT 0x1000 // Host controller halted
58 #define USBSTS_SYS_ERROR 0x10 // Host system error
59 #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
60 // (write clean) bits in USBSTS register
62 #define PORTSC_CONN 0x01 // Current Connect Status
63 #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
64 #define PORTSC_ENABLED 0x04 // Port Enable / Disable
65 #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
66 #define PORTSC_OVERCUR 0x10 // Over current Active
67 #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
68 #define PORSTSC_RESUME 0x40 // Force Port Resume
69 #define PORTSC_SUSPEND 0x80 // Port Suspend State
70 #define PORTSC_RESET 0x100 // Port Reset
71 #define PORTSC_LINESTATE_K 0x400 // Line Status K-state
72 #define PORTSC_LINESTATE_J 0x800 // Line Status J-state
73 #define PORTSC_POWER 0x1000 // Port Power
74 #define PORTSC_OWNER 0x2000 // Port Owner
75 #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
76 // they are WC (write clean)
78 // PCI Configuration Registers
80 #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
82 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
84 #define EHC_ADDR(High, QhHw32) \
85 ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
87 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
90 // Structure to map the hardware port states to the
91 // UEFI's port states.
99 // Ehci Data and Ctrl Structures
111 Read EHCI capability register.
113 @param Ehc The EHCI device.
114 @param Offset Capability register address.
116 @retval the register content read.
121 IN PEI_USB2_HC_DEV
*Ehc
,
127 Read Ehc Operation register.
129 @param Ehc The EHCI device.
130 @param Offset The operation register offset.
132 @retval the register content read.
137 IN PEI_USB2_HC_DEV
*Ehc
,
143 Write the data to the EHCI operation register.
145 @param Ehc The EHCI device.
146 @param Offset EHCI operation register offset.
147 @param Data The data to write.
152 IN PEI_USB2_HC_DEV
*Ehc
,
159 Stop the legacy USB SMI support.
161 @param Ehc The EHCI device.
165 EhcClearLegacySupport (
166 IN PEI_USB2_HC_DEV
*Ehc
171 Set door bell and wait it to be ACKed by host controller.
172 This function is used to synchronize with the hardware.
174 @param Ehc The EHCI device.
175 @param Timeout The time to wait before abort (in millisecond, ms).
177 @retval EFI_TIMEOUT Time out happened while waiting door bell to set.
178 @retval EFI_SUCCESS Synchronized with the hardware.
182 EhcSetAndWaitDoorBell (
183 IN PEI_USB2_HC_DEV
*Ehc
,
189 Clear all the interrutp status bits, these bits
192 @param Ehc The EHCI device.
197 IN PEI_USB2_HC_DEV
*Ehc
202 Check whether Ehc is halted.
204 @param Ehc The EHCI device.
206 @retval TRUE The controller is halted.
207 @retval FALSE The controller isn't halted.
212 IN PEI_USB2_HC_DEV
*Ehc
217 Check whether system error occurred.
219 @param Ehc The EHCI device.
221 @retval TRUE System error happened.
222 @retval FALSE No system error.
227 IN PEI_USB2_HC_DEV
*Ehc
232 Reset the host controller.
234 @param Ehc The EHCI device.
235 @param Timeout Time to wait before abort (in millisecond, ms).
237 @retval EFI_TIMEOUT The transfer failed due to time out.
238 @retval Others Failed to reset the host.
243 IN PEI_USB2_HC_DEV
*Ehc
,
249 Halt the host controller.
251 @param Ehc The EHCI device.
252 @param Timeout Time to wait before abort.
254 @retval EFI_TIMEOUT Failed to halt the controller before Timeout.
255 @retval EFI_SUCCESS The EHCI is halt.
260 IN PEI_USB2_HC_DEV
*Ehc
,
268 @param Ehc The EHCI device.
269 @param Timeout Time to wait before abort.
271 @retval EFI_SUCCESS The EHCI is running.
272 @retval Others Failed to set the EHCI to run.
277 IN PEI_USB2_HC_DEV
*Ehc
,
283 Initialize the HC hardware.
284 EHCI spec lists the five things to do to initialize the hardware.
285 1. Program CTRLDSSEGMENT.
286 2. Set USBINTR to enable interrupts.
287 3. Set periodic list base.
288 4. Set USBCMD, interrupt threshold, frame list size etc.
289 5. Write 1 to CONFIGFLAG to route all ports to EHCI.
291 @param Ehc The EHCI device.
293 @retval EFI_SUCCESS The EHCI has come out of halt state.
294 @retval EFI_TIMEOUT Time out happened.
299 IN PEI_USB2_HC_DEV
*Ehc