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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NonDiscoverablePciDeviceDxe / NonDiscoverablePciDeviceIo.h
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1/** @file\r
2\r
3 Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>\r
4\r
9d510e61 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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6\r
7**/\r
8\r
9#ifndef __NON_DISCOVERABLE_PCI_DEVICE_IO_H__\r
10#define __NON_DISCOVERABLE_PCI_DEVICE_IO_H__\r
11\r
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12#include <PiDxe.h>\r
13\r
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14#include <Library/BaseMemoryLib.h>\r
15#include <Library/DebugLib.h>\r
16#include <Library/MemoryAllocationLib.h>\r
17#include <Library/UefiBootServicesTableLib.h>\r
18#include <Library/UefiLib.h>\r
19\r
20#include <IndustryStandard/Pci.h>\r
21\r
22#include <Protocol/ComponentName.h>\r
23#include <Protocol/NonDiscoverableDevice.h>\r
16296a12 24#include <Protocol/Cpu.h>\r
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25#include <Protocol/PciIo.h>\r
26\r
1436aea4 27#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')\r
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28\r
29#define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \\r
30 CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \\r
31 NON_DISCOVERABLE_PCI_DEVICE_SIG)\r
32\r
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33#define DEV_SUPPORTED_ATTRIBUTES \\r
34 (EFI_PCI_DEVICE_ENABLE | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
35\r
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36#define PCI_ID_VENDOR_UNKNOWN 0xffff\r
37#define PCI_ID_DEVICE_DONTCARE 0x0000\r
a42e6d44 38\r
1436aea4 39extern EFI_CPU_ARCH_PROTOCOL *mCpu;\r
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40\r
41typedef struct {\r
42 //\r
43 // The linked-list next pointer\r
44 //\r
1436aea4 45 LIST_ENTRY List;\r
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46 //\r
47 // The address of the uncached allocation\r
48 //\r
1436aea4 49 VOID *HostAddress;\r
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50 //\r
51 // The number of pages in the allocation\r
52 //\r
1436aea4 53 UINTN NumPages;\r
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54 //\r
55 // The attributes of the allocation\r
56 //\r
1436aea4 57 UINT64 Attributes;\r
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58} NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION;\r
59\r
a42e6d44 60typedef struct {\r
1436aea4 61 UINT32 Signature;\r
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62 //\r
63 // The bound non-discoverable device protocol instance\r
64 //\r
1436aea4 65 NON_DISCOVERABLE_DEVICE *Device;\r
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66 //\r
67 // The exposed PCI I/O protocol instance.\r
68 //\r
1436aea4 69 EFI_PCI_IO_PROTOCOL PciIo;\r
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70 //\r
71 // The emulated PCI config space of the device. Only the minimally required\r
72 // items are assigned.\r
73 //\r
1436aea4 74 PCI_TYPE00 ConfigSpace;\r
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75 //\r
76 // The first virtual BAR to assign based on the resources described\r
77 // by the non-discoverable device.\r
78 //\r
1436aea4 79 UINT32 BarOffset;\r
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80 //\r
81 // The number of virtual BARs we expose based on the number of\r
82 // resources\r
83 //\r
1436aea4 84 UINT32 BarCount;\r
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85 //\r
86 // The PCI I/O attributes for this device\r
87 //\r
1436aea4 88 UINT64 Attributes;\r
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89 //\r
90 // Whether this device has been enabled\r
91 //\r
1436aea4 92 BOOLEAN Enabled;\r
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93 //\r
94 // Linked list to keep track of uncached allocations performed\r
95 // on behalf of this device\r
96 //\r
1436aea4 97 LIST_ENTRY UncachedAllocationList;\r
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98 //\r
99 // Unique ID for this device instance: needed so that we can report unique\r
100 // segment/bus/device number for each device instance. Note that this number\r
101 // may change when disconnecting/reconnecting the driver.\r
102 //\r
1436aea4 103 UINTN UniqueId;\r
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104} NON_DISCOVERABLE_PCI_DEVICE;\r
105\r
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106/**\r
107 Initialize PciIo Protocol.\r
108\r
109 @param Device Point to NON_DISCOVERABLE_PCI_DEVICE instance.\r
110\r
111**/\r
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112VOID\r
113InitializePciIoProtocol (\r
1436aea4 114 NON_DISCOVERABLE_PCI_DEVICE *Device\r
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115 );\r
116\r
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117extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;\r
118extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;\r
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119\r
120#endif\r