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a42e6d44 AB |
1 | /** @file\r |
2 | \r | |
3 | Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>\r | |
4 | \r | |
9d510e61 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a42e6d44 AB |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #ifndef __NON_DISCOVERABLE_PCI_DEVICE_IO_H__\r | |
10 | #define __NON_DISCOVERABLE_PCI_DEVICE_IO_H__\r | |
11 | \r | |
16296a12 AB |
12 | #include <PiDxe.h>\r |
13 | \r | |
a42e6d44 AB |
14 | #include <Library/BaseMemoryLib.h>\r |
15 | #include <Library/DebugLib.h>\r | |
16 | #include <Library/MemoryAllocationLib.h>\r | |
17 | #include <Library/UefiBootServicesTableLib.h>\r | |
18 | #include <Library/UefiLib.h>\r | |
19 | \r | |
20 | #include <IndustryStandard/Pci.h>\r | |
21 | \r | |
22 | #include <Protocol/ComponentName.h>\r | |
23 | #include <Protocol/NonDiscoverableDevice.h>\r | |
16296a12 | 24 | #include <Protocol/Cpu.h>\r |
a42e6d44 AB |
25 | #include <Protocol/PciIo.h>\r |
26 | \r | |
1436aea4 | 27 | #define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')\r |
a42e6d44 AB |
28 | \r |
29 | #define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \\r | |
30 | CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \\r | |
31 | NON_DISCOVERABLE_PCI_DEVICE_SIG)\r | |
32 | \r | |
3b9cd714 GJ |
33 | #define DEV_SUPPORTED_ATTRIBUTES \\r |
34 | (EFI_PCI_DEVICE_ENABLE | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r | |
35 | \r | |
1436aea4 MK |
36 | #define PCI_ID_VENDOR_UNKNOWN 0xffff\r |
37 | #define PCI_ID_DEVICE_DONTCARE 0x0000\r | |
a42e6d44 | 38 | \r |
1436aea4 | 39 | extern EFI_CPU_ARCH_PROTOCOL *mCpu;\r |
16296a12 AB |
40 | \r |
41 | typedef struct {\r | |
42 | //\r | |
43 | // The linked-list next pointer\r | |
44 | //\r | |
1436aea4 | 45 | LIST_ENTRY List;\r |
16296a12 AB |
46 | //\r |
47 | // The address of the uncached allocation\r | |
48 | //\r | |
1436aea4 | 49 | VOID *HostAddress;\r |
16296a12 AB |
50 | //\r |
51 | // The number of pages in the allocation\r | |
52 | //\r | |
1436aea4 | 53 | UINTN NumPages;\r |
16296a12 AB |
54 | //\r |
55 | // The attributes of the allocation\r | |
56 | //\r | |
1436aea4 | 57 | UINT64 Attributes;\r |
16296a12 AB |
58 | } NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION;\r |
59 | \r | |
a42e6d44 | 60 | typedef struct {\r |
1436aea4 | 61 | UINT32 Signature;\r |
a42e6d44 AB |
62 | //\r |
63 | // The bound non-discoverable device protocol instance\r | |
64 | //\r | |
1436aea4 | 65 | NON_DISCOVERABLE_DEVICE *Device;\r |
a42e6d44 AB |
66 | //\r |
67 | // The exposed PCI I/O protocol instance.\r | |
68 | //\r | |
1436aea4 | 69 | EFI_PCI_IO_PROTOCOL PciIo;\r |
a42e6d44 AB |
70 | //\r |
71 | // The emulated PCI config space of the device. Only the minimally required\r | |
72 | // items are assigned.\r | |
73 | //\r | |
1436aea4 | 74 | PCI_TYPE00 ConfigSpace;\r |
a42e6d44 AB |
75 | //\r |
76 | // The first virtual BAR to assign based on the resources described\r | |
77 | // by the non-discoverable device.\r | |
78 | //\r | |
1436aea4 | 79 | UINT32 BarOffset;\r |
a42e6d44 AB |
80 | //\r |
81 | // The number of virtual BARs we expose based on the number of\r | |
82 | // resources\r | |
83 | //\r | |
1436aea4 | 84 | UINT32 BarCount;\r |
a42e6d44 AB |
85 | //\r |
86 | // The PCI I/O attributes for this device\r | |
87 | //\r | |
1436aea4 | 88 | UINT64 Attributes;\r |
a42e6d44 AB |
89 | //\r |
90 | // Whether this device has been enabled\r | |
91 | //\r | |
1436aea4 | 92 | BOOLEAN Enabled;\r |
16296a12 AB |
93 | //\r |
94 | // Linked list to keep track of uncached allocations performed\r | |
95 | // on behalf of this device\r | |
96 | //\r | |
1436aea4 | 97 | LIST_ENTRY UncachedAllocationList;\r |
1a3bee20 AB |
98 | //\r |
99 | // Unique ID for this device instance: needed so that we can report unique\r | |
100 | // segment/bus/device number for each device instance. Note that this number\r | |
101 | // may change when disconnecting/reconnecting the driver.\r | |
102 | //\r | |
1436aea4 | 103 | UINTN UniqueId;\r |
a42e6d44 AB |
104 | } NON_DISCOVERABLE_PCI_DEVICE;\r |
105 | \r | |
43b7cd61 DB |
106 | /**\r |
107 | Initialize PciIo Protocol.\r | |
108 | \r | |
109 | @param Device Point to NON_DISCOVERABLE_PCI_DEVICE instance.\r | |
110 | \r | |
111 | **/\r | |
a42e6d44 AB |
112 | VOID\r |
113 | InitializePciIoProtocol (\r | |
1436aea4 | 114 | NON_DISCOVERABLE_PCI_DEVICE *Device\r |
a42e6d44 AB |
115 | );\r |
116 | \r | |
1436aea4 MK |
117 | extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;\r |
118 | extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;\r | |
a42e6d44 AB |
119 | \r |
120 | #endif\r |