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1/** @file\r
2\r
3 Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>\r
4\r
9d510e61 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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6\r
7**/\r
8\r
9#ifndef __NON_DISCOVERABLE_PCI_DEVICE_IO_H__\r
10#define __NON_DISCOVERABLE_PCI_DEVICE_IO_H__\r
11\r
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12#include <PiDxe.h>\r
13\r
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14#include <Library/BaseMemoryLib.h>\r
15#include <Library/DebugLib.h>\r
16#include <Library/MemoryAllocationLib.h>\r
17#include <Library/UefiBootServicesTableLib.h>\r
18#include <Library/UefiLib.h>\r
19\r
20#include <IndustryStandard/Pci.h>\r
21\r
22#include <Protocol/ComponentName.h>\r
23#include <Protocol/NonDiscoverableDevice.h>\r
16296a12 24#include <Protocol/Cpu.h>\r
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25#include <Protocol/PciIo.h>\r
26\r
27#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')\r
28\r
29#define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \\r
30 CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \\r
31 NON_DISCOVERABLE_PCI_DEVICE_SIG)\r
32\r
33#define PCI_ID_VENDOR_UNKNOWN 0xffff\r
34#define PCI_ID_DEVICE_DONTCARE 0x0000\r
35\r
36#define PCI_MAX_BARS 6\r
37\r
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38extern EFI_CPU_ARCH_PROTOCOL *mCpu;\r
39\r
40typedef struct {\r
41 //\r
42 // The linked-list next pointer\r
43 //\r
44 LIST_ENTRY List;\r
45 //\r
46 // The address of the uncached allocation\r
47 //\r
48 VOID *HostAddress;\r
49 //\r
50 // The number of pages in the allocation\r
51 //\r
52 UINTN NumPages;\r
53 //\r
54 // The attributes of the allocation\r
55 //\r
56 UINT64 Attributes;\r
57} NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION;\r
58\r
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59typedef struct {\r
60 UINT32 Signature;\r
61 //\r
62 // The bound non-discoverable device protocol instance\r
63 //\r
64 NON_DISCOVERABLE_DEVICE *Device;\r
65 //\r
66 // The exposed PCI I/O protocol instance.\r
67 //\r
68 EFI_PCI_IO_PROTOCOL PciIo;\r
69 //\r
70 // The emulated PCI config space of the device. Only the minimally required\r
71 // items are assigned.\r
72 //\r
73 PCI_TYPE00 ConfigSpace;\r
74 //\r
75 // The first virtual BAR to assign based on the resources described\r
76 // by the non-discoverable device.\r
77 //\r
78 UINT32 BarOffset;\r
79 //\r
80 // The number of virtual BARs we expose based on the number of\r
81 // resources\r
82 //\r
83 UINT32 BarCount;\r
84 //\r
85 // The PCI I/O attributes for this device\r
86 //\r
87 UINT64 Attributes;\r
88 //\r
89 // Whether this device has been enabled\r
90 //\r
91 BOOLEAN Enabled;\r
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92 //\r
93 // Linked list to keep track of uncached allocations performed\r
94 // on behalf of this device\r
95 //\r
96 LIST_ENTRY UncachedAllocationList;\r
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97 //\r
98 // Unique ID for this device instance: needed so that we can report unique\r
99 // segment/bus/device number for each device instance. Note that this number\r
100 // may change when disconnecting/reconnecting the driver.\r
101 //\r
102 UINTN UniqueId;\r
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103} NON_DISCOVERABLE_PCI_DEVICE;\r
104\r
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105/**\r
106 Initialize PciIo Protocol.\r
107\r
108 @param Device Point to NON_DISCOVERABLE_PCI_DEVICE instance.\r
109\r
110**/\r
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111VOID\r
112InitializePciIoProtocol (\r
113 NON_DISCOVERABLE_PCI_DEVICE *Device\r
114 );\r
115\r
116extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;\r
117extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;\r
118\r
119#endif\r