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MdeModulePkg/NvmExpressDxe: fix build error
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressPassthru.c
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eb290d02
FT		 1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
35f910f0 5 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r
769402ef 6 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
eb290d02
FT		 7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php.\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include "NvmExpress.h"\r
18\r
19//\r
20// Page size should be set in the Controller Configuration register\r
21// during controller init, and the controller configuration save in\r
22// the controller's private data. The Max and Min supported page sizes\r
23// for the controller are specified in the Controller Capabilities register.\r
24//\r
25\r
26GLOBAL_REMOVE_IF_UNREFERENCED NVM_EXPRESS_PASS_THRU_MODE gNvmExpressPassThruMode = {\r
27 0,\r
28 NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL | NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVME,\r
29 sizeof (UINTN),\r
30 0x10000,\r
31 0,\r
32 0\r
33};\r
34\r
35\r
36/**\r
37 Dump the execution status from a given completion queue entry.\r
38\r
39 @param[in] Cq A pointer to the NVME_CQ item.\r
40\r
41**/\r
42VOID\r
43NvmeDumpStatus (\r
44 IN NVME_CQ *Cq\r
45 )\r
46{\r
47 DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r
48\r
49 DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r
50\r
51 DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r
52\r
53 switch (Cq->Sct) {\r
54 case 0x0:\r
55 switch (Cq->Sc) {\r
56 case 0x0:\r
57 DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r
58 break;\r
59 case 0x1:\r
60 DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r
61 break;\r
62 case 0x2:\r
63 DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r
64 break;\r
65 case 0x3:\r
66 DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r
67 break;\r
68 case 0x4:\r
69 DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r
70 break;\r
71 case 0x5:\r
72 DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r
73 break;\r
74 case 0x6:\r
75 DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r
76 break;\r
77 case 0x7:\r
78 DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r
79 break;\r
80 case 0x8:\r
81 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r
82 break;\r
83 case 0x9:\r
84 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r
85 break;\r
86 case 0xA:\r
87 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r
88 break;\r
89 case 0xB:\r
90 DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r
91 break;\r
92 case 0xC:\r
93 DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r
94 break;\r
95 case 0xD:\r
96 DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r
97 break;\r
98 case 0xE:\r
99 DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r
100 break;\r
101 case 0xF:\r
102 DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r
103 break;\r
104 case 0x10:\r
105 DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r
106 break;\r
107 case 0x11:\r
108 DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r
109 break;\r
110 case 0x80:\r
111 DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r
112 break;\r
113 case 0x81:\r
114 DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r
115 break;\r
116 case 0x82:\r
117 DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r
118 break;\r
119 case 0x83:\r
120 DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r
121 break;\r
122 }\r
123 break;\r
124\r
125 case 0x1:\r
126 switch (Cq->Sc) {\r
127 case 0x0:\r
128 DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r
129 break;\r
130 case 0x1:\r
131 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r
132 break;\r
133 case 0x2:\r
134 DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r
135 break;\r
136 case 0x3:\r
137 DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r
138 break;\r
139 case 0x5:\r
140 DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r
141 break;\r
142 case 0x6:\r
143 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r
144 break;\r
145 case 0x7:\r
146 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r
147 break;\r
148 case 0x8:\r
149 DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r
150 break;\r
151 case 0x9:\r
152 DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r
153 break;\r
154 case 0xA:\r
155 DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r
156 break;\r
157 case 0xB:\r
158 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r
159 break;\r
160 case 0xC:\r
161 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r
162 break;\r
163 case 0xD:\r
164 DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r
165 break;\r
166 case 0xE:\r
167 DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r
168 break;\r
169 case 0xF:\r
170 DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r
171 break;\r
172 case 0x10:\r
173 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r
174 break;\r
175 case 0x80:\r
176 DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r
177 break;\r
178 case 0x81:\r
179 DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r
180 break;\r
181 case 0x82:\r
182 DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r
183 break;\r
184 }\r
185 break;\r
186\r
187 case 0x2:\r
188 switch (Cq->Sc) {\r
189 case 0x80:\r
190 DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r
191 break;\r
192 case 0x81:\r
193 DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r
194 break;\r
195 case 0x82:\r
196 DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r
197 break;\r
198 case 0x83:\r
199 DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r
200 break;\r
201 case 0x84:\r
202 DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r
203 break;\r
204 case 0x85:\r
205 DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r
206 break;\r
207 case 0x86:\r
208 DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r
209 break;\r
210 }\r
211 break;\r
212\r
213 default:\r
214 break;\r
215 }\r
216}\r
217\r
218/**\r
219 Create PRP lists for data transfer which is larger than 2 memory pages.\r
220 Note here we calcuate the number of required PRP lists and allocate them at one time.\r
221\r
222 @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
223 @param[in] PhysicalAddr The physical base address of data buffer.\r
224 @param[in] Pages The number of pages to be transfered.\r
225 @param[out] PrpListHost The host base address of PRP lists.\r
226 @param[in,out] PrpListNo The number of PRP List.\r
227 @param[out] Mapping The mapping value returned from PciIo.Map().\r
228\r
229 @retval The pointer to the first PRP List of the PRP lists.\r
230\r
231**/\r
232VOID*\r
233NvmeCreatePrpList (\r
234 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
235 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r
236 IN UINTN Pages,\r
237 OUT VOID **PrpListHost,\r
238 IN OUT UINTN *PrpListNo,\r
239 OUT VOID **Mapping\r
240 )\r
241{\r
242 UINTN PrpEntryNo;\r
243 UINT64 PrpListBase;\r
244 UINTN PrpListIndex;\r
245 UINTN PrpEntryIndex;\r
246 UINT64 Remainder;\r
247 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r
248 UINTN Bytes;\r
249 EFI_STATUS Status;\r
250\r
251 //\r
252 // The number of Prp Entry in a memory page.\r
253 //\r
254 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r
255\r
256 //\r
257 // Calculate total PrpList number.\r
258 //\r
769402ef
FT		 259 *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);\r
260 if (*PrpListNo == 0) {\r
261 *PrpListNo = 1;\r
a9ec6d65 262 } else if ((Remainder != 0) && (Remainder != 1)) {\r
eb290d02 263 *PrpListNo += 1;\r
769402ef
FT		 264 } else if (Remainder == 1) {\r
265 Remainder = PrpEntryNo;\r
266 } else if (Remainder == 0) {\r
267 Remainder = PrpEntryNo - 1;\r
eb290d02
FT		 268 }\r
269\r
270 Status = PciIo->AllocateBuffer (\r
271 PciIo,\r
272 AllocateAnyPages,\r
273 EfiBootServicesData,\r
274 *PrpListNo,\r
275 PrpListHost,\r
276 0\r
277 );\r
278\r
279 if (EFI_ERROR (Status)) {\r
280 return NULL;\r
281 }\r
282\r
283 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r
284 Status = PciIo->Map (\r
285 PciIo,\r
286 EfiPciIoOperationBusMasterCommonBuffer,\r
287 *PrpListHost,\r
288 &Bytes,\r
289 &PrpListPhyAddr,\r
290 Mapping\r
291 );\r
292\r
293 if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r
294 DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r
295 goto EXIT;\r
296 }\r
297 //\r
298 // Fill all PRP lists except of last one.\r
299 //\r
300 ZeroMem (*PrpListHost, Bytes);\r
301 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r
769402ef 302 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
eb290d02
FT		 303\r
304 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r
305 if (PrpEntryIndex != PrpEntryNo - 1) {\r
306 //\r
307 // Fill all PRP entries except of last one.\r
308 //\r
309 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
310 PhysicalAddr += EFI_PAGE_SIZE;\r
311 } else {\r
312 //\r
313 // Fill last PRP entries with next PRP List pointer.\r
314 //\r
315 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r
316 }\r
317 }\r
318 }\r
319 //\r
320 // Fill last PRP list.\r
321 //\r
322 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
769402ef 323 for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {\r
eb290d02
FT		 324 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
325 PhysicalAddr += EFI_PAGE_SIZE;\r
326 }\r
327\r
328 return (VOID*)(UINTN)PrpListPhyAddr;\r
329\r
330EXIT:\r
331 PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r
332 return NULL;\r
333}\r
334\r
335\r
336/**\r
337 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
338 both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
339 I/O functionality is optional.\r
340\r
341 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
342 @param[in] NamespaceId Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
343 A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace\r
344 ID specifies that the command packet should be sent to all valid namespaces.\r
345 @param[in] NamespaceUuid Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
346 A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace\r
347 UUID specifies that the command packet should be sent to all valid namespaces.\r
348 @param[in,out] Packet A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
349 by NamespaceId.\r
350 @param[in] Event If nonblocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r
351 If Event is NULL, then blocking I/O is performed. If Event is not NULL and non blocking I/O\r
352 is supported, then nonblocking I/O is performed, and Event will be signaled when the NVM\r
353 Express Command Packet completes.\r
354\r
355 @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
356 to, or from DataBuffer.\r
357 @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r
358 is returned in TransferLength.\r
359 @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
360 may retry again later.\r
361 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r
362 @retval EFI_INVALID_PARAMETER Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
363 Express Command Packet was not sent, so no additional status information is available.\r
364 @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the host adapter.\r
365 The NVM Express Command Packet was not sent, so no additional status information is available.\r
366 @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
367\r
368**/\r
369EFI_STATUS\r
370EFIAPI\r
371NvmExpressPassThru (\r
372 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
373 IN UINT32 NamespaceId,\r
374 IN UINT64 NamespaceUuid,\r
375 IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r
376 IN EFI_EVENT Event OPTIONAL\r
377 )\r
378{\r
379 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
380 EFI_STATUS Status;\r
381 EFI_PCI_IO_PROTOCOL *PciIo;\r
382 NVME_SQ *Sq;\r
383 NVME_CQ *Cq;\r
384 UINT8 Qid;\r
385 UINT32 Bytes;\r
386 UINT16 Offset;\r
387 EFI_EVENT TimerEvent;\r
388 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
389 EFI_PHYSICAL_ADDRESS PhyAddr;\r
390 VOID *MapData;\r
391 VOID *MapMeta;\r
392 VOID *MapPrpList;\r
393 UINTN MapLength;\r
394 UINT64 *Prp;\r
395 VOID *PrpListHost;\r
396 UINTN PrpListNo;\r
7b8883c6 397 UINT32 Data;\r
eb290d02
FT		 398\r
399 //\r
400 // check the data fields in Packet parameter.\r
401 //\r
402 if ((This == NULL) || (Packet == NULL)) {\r
403 return EFI_INVALID_PARAMETER;\r
404 }\r
405\r
406 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeResponse == NULL)) {\r
407 return EFI_INVALID_PARAMETER;\r
408 }\r
409\r
410 if (Packet->QueueId != NVME_ADMIN_QUEUE && Packet->QueueId != NVME_IO_QUEUE) {\r
411 return EFI_INVALID_PARAMETER;\r
412 }\r
413\r
414 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
415 PciIo = Private->PciIo;\r
416 MapData = NULL;\r
417 MapMeta = NULL;\r
418 MapPrpList = NULL;\r
419 PrpListHost = NULL;\r
420 PrpListNo = 0;\r
421 Prp = NULL;\r
422 TimerEvent = NULL;\r
423 Status = EFI_SUCCESS;\r
424\r
425 Qid = Packet->QueueId;\r
426 Sq = Private->SqBuffer[Qid] + Private->SqTdbl[Qid].Sqt;\r
427 Cq = Private->CqBuffer[Qid] + Private->CqHdbl[Qid].Cqh;\r
428\r
429 if (Packet->NvmeCmd->Nsid != NamespaceId) {\r
430 return EFI_INVALID_PARAMETER;\r
431 }\r
432\r
433 ZeroMem (Sq, sizeof (NVME_SQ));\r
434 Sq->Opc = Packet->NvmeCmd->Cdw0.Opcode;\r
435 Sq->Fuse = Packet->NvmeCmd->Cdw0.FusedOperation;\r
436 Sq->Cid = Packet->NvmeCmd->Cdw0.Cid;\r
437 Sq->Nsid = Packet->NvmeCmd->Nsid;\r
438\r
439 //\r
440 // Currently we only support PRP for data transfer, SGL is NOT supported.\r
441 //\r
7b8883c6
FT		 442 ASSERT (Sq->Psdt == 0);\r
443 if (Sq->Psdt != 0) {\r
eb290d02
FT		 444 DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r
445 return EFI_UNSUPPORTED;\r
446 }\r
447\r
448 Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r
449 //\r
450 // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r
451 // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r
452 // these two cmds are special which requires their data buffer must support simultaneous access by both the\r
453 // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r
454 //\r
455 if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_OPC) && (Sq->Opc != NVME_ADMIN_CRIOSQ_OPC)) {\r
456 if ((Sq->Opc & BIT0) != 0) {\r
457 Flag = EfiPciIoOperationBusMasterRead;\r
458 } else {\r
459 Flag = EfiPciIoOperationBusMasterWrite;\r
460 }\r
461\r
462 MapLength = Packet->TransferLength;\r
463 Status = PciIo->Map (\r
464 PciIo,\r
465 Flag,\r
466 Packet->TransferBuffer,\r
467 &MapLength,\r
468 &PhyAddr,\r
469 &MapData\r
470 );\r
471 if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r
472 return EFI_OUT_OF_RESOURCES;\r
473 }\r
474\r
475 Sq->Prp[0] = PhyAddr;\r
476 Sq->Prp[1] = 0;\r
477\r
478 MapLength = Packet->MetadataLength;\r
479 if(Packet->MetadataBuffer != NULL) {\r
480 MapLength = Packet->MetadataLength;\r
481 Status = PciIo->Map (\r
482 PciIo,\r
483 Flag,\r
484 Packet->MetadataBuffer,\r
485 &MapLength,\r
486 &PhyAddr,\r
487 &MapMeta\r
488 );\r
489 if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r
490 PciIo->Unmap (\r
491 PciIo,\r
492 MapData\r
493 );\r
494\r
495 return EFI_OUT_OF_RESOURCES;\r
496 }\r
497 Sq->Mptr = PhyAddr;\r
498 }\r
499 }\r
500 //\r
501 // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r
502 // then build a PRP list in the second PRP submission queue entry.\r
503 //\r
504 Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r
505 Bytes = Packet->TransferLength;\r
506\r
507 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r
508 //\r
509 // Create PrpList for remaining data buffer.\r
510 //\r
511 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
512 Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r
513 if (Prp == NULL) {\r
514 goto EXIT;\r
515 }\r
516\r
517 Sq->Prp[1] = (UINT64)(UINTN)Prp;\r
518 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r
519 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
520 }\r
521\r
522 if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r
523 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r
524 }\r
525 if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r
526 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r
527 }\r
528 if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r
529 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r
530 }\r
531 if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r
532 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r
533 }\r
534 if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r
535 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r
536 }\r
537 if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r
538 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r
539 }\r
540\r
541 //\r
542 // Ring the submission queue doorbell.\r
543 //\r
544 Private->SqTdbl[Qid].Sqt ^= 1;\r
7b8883c6 545 Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[Qid]);\r
eb290d02
FT		 546 PciIo->Mem.Write (\r
547 PciIo,\r
548 EfiPciIoWidthUint32,\r
549 NVME_BAR,\r
550 NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd),\r
551 1,\r
7b8883c6 552 &Data\r
eb290d02
FT		 553 );\r
554\r
555 Status = gBS->CreateEvent (\r
556 EVT_TIMER,\r
557 TPL_CALLBACK,\r
558 NULL,\r
559 NULL,\r
560 &TimerEvent\r
561 );\r
562 if (EFI_ERROR (Status)) {\r
563 goto EXIT;\r
564 }\r
565\r
566 Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r
567\r
568 if (EFI_ERROR(Status)) {\r
569 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_DEVICE_ERROR;\r
570 goto EXIT;\r
571 }\r
572\r
573 //\r
574 // Wait for completion queue to get filled in.\r
575 //\r
576 Status = EFI_TIMEOUT;\r
577 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_TIMEOUT_COMMAND;\r
578 while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r
579 if (Cq->Pt != Private->Pt[Qid]) {\r
580 Status = EFI_SUCCESS;\r
581 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_READY;\r
582 break;\r
583 }\r
584 }\r
585\r
586 if ((Private->CqHdbl[Qid].Cqh ^= 1) == 0) {\r
587 Private->Pt[Qid] ^= 1;\r
588 }\r
589\r
590 //\r
591 // Copy the Respose Queue entry for this command to the callers response buffer\r
592 //\r
593 CopyMem(Packet->NvmeResponse, Cq, sizeof(NVM_EXPRESS_RESPONSE));\r
594\r
595 //\r
596 // Dump every completion entry status for debugging.\r
597 //\r
598 DEBUG_CODE_BEGIN();\r
599 NvmeDumpStatus(Cq);\r
600 DEBUG_CODE_END();\r
601\r
7b8883c6 602 Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[Qid]);\r
eb290d02
FT		 603 PciIo->Mem.Write (\r
604 PciIo,\r
605 EfiPciIoWidthUint32,\r
606 NVME_BAR,\r
607 NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd),\r
608 1,\r
7b8883c6 609 &Data\r
eb290d02
FT		 610 );\r
611\r
612EXIT:\r
613 if (MapData != NULL) {\r
614 PciIo->Unmap (\r
615 PciIo,\r
616 MapData\r
617 );\r
618 }\r
619\r
620 if (MapMeta != NULL) {\r
621 PciIo->Unmap (\r
622 PciIo,\r
623 MapMeta\r
624 );\r
625 }\r
626\r
627 if (MapPrpList != NULL) {\r
628 PciIo->Unmap (\r
629 PciIo,\r
630 MapPrpList\r
631 );\r
632 }\r
633\r
634 if (Prp != NULL) {\r
635 PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r
636 }\r
637\r
638 if (TimerEvent != NULL) {\r
639 gBS->CloseEvent (TimerEvent);\r
640 }\r
641 return Status;\r
642}\r
643\r
644/**\r
645 Used to retrieve the list of namespaces defined on an NVM Express controller.\r
646\r
647 The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves a list of namespaces\r
648 defined on an NVM Express controller. If on input a NamespaceID is specified by all 0xFF in the\r
649 namespace buffer, then the first namespace defined on the NVM Express controller is returned in\r
650 NamespaceID, and a status of EFI_SUCCESS is returned.\r
651\r
652 If NamespaceId is a Namespace value that was returned on a previous call to GetNextNamespace(),\r
653 then the next valid NamespaceId for an NVM Express SSD namespace on the NVM Express controller\r
654 is returned in NamespaceId, and EFI_SUCCESS is returned.\r
655\r
656 If Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned on a previous call to\r
657 GetNextNamespace(), then EFI_INVALID_PARAMETER is returned.\r
658\r
659 If NamespaceId is the NamespaceId of the last SSD namespace on the NVM Express controller, then\r
660 EFI_NOT_FOUND is returned\r
661\r
662 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
663 @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r
664 namespace present on the NVM Express controller. On output, a\r
665 pointer to the next NamespaceId of an NVM Express namespace on\r
666 an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r
667 the first NamespaceId for an NVM Express namespace present on an\r
668 NVM Express controller.\r
669 @param[out] NamespaceUuid On output, the UUID associated with the next namespace, if a UUID\r
670 is defined for that NamespaceId, otherwise, zero is returned in\r
671 this parameter. If the caller does not require a UUID, then a NULL\r
672 pointer may be passed.\r
673\r
674 @retval EFI_SUCCESS The NamespaceId of the next Namespace was returned.\r
675 @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r
676 @retval EFI_INVALID_PARAMETER Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned\r
677 on a previous call to GetNextNamespace().\r
678\r
679**/\r
680EFI_STATUS\r
681EFIAPI\r
682NvmExpressGetNextNamespace (\r
683 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
684 IN OUT UINT32 *NamespaceId,\r
685 OUT UINT64 *NamespaceUuid OPTIONAL\r
686 )\r
687{\r
688 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
689 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
690 UINT32 NextNamespaceId;\r
691 EFI_STATUS Status;\r
692\r
693 if ((This == NULL) || (NamespaceId == NULL)) {\r
694 return EFI_INVALID_PARAMETER;\r
695 }\r
696\r
697 NamespaceData = NULL;\r
698 Status = EFI_NOT_FOUND;\r
699\r
700 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
701 //\r
702 // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r
703 //\r
704 if (*NamespaceId == 0xFFFFFFFF) {\r
705 //\r
706 // Start with the first namespace ID\r
707 //\r
708 NextNamespaceId = 1;\r
709 //\r
710 // Allocate buffer for Identify Namespace data.\r
711 //\r
712 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
713\r
714 if (NamespaceData == NULL) {\r
715 return EFI_NOT_FOUND;\r
716 }\r
717\r
718 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
719 if (EFI_ERROR(Status)) {\r
720 goto Done;\r
721 }\r
722\r
723 *NamespaceId = NextNamespaceId;\r
724 if (NamespaceUuid != NULL) {\r
725 *NamespaceUuid = NamespaceData->Eui64;\r
726 }\r
727 } else {\r
728 if (*NamespaceId >= Private->ControllerData->Nn) {\r
729 return EFI_INVALID_PARAMETER;\r
730 }\r
731\r
732 NextNamespaceId = *NamespaceId + 1;\r
733 //\r
734 // Allocate buffer for Identify Namespace data.\r
735 //\r
736 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
737 if (NamespaceData == NULL) {\r
738 return EFI_NOT_FOUND;\r
739 }\r
740\r
741 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
742 if (EFI_ERROR(Status)) {\r
743 goto Done;\r
744 }\r
745\r
746 *NamespaceId = NextNamespaceId;\r
747 if (NamespaceUuid != NULL) {\r
748 *NamespaceUuid = NamespaceData->Eui64;\r
749 }\r
750 }\r
751\r
752Done:\r
753 if (NamespaceData != NULL) {\r
754 FreePool(NamespaceData);\r
755 }\r
756\r
757 return Status;\r
758}\r
759\r
760/**\r
761 Used to translate a device path node to a Namespace ID and Namespace UUID.\r
762\r
763 The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamwspace() function determines the Namespace ID and Namespace UUID\r
764 associated with the NVM Express SSD namespace described by DevicePath. If DevicePath is a device path node type\r
765 that the NVM Express Pass Thru driver supports, then the NVM Express Pass Thru driver will attempt to translate\r
766 the contents DevicePath into a Namespace ID and UUID. If this translation is successful, then that Namespace ID\r
767 and UUID are returned in NamespaceID and NamespaceUUID, and EFI_SUCCESS is returned.\r
768\r
769 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
770 @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r
771 the NVM Express controller.\r
772 @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r
773 @param[out] NamespaceUuid The NVM Express namespace contained in the device path node.\r
774\r
775 @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId and NamespaceUuid.\r
776 @retval EFI_INVALID_PARAMETER If DevicePath, NamespaceId, or NamespaceUuid are NULL, then EFI_INVALID_PARAMETER\r
777 is returned.\r
778 @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r
779 supports, then EFI_UNSUPPORTED is returned.\r
780 @retval EFI_NOT_FOUND If DevicePath is a device path node type that the Nvm Express Pass Thru driver\r
781 supports, but there is not a valid translation from DevicePath to a NamespaceID\r
782 and NamespaceUuid, then EFI_NOT_FOUND is returned.\r
783**/\r
784EFI_STATUS\r
785EFIAPI\r
786NvmExpressGetNamespace (\r
787 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
788 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
789 OUT UINT32 *NamespaceId,\r
790 OUT UINT64 *NamespaceUuid\r
791 )\r
792{\r
793 NVME_NAMESPACE_DEVICE_PATH *Node;\r
794\r
795 if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL) || (NamespaceUuid == NULL)) {\r
796 return EFI_INVALID_PARAMETER;\r
797 }\r
798\r
799 if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r
800 return EFI_UNSUPPORTED;\r
801 }\r
802\r
803 Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r
804\r
805 if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r
806 if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r
807 return EFI_NOT_FOUND;\r
808 }\r
809\r
810 *NamespaceId = Node->NamespaceId;\r
811 *NamespaceUuid = Node->NamespaceUuid;\r
812\r
813 return EFI_SUCCESS;\r
814 } else {\r
815 return EFI_UNSUPPORTED;\r
816 }\r
817}\r
818\r
819/**\r
820 Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r
821\r
822 The NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r
823 path node for the NVM Express namespace specified by NamespaceId.\r
824\r
825 If the namespace device specified by NamespaceId is not valid , then EFI_NOT_FOUND is returned.\r
826\r
827 If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r
828\r
829 If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r
830\r
831 Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r
832 initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r
833\r
834 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
835 @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r
836 allocated and built. Caller must set the NamespaceId to zero if the\r
837 device path node will contain a valid UUID.\r
838 @param[in] NamespaceUuid The NVM Express namespace UUID for which a device path node is to be\r
839 allocated and built. UUID will only be valid of the Namespace ID is zero.\r
840 @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r
841 namespace specified by NamespaceId. This function is responsible for\r
842 allocating the buffer DevicePath with the boot service AllocatePool().\r
843 It is the caller's responsibility to free DevicePath when the caller\r
844 is finished with DevicePath.\r
845 @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r
846 by NamespaceId was allocated and returned in DevicePath.\r
847 @retval EFI_NOT_FOUND The NVM Express namespace specified by NamespaceId does not exist on the\r
848 NVM Express controller.\r
849 @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r
850 @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r
851\r
852**/\r
853EFI_STATUS\r
854EFIAPI\r
855NvmExpressBuildDevicePath (\r
856 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
857 IN UINT32 NamespaceId,\r
858 IN UINT64 NamespaceUuid,\r
859 IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
860 )\r
861{\r
eb290d02
FT		 862 NVME_NAMESPACE_DEVICE_PATH *Node;\r
863\r
864 //\r
865 // Validate parameters\r
866 //\r
867 if ((This == NULL) || (DevicePath == NULL)) {\r
868 return EFI_INVALID_PARAMETER;\r
869 }\r
870\r
eb290d02
FT		 871 if (NamespaceId == 0) {\r
872 return EFI_NOT_FOUND;\r
873 }\r
874\r
875 Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
876\r
877 if (Node == NULL) {\r
878 return EFI_OUT_OF_RESOURCES;\r
879 }\r
880\r
881 Node->Header.Type = MESSAGING_DEVICE_PATH;\r
882 Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r
883 SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
884 Node->NamespaceId = NamespaceId;\r
885 Node->NamespaceUuid = NamespaceUuid;\r
886\r
887 *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r
888 return EFI_SUCCESS;\r
889}\r
890\r
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