[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressPei / NvmExpressPei.h

/** @file\r
  The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
  which follows NVM Express specification at PEI phase.\r
\r
  Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions\r
  of the BSD License which accompanies this distribution.  The\r
  full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _NVM_EXPRESS_PEI_H_\r
#define _NVM_EXPRESS_PEI_H_\r
\r
#include <PiPei.h>\r
\r
#include <IndustryStandard/Nvme.h>\r
\r
#include <Ppi/NvmExpressHostController.h>\r
#include <Ppi/BlockIo.h>\r
#include <Ppi/BlockIo2.h>\r
#include <Ppi/StorageSecurityCommand.h>\r
#include <Ppi/IoMmu.h>\r
#include <Ppi/EndOfPeiPhase.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/TimerLib.h>\r
\r
//\r
// Structure forward declarations\r
//\r
typedef struct _PEI_NVME_NAMESPACE_INFO           PEI_NVME_NAMESPACE_INFO;\r
typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA  PEI_NVME_CONTROLLER_PRIVATE_DATA;\r
\r
#include "NvmExpressPeiHci.h"\r
#include "NvmExpressPeiPassThru.h"\r
#include "NvmExpressPeiBlockIo.h"\r
#include "NvmExpressPeiStorageSecurity.h"\r
\r
//\r
// NVME PEI driver implementation related definitions\r
//\r
#define NVME_MAX_QUEUES                               2     // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ\r
#define NVME_ASQ_SIZE                                 1     // Number of admin submission queue entries, which is 0-based\r
#define NVME_ACQ_SIZE                                 1     // Number of admin completion queue entries, which is 0-based\r
#define NVME_CSQ_SIZE                                 63    // Number of I/O submission queue entries, which is 0-based\r
#define NVME_CCQ_SIZE                                 63    // Number of I/O completion queue entries, which is 0-based\r
#define NVME_PRP_SIZE                                 (8)   // Pages of PRP list\r
\r
#define NVME_MEM_MAX_PAGES                                           \\r
  (                                                                  \\r
  1                                         /* ASQ */             +  \\r
  1                                         /* ACQ */             +  \\r
  1                                         /* SQs */             +  \\r
  1                                         /* CQs */             +  \\r
  NVME_PRP_SIZE)                            /* PRPs */\r
\r
#define NVME_ADMIN_QUEUE                              0x00\r
#define NVME_IO_QUEUE                                 0x01\r
#define NVME_GENERIC_TIMEOUT                          5000000   // Generic PassThru command timeout value, in us unit\r
#define NVME_POLL_INTERVAL                            100       // Poll interval for PassThru command, in us unit\r
\r
//\r
// Nvme namespace data structure.\r
//\r
struct _PEI_NVME_NAMESPACE_INFO {\r
  UINT32                                    NamespaceId;\r
  UINT64                                    NamespaceUuid;\r
  EFI_PEI_BLOCK_IO2_MEDIA                   Media;\r
\r
  PEI_NVME_CONTROLLER_PRIVATE_DATA          *Controller;\r
};\r
\r
//\r
// Unique signature for private data structure.\r
//\r
#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE    SIGNATURE_32 ('N','V','P','C')\r
\r
//\r
// Nvme controller private data structure.\r
//\r
struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {\r
  UINT32                                    Signature;\r
  UINTN                                     MmioBase;\r
  UINTN                                     DevicePathLength;\r
  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;\r
\r
  EFI_PEI_RECOVERY_BLOCK_IO_PPI             BlkIoPpi;\r
  EFI_PEI_RECOVERY_BLOCK_IO2_PPI            BlkIo2Ppi;\r
  EDKII_PEI_STORAGE_SECURITY_CMD_PPI        StorageSecurityPpi;\r
  EFI_PEI_PPI_DESCRIPTOR                    BlkIoPpiList;\r
  EFI_PEI_PPI_DESCRIPTOR                    BlkIo2PpiList;\r
  EFI_PEI_PPI_DESCRIPTOR                    StorageSecurityPpiList;\r
  EFI_PEI_NOTIFY_DESCRIPTOR                 EndOfPeiNotifyList;\r
\r
  //\r
  // Pointer to identify controller data\r
  //\r
  NVME_ADMIN_CONTROLLER_DATA                *ControllerData;\r
\r
  //\r
  // (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer\r
  // 1st 4kB boundary is the start of the admin submission queue\r
  // 2nd 4kB boundary is the start of the admin completion queue\r
  // 3rd 4kB boundary is the start of I/O submission queue\r
  // 4th 4kB boundary is the start of I/O completion queue\r
  // 5th 4kB boundary is the start of PRP list buffers\r
  //\r
  VOID                                      *Buffer;\r
  VOID                                      *BufferMapping;\r
\r
  //\r
  // Pointers to 4kB aligned submission & completion queues\r
  //\r
  NVME_SQ                                   *SqBuffer[NVME_MAX_QUEUES];\r
  NVME_CQ                                   *CqBuffer[NVME_MAX_QUEUES];\r
\r
  //\r
  // Submission and completion queue indices\r
  //\r
  NVME_SQTDBL                               SqTdbl[NVME_MAX_QUEUES];\r
  NVME_CQHDBL                               CqHdbl[NVME_MAX_QUEUES];\r
\r
  UINT8                                     Pt[NVME_MAX_QUEUES];\r
  UINT16                                    Cid[NVME_MAX_QUEUES];\r
\r
  //\r
  // Nvme controller capabilities\r
  //\r
  NVME_CAP                                  Cap;\r
\r
  //\r
  // Namespaces information on the controller\r
  //\r
  UINT32                                    ActiveNamespaceNum;\r
  PEI_NVME_NAMESPACE_INFO                   *NamespaceInfo;\r
};\r
\r
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a)               \\r
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a)              \\r
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a)    \\r
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a)              \\r
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
\r
\r
//\r
// Internal functions\r
//\r
\r
/**\r
  Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
  OperationBusMasterCommonBuffer64 mapping.\r
\r
  @param  Pages                 The number of pages to allocate.\r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
IoMmuAllocateBuffer (\r
  IN UINTN                  Pages,\r
  OUT VOID                  **HostAddress,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  @param  Pages                 The number of pages to free.\r
  @param  HostAddress           The base system memory address of the allocated range.\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with AllocateBuffer().\r
\r
**/\r
EFI_STATUS\r
IoMmuFreeBuffer (\r
  IN UINTN                  Pages,\r
  IN VOID                   *HostAddress,\r
  IN VOID                   *Mapping\r
  );\r
\r
/**\r
  Provides the controller-specific addresses required to access system memory from a\r
  DMA bus master.\r
\r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the PCI controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
\r
**/\r
EFI_STATUS\r
IoMmuMap (\r
  IN  EDKII_IOMMU_OPERATION Operation,\r
  IN VOID                   *HostAddress,\r
  IN  OUT UINTN             *NumberOfBytes,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
**/\r
EFI_STATUS\r
IoMmuUnmap (\r
  IN VOID                  *Mapping\r
  );\r
\r
/**\r
  One notified function to cleanup the allocated resources at the end of PEI.\r
\r
  @param[in] PeiServices         Pointer to PEI Services Table.\r
  @param[in] NotifyDescriptor    Pointer to the descriptor for the Notification\r
                                 event that caused this function to execute.\r
  @param[in] Ppi                 Pointer to the PPI data associated with this function.\r
\r
  @retval     EFI_SUCCESS  The function completes successfully\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
NvmePeimEndOfPei (\r
  IN EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  );\r
\r
/**\r
  Check the validity of the device path of a NVM Express host controller.\r
\r
  @param[in] DevicePath          A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
                                 structure.\r
  @param[in] DevicePathLength    The length of the device path.\r
\r
  @retval EFI_SUCCESS              The device path is valid.\r
  @retval EFI_INVALID_PARAMETER    The device path is invalid.\r
\r
**/\r
EFI_STATUS\r
NvmeIsHcDevicePathValid (\r
  IN EFI_DEVICE_PATH_PROTOCOL    *DevicePath,\r
  IN UINTN                       DevicePathLength\r
  );\r
\r
/**\r
  Build the device path for an Nvm Express device with given namespace identifier\r
  and namespace extended unique identifier.\r
\r
  @param[in]  Private              A pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA\r
                                   data structure.\r
  @param[in]  NamespaceId          The given namespace identifier.\r
  @param[in]  NamespaceUuid        The given namespace extended unique identifier.\r
  @param[out] DevicePathLength     The length of the device path in bytes specified\r
                                   by DevicePath.\r
  @param[out] DevicePath           The device path of Nvm Express device.\r
\r
  @retval EFI_SUCCESS              The operation succeeds.\r
  @retval EFI_INVALID_PARAMETER    The parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES     The operation fails due to lack of resources.\r
\r
**/\r
EFI_STATUS\r
NvmeBuildDevicePath (\r
  IN  PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private,\r
  IN  UINT32                              NamespaceId,\r
  IN  UINT64                              NamespaceUuid,\r
  OUT UINTN                               *DevicePathLength,\r
  OUT EFI_DEVICE_PATH_PROTOCOL            **DevicePath\r
  );\r
\r
#endif\r
Commit	Line	Data
b8b69433 HW	1	/** @file\r
	2	The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
	3	which follows NVM Express specification at PEI phase.\r
	4	\r
4104423a	5	Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
b8b69433 HW	6	\r
	7	This program and the accompanying materials\r
	8	are licensed and made available under the terms and conditions\r
	9	of the BSD License which accompanies this distribution. The\r
	10	full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef _NVM_EXPRESS_PEI_H_\r
	19	#define _NVM_EXPRESS_PEI_H_\r
	20	\r
	21	#include <PiPei.h>\r
	22	\r
	23	#include <IndustryStandard/Nvme.h>\r
	24	\r
	25	#include <Ppi/NvmExpressHostController.h>\r
	26	#include <Ppi/BlockIo.h>\r
	27	#include <Ppi/BlockIo2.h>\r
2e15b750	28	#include <Ppi/StorageSecurityCommand.h>\r
b8b69433 HW	29	#include <Ppi/IoMmu.h>\r
	30	#include <Ppi/EndOfPeiPhase.h>\r
	31	\r
	32	#include <Library/DebugLib.h>\r
	33	#include <Library/PeiServicesLib.h>\r
	34	#include <Library/MemoryAllocationLib.h>\r
	35	#include <Library/BaseMemoryLib.h>\r
	36	#include <Library/IoLib.h>\r
b8b69433 HW	37	#include <Library/TimerLib.h>\r
	38	\r
	39	//\r
	40	// Structure forward declarations\r
	41	//\r
	42	typedef struct _PEI_NVME_NAMESPACE_INFO PEI_NVME_NAMESPACE_INFO;\r
	43	typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DATA;\r
	44	\r
	45	#include "NvmExpressPeiHci.h"\r
	46	#include "NvmExpressPeiPassThru.h"\r
	47	#include "NvmExpressPeiBlockIo.h"\r
2e15b750	48	#include "NvmExpressPeiStorageSecurity.h"\r
b8b69433 HW	49	\r
	50	//\r
	51	// NVME PEI driver implementation related definitions\r
	52	//\r
	53	#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ\r
	54	#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based\r
	55	#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based\r
	56	#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based\r
	57	#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based\r
	58	#define NVME_PRP_SIZE (8) // Pages of PRP list\r
	59	\r
	60	#define NVME_MEM_MAX_PAGES \\r
	61	( \\r
	62	1 /* ASQ */ + \\r
	63	1 /* ACQ */ + \\r
	64	1 /* SQs */ + \\r
	65	1 /* CQs */ + \\r
	66	NVME_PRP_SIZE) /* PRPs */\r
	67	\r
	68	#define NVME_ADMIN_QUEUE 0x00\r
	69	#define NVME_IO_QUEUE 0x01\r
	70	#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit\r
	71	#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit\r
	72	\r
	73	//\r
	74	// Nvme namespace data structure.\r
	75	//\r
	76	struct _PEI_NVME_NAMESPACE_INFO {\r
	77	UINT32 NamespaceId;\r
	78	UINT64 NamespaceUuid;\r
	79	EFI_PEI_BLOCK_IO2_MEDIA Media;\r
	80	\r
	81	PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;\r
	82	};\r
	83	\r
	84	//\r
	85	// Unique signature for private data structure.\r
	86	//\r
	87	#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')\r
	88	\r
	89	//\r
	90	// Nvme controller private data structure.\r
	91	//\r
	92	struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {\r
	93	UINT32 Signature;\r
	94	UINTN MmioBase;\r
2e15b750 HW	95	UINTN DevicePathLength;\r
	96	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	97	\r
b8b69433 HW	98	EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;\r
b8b69433 HW	99	EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;\r
2e15b750	100	EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;\r
b8b69433 HW	101	EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;\r
b8b69433 HW	102	EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;\r
2e15b750	103	EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;\r
b8b69433 HW	104	EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
	105	\r
	106	//\r
	107	// Pointer to identify controller data\r
	108	//\r
	109	NVME_ADMIN_CONTROLLER_DATA *ControllerData;\r
	110	\r
	111	//\r
	112	// (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer\r
	113	// 1st 4kB boundary is the start of the admin submission queue\r
	114	// 2nd 4kB boundary is the start of the admin completion queue\r
	115	// 3rd 4kB boundary is the start of I/O submission queue\r
	116	// 4th 4kB boundary is the start of I/O completion queue\r
	117	// 5th 4kB boundary is the start of PRP list buffers\r
	118	//\r
	119	VOID *Buffer;\r
	120	VOID *BufferMapping;\r
	121	\r
	122	//\r
	123	// Pointers to 4kB aligned submission & completion queues\r
	124	//\r
	125	NVME_SQ *SqBuffer[NVME_MAX_QUEUES];\r
	126	NVME_CQ *CqBuffer[NVME_MAX_QUEUES];\r
	127	\r
	128	//\r
	129	// Submission and completion queue indices\r
	130	//\r
	131	NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];\r
	132	NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];\r
	133	\r
	134	UINT8 Pt[NVME_MAX_QUEUES];\r
	135	UINT16 Cid[NVME_MAX_QUEUES];\r
	136	\r
	137	//\r
	138	// Nvme controller capabilities\r
	139	//\r
	140	NVME_CAP Cap;\r
	141	\r
	142	//\r
	143	// Namespaces information on the controller\r
	144	//\r
	145	UINT32 ActiveNamespaceNum;\r
	146	PEI_NVME_NAMESPACE_INFO *NamespaceInfo;\r
	147	};\r
	148	\r
2e15b750	149	#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \\r
b8b69433	150	CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
2e15b750	151	#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \\r
b8b69433	152	CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
2e15b750 HW	153	#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a) \\r
	154	CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
	155	#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \\r
b8b69433 HW	156	CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
	157	\r
	158	\r
4104423a HW	159	//\r
	160	// Internal functions\r
	161	//\r
b8b69433 HW	162	\r
	163	/**\r
	164	Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
	165	OperationBusMasterCommonBuffer64 mapping.\r
	166	\r
	167	@param Pages The number of pages to allocate.\r
	168	@param HostAddress A pointer to store the base system memory address of the\r
	169	allocated range.\r
	170	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	171	access the hosts HostAddress.\r
	172	@param Mapping A resulting value to pass to Unmap().\r
	173	\r
	174	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	175	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
	176	MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
	177	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	178	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
	179	\r
	180	**/\r
	181	EFI_STATUS\r
	182	IoMmuAllocateBuffer (\r
	183	IN UINTN Pages,\r
	184	OUT VOID **HostAddress,\r
	185	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	186	OUT VOID **Mapping\r
	187	);\r
	188	\r
	189	/**\r
	190	Frees memory that was allocated with AllocateBuffer().\r
	191	\r
	192	@param Pages The number of pages to free.\r
	193	@param HostAddress The base system memory address of the allocated range.\r
	194	@param Mapping The mapping value returned from Map().\r
	195	\r
	196	@retval EFI_SUCCESS The requested memory pages were freed.\r
	197	@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
	198	was not allocated with AllocateBuffer().\r
	199	\r
	200	**/\r
	201	EFI_STATUS\r
	202	IoMmuFreeBuffer (\r
	203	IN UINTN Pages,\r
	204	IN VOID *HostAddress,\r
	205	IN VOID *Mapping\r
	206	);\r
	207	\r
	208	/**\r
	209	Provides the controller-specific addresses required to access system memory from a\r
	210	DMA bus master.\r
	211	\r
	212	@param Operation Indicates if the bus master is going to read or write to system memory.\r
	213	@param HostAddress The system memory address to map to the PCI controller.\r
	214	@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
	215	that were mapped.\r
	216	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	217	access the hosts HostAddress.\r
	218	@param Mapping A resulting value to pass to Unmap().\r
	219	\r
	220	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
	221	@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
	222	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	223	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	224	@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
	225	\r
226	**/\r
227	EFI_STATUS\r
228	IoMmuMap (\r
229	IN EDKII_IOMMU_OPERATION Operation,\r
230	IN VOID *HostAddress,\r
231	IN OUT UINTN *NumberOfBytes,\r
232	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
233	OUT VOID **Mapping\r
234	);\r
235	\r
236	/**\r
237	Completes the Map() operation and releases any corresponding resources.\r
238	\r
239	@param Mapping The mapping value returned from Map().\r
240	\r
241	@retval EFI_SUCCESS The range was unmapped.\r
242	@retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
243	@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
244	**/\r
245	EFI_STATUS\r
246	IoMmuUnmap (\r
247	IN VOID *Mapping\r
248	);\r
249	\r
250	/**\r
251	One notified function to cleanup the allocated resources at the end of PEI.\r
252	\r
253	@param[in] PeiServices Pointer to PEI Services Table.\r
254	@param[in] NotifyDescriptor Pointer to the descriptor for the Notification\r
255	event that caused this function to execute.\r
256	@param[in] Ppi Pointer to the PPI data associated with this function.\r
257	\r
258	@retval EFI_SUCCESS The function completes successfully\r
259	\r
260	**/\r
261	EFI_STATUS\r
262	EFIAPI\r
263	NvmePeimEndOfPei (\r
264	IN EFI_PEI_SERVICES **PeiServices,\r
265	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
266	IN VOID *Ppi\r
267	);\r
268	\r
2e15b750 HW	269	/**\r
	270	Check the validity of the device path of a NVM Express host controller.\r
	271	\r
	272	@param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL\r
	273	structure.\r
	274	@param[in] DevicePathLength The length of the device path.\r
	275	\r
	276	@retval EFI_SUCCESS The device path is valid.\r
	277	@retval EFI_INVALID_PARAMETER The device path is invalid.\r
	278	\r
	279	**/\r
	280	EFI_STATUS\r
	281	NvmeIsHcDevicePathValid (\r
	282	IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
	283	IN UINTN DevicePathLength\r
	284	);\r
	285	\r
	286	/**\r
	287	Build the device path for an Nvm Express device with given namespace identifier\r
	288	and namespace extended unique identifier.\r
	289	\r
	290	@param[in] Private A pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA\r
	291	data structure.\r
	292	@param[in] NamespaceId The given namespace identifier.\r
	293	@param[in] NamespaceUuid The given namespace extended unique identifier.\r
	294	@param[out] DevicePathLength The length of the device path in bytes specified\r
	295	by DevicePath.\r
	296	@param[out] DevicePath The device path of Nvm Express device.\r
	297	\r
	298	@retval EFI_SUCCESS The operation succeeds.\r
	299	@retval EFI_INVALID_PARAMETER The parameters are invalid.\r
	300	@retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.\r
	301	\r
	302	**/\r
	303	EFI_STATUS\r
	304	NvmeBuildDevicePath (\r
	305	IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
	306	IN UINT32 NamespaceId,\r
	307	IN UINT64 NamespaceUuid,\r
	308	OUT UINTN *DevicePathLength,\r
	309	OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
	310	);\r
	311	\r
b8b69433	312	#endif\r