[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressPei / NvmExpressPei.h

/** @file\r
  The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
  which follows NVM Express specification at PEI phase.\r
\r
  Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions\r
  of the BSD License which accompanies this distribution.  The\r
  full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _NVM_EXPRESS_PEI_H_\r
#define _NVM_EXPRESS_PEI_H_\r
\r
#include <PiPei.h>\r
\r
#include <IndustryStandard/Nvme.h>\r
\r
#include <Ppi/NvmExpressHostController.h>\r
#include <Ppi/BlockIo.h>\r
#include <Ppi/BlockIo2.h>\r
#include <Ppi/IoMmu.h>\r
#include <Ppi/EndOfPeiPhase.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/TimerLib.h>\r
\r
//\r
// Structure forward declarations\r
//\r
typedef struct _PEI_NVME_NAMESPACE_INFO           PEI_NVME_NAMESPACE_INFO;\r
typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA  PEI_NVME_CONTROLLER_PRIVATE_DATA;\r
\r
#include "NvmExpressPeiHci.h"\r
#include "NvmExpressPeiPassThru.h"\r
#include "NvmExpressPeiBlockIo.h"\r
\r
//\r
// NVME PEI driver implementation related definitions\r
//\r
#define NVME_MAX_QUEUES                               2     // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ\r
#define NVME_ASQ_SIZE                                 1     // Number of admin submission queue entries, which is 0-based\r
#define NVME_ACQ_SIZE                                 1     // Number of admin completion queue entries, which is 0-based\r
#define NVME_CSQ_SIZE                                 63    // Number of I/O submission queue entries, which is 0-based\r
#define NVME_CCQ_SIZE                                 63    // Number of I/O completion queue entries, which is 0-based\r
#define NVME_PRP_SIZE                                 (8)   // Pages of PRP list\r
\r
#define NVME_MEM_MAX_PAGES                                           \\r
  (                                                                  \\r
  1                                         /* ASQ */             +  \\r
  1                                         /* ACQ */             +  \\r
  1                                         /* SQs */             +  \\r
  1                                         /* CQs */             +  \\r
  NVME_PRP_SIZE)                            /* PRPs */\r
\r
#define NVME_ADMIN_QUEUE                              0x00\r
#define NVME_IO_QUEUE                                 0x01\r
#define NVME_GENERIC_TIMEOUT                          5000000   // Generic PassThru command timeout value, in us unit\r
#define NVME_POLL_INTERVAL                            100       // Poll interval for PassThru command, in us unit\r
\r
//\r
// Nvme namespace data structure.\r
//\r
struct _PEI_NVME_NAMESPACE_INFO {\r
  UINT32                                    NamespaceId;\r
  UINT64                                    NamespaceUuid;\r
  EFI_PEI_BLOCK_IO2_MEDIA                   Media;\r
\r
  PEI_NVME_CONTROLLER_PRIVATE_DATA          *Controller;\r
};\r
\r
//\r
// Unique signature for private data structure.\r
//\r
#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE    SIGNATURE_32 ('N','V','P','C')\r
\r
//\r
// Nvme controller private data structure.\r
//\r
struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {\r
  UINT32                                    Signature;\r
  UINTN                                     MmioBase;\r
  EFI_PEI_RECOVERY_BLOCK_IO_PPI             BlkIoPpi;\r
  EFI_PEI_RECOVERY_BLOCK_IO2_PPI            BlkIo2Ppi;\r
  EFI_PEI_PPI_DESCRIPTOR                    BlkIoPpiList;\r
  EFI_PEI_PPI_DESCRIPTOR                    BlkIo2PpiList;\r
  EFI_PEI_NOTIFY_DESCRIPTOR                 EndOfPeiNotifyList;\r
\r
  //\r
  // Pointer to identify controller data\r
  //\r
  NVME_ADMIN_CONTROLLER_DATA                *ControllerData;\r
\r
  //\r
  // (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer\r
  // 1st 4kB boundary is the start of the admin submission queue\r
  // 2nd 4kB boundary is the start of the admin completion queue\r
  // 3rd 4kB boundary is the start of I/O submission queue\r
  // 4th 4kB boundary is the start of I/O completion queue\r
  // 5th 4kB boundary is the start of PRP list buffers\r
  //\r
  VOID                                      *Buffer;\r
  VOID                                      *BufferMapping;\r
\r
  //\r
  // Pointers to 4kB aligned submission & completion queues\r
  //\r
  NVME_SQ                                   *SqBuffer[NVME_MAX_QUEUES];\r
  NVME_CQ                                   *CqBuffer[NVME_MAX_QUEUES];\r
\r
  //\r
  // Submission and completion queue indices\r
  //\r
  NVME_SQTDBL                               SqTdbl[NVME_MAX_QUEUES];\r
  NVME_CQHDBL                               CqHdbl[NVME_MAX_QUEUES];\r
\r
  UINT8                                     Pt[NVME_MAX_QUEUES];\r
  UINT16                                    Cid[NVME_MAX_QUEUES];\r
\r
  //\r
  // Nvme controller capabilities\r
  //\r
  NVME_CAP                                  Cap;\r
\r
  //\r
  // Namespaces information on the controller\r
  //\r
  UINT32                                    ActiveNamespaceNum;\r
  PEI_NVME_NAMESPACE_INFO                   *NamespaceInfo;\r
};\r
\r
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a)     \\r
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a)    \\r
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a)    \\r
  CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
\r
\r
/**\r
  Initialize IOMMU.\r
**/\r
VOID\r
IoMmuInit (\r
  VOID\r
  );\r
\r
/**\r
  Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
  OperationBusMasterCommonBuffer64 mapping.\r
\r
  @param  Pages                 The number of pages to allocate.\r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
IoMmuAllocateBuffer (\r
  IN UINTN                  Pages,\r
  OUT VOID                  **HostAddress,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  @param  Pages                 The number of pages to free.\r
  @param  HostAddress           The base system memory address of the allocated range.\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with AllocateBuffer().\r
\r
**/\r
EFI_STATUS\r
IoMmuFreeBuffer (\r
  IN UINTN                  Pages,\r
  IN VOID                   *HostAddress,\r
  IN VOID                   *Mapping\r
  );\r
\r
/**\r
  Provides the controller-specific addresses required to access system memory from a\r
  DMA bus master.\r
\r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the PCI controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
\r
**/\r
EFI_STATUS\r
IoMmuMap (\r
  IN  EDKII_IOMMU_OPERATION Operation,\r
  IN VOID                   *HostAddress,\r
  IN  OUT UINTN             *NumberOfBytes,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
**/\r
EFI_STATUS\r
IoMmuUnmap (\r
  IN VOID                  *Mapping\r
  );\r
\r
/**\r
  One notified function to cleanup the allocated resources at the end of PEI.\r
\r
  @param[in] PeiServices         Pointer to PEI Services Table.\r
  @param[in] NotifyDescriptor    Pointer to the descriptor for the Notification\r
                                 event that caused this function to execute.\r
  @param[in] Ppi                 Pointer to the PPI data associated with this function.\r
\r
  @retval     EFI_SUCCESS  The function completes successfully\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
NvmePeimEndOfPei (\r
  IN EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  );\r
\r
#endif\r
Commit	Line	Data
b8b69433 HW	1	/** @file\r
	2	The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
	3	which follows NVM Express specification at PEI phase.\r
	4	\r
	5	Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
	6	\r
	7	This program and the accompanying materials\r
	8	are licensed and made available under the terms and conditions\r
	9	of the BSD License which accompanies this distribution. The\r
	10	full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef _NVM_EXPRESS_PEI_H_\r
	19	#define _NVM_EXPRESS_PEI_H_\r
	20	\r
	21	#include <PiPei.h>\r
	22	\r
	23	#include <IndustryStandard/Nvme.h>\r
	24	\r
	25	#include <Ppi/NvmExpressHostController.h>\r
	26	#include <Ppi/BlockIo.h>\r
	27	#include <Ppi/BlockIo2.h>\r
	28	#include <Ppi/IoMmu.h>\r
	29	#include <Ppi/EndOfPeiPhase.h>\r
	30	\r
	31	#include <Library/DebugLib.h>\r
	32	#include <Library/PeiServicesLib.h>\r
	33	#include <Library/MemoryAllocationLib.h>\r
	34	#include <Library/BaseMemoryLib.h>\r
	35	#include <Library/IoLib.h>\r
	36	#include <Library/PciLib.h>\r
	37	#include <Library/TimerLib.h>\r
	38	\r
	39	//\r
	40	// Structure forward declarations\r
	41	//\r
	42	typedef struct _PEI_NVME_NAMESPACE_INFO PEI_NVME_NAMESPACE_INFO;\r
	43	typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DATA;\r
	44	\r
	45	#include "NvmExpressPeiHci.h"\r
	46	#include "NvmExpressPeiPassThru.h"\r
	47	#include "NvmExpressPeiBlockIo.h"\r
	48	\r
	49	//\r
	50	// NVME PEI driver implementation related definitions\r
	51	//\r
	52	#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ\r
	53	#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based\r
	54	#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based\r
	55	#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based\r
	56	#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based\r
	57	#define NVME_PRP_SIZE (8) // Pages of PRP list\r
	58	\r
	59	#define NVME_MEM_MAX_PAGES \\r
	60	( \\r
	61	1 /* ASQ */ + \\r
	62	1 /* ACQ */ + \\r
	63	1 /* SQs */ + \\r
	64	1 /* CQs */ + \\r
65	NVME_PRP_SIZE) /* PRPs */\r
66	\r
67	#define NVME_ADMIN_QUEUE 0x00\r
68	#define NVME_IO_QUEUE 0x01\r
69	#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit\r
70	#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit\r
71	\r
72	//\r
73	// Nvme namespace data structure.\r
74	//\r
75	struct _PEI_NVME_NAMESPACE_INFO {\r
76	UINT32 NamespaceId;\r
77	UINT64 NamespaceUuid;\r
78	EFI_PEI_BLOCK_IO2_MEDIA Media;\r
79	\r
80	PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;\r
81	};\r
82	\r
83	//\r
84	// Unique signature for private data structure.\r
85	//\r
86	#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')\r
87	\r
88	//\r
89	// Nvme controller private data structure.\r
90	//\r
91	struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {\r
92	UINT32 Signature;\r
93	UINTN MmioBase;\r
94	EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;\r
95	EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;\r
96	EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;\r
97	EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;\r
98	EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
99	\r
100	//\r
101	// Pointer to identify controller data\r
102	//\r
103	NVME_ADMIN_CONTROLLER_DATA *ControllerData;\r
104	\r
105	//\r
106	// (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer\r
107	// 1st 4kB boundary is the start of the admin submission queue\r
108	// 2nd 4kB boundary is the start of the admin completion queue\r
109	// 3rd 4kB boundary is the start of I/O submission queue\r
110	// 4th 4kB boundary is the start of I/O completion queue\r
111	// 5th 4kB boundary is the start of PRP list buffers\r
112	//\r
113	VOID *Buffer;\r
114	VOID *BufferMapping;\r
115	\r
116	//\r
117	// Pointers to 4kB aligned submission & completion queues\r
118	//\r
119	NVME_SQ *SqBuffer[NVME_MAX_QUEUES];\r
120	NVME_CQ *CqBuffer[NVME_MAX_QUEUES];\r
121	\r
122	//\r
123	// Submission and completion queue indices\r
124	//\r
125	NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];\r
126	NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];\r
127	\r
128	UINT8 Pt[NVME_MAX_QUEUES];\r
129	UINT16 Cid[NVME_MAX_QUEUES];\r
130	\r
131	//\r
132	// Nvme controller capabilities\r
133	//\r
134	NVME_CAP Cap;\r
135	\r
136	//\r
137	// Namespaces information on the controller\r
138	//\r
139	UINT32 ActiveNamespaceNum;\r
140	PEI_NVME_NAMESPACE_INFO *NamespaceInfo;\r
141	};\r
142	\r
143	#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \\r
144	CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
145	#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \\r
146	CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
147	#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \\r
148	CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
149	\r
150	\r
151	/**\r
152	Initialize IOMMU.\r
153	**/\r
154	VOID\r
155	IoMmuInit (\r
156	VOID\r
157	);\r
158	\r
159	/**\r
160	Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
161	OperationBusMasterCommonBuffer64 mapping.\r
162	\r
163	@param Pages The number of pages to allocate.\r
164	@param HostAddress A pointer to store the base system memory address of the\r
165	allocated range.\r
166	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
167	access the hosts HostAddress.\r
168	@param Mapping A resulting value to pass to Unmap().\r
169	\r
170	@retval EFI_SUCCESS The requested memory pages were allocated.\r
171	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
172	MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
173	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
174	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
175	\r
176	**/\r
177	EFI_STATUS\r
178	IoMmuAllocateBuffer (\r
179	IN UINTN Pages,\r
180	OUT VOID **HostAddress,\r
181	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
182	OUT VOID **Mapping\r
183	);\r
184	\r
185	/**\r
186	Frees memory that was allocated with AllocateBuffer().\r
187	\r
188	@param Pages The number of pages to free.\r
189	@param HostAddress The base system memory address of the allocated range.\r
190	@param Mapping The mapping value returned from Map().\r
191	\r
192	@retval EFI_SUCCESS The requested memory pages were freed.\r
193	@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
194	was not allocated with AllocateBuffer().\r
195	\r
196	**/\r
197	EFI_STATUS\r
198	IoMmuFreeBuffer (\r
199	IN UINTN Pages,\r
200	IN VOID *HostAddress,\r
201	IN VOID *Mapping\r
202	);\r
203	\r
204	/**\r
205	Provides the controller-specific addresses required to access system memory from a\r
206	DMA bus master.\r
207	\r
208	@param Operation Indicates if the bus master is going to read or write to system memory.\r
209	@param HostAddress The system memory address to map to the PCI controller.\r
210	@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
211	that were mapped.\r
212	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
213	access the hosts HostAddress.\r
214	@param Mapping A resulting value to pass to Unmap().\r
215	\r
216	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
217	@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
218	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
219	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
220	@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
221	\r
222	**/\r
223	EFI_STATUS\r
224	IoMmuMap (\r
225	IN EDKII_IOMMU_OPERATION Operation,\r
226	IN VOID *HostAddress,\r
227	IN OUT UINTN *NumberOfBytes,\r
228	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
229	OUT VOID **Mapping\r
230	);\r
231	\r
232	/**\r
233	Completes the Map() operation and releases any corresponding resources.\r
234	\r
235	@param Mapping The mapping value returned from Map().\r
236	\r
237	@retval EFI_SUCCESS The range was unmapped.\r
238	@retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
239	@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
240	**/\r
241	EFI_STATUS\r
242	IoMmuUnmap (\r
243	IN VOID *Mapping\r
244	);\r
245	\r
246	/**\r
247	One notified function to cleanup the allocated resources at the end of PEI.\r
248	\r
249	@param[in] PeiServices Pointer to PEI Services Table.\r
250	@param[in] NotifyDescriptor Pointer to the descriptor for the Notification\r
251	event that caused this function to execute.\r
252	@param[in] Ppi Pointer to the PPI data associated with this function.\r
253	\r
254	@retval EFI_SUCCESS The function completes successfully\r
255	\r
256	**/\r
257	EFI_STATUS\r
258	EFIAPI\r
259	NvmePeimEndOfPei (\r
260	IN EFI_PEI_SERVICES **PeiServices,\r
261	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
262	IN VOID *Ppi\r
263	);\r
264	\r
265	#endif\r