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9060e3ec 1/** @file\r
2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
3\r
724f26a9 4Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
25a26646 5(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
cd5ebaa0 6This program and the accompanying materials\r
9060e3ec 7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "PciBus.h"\r
17\r
18/**\r
19 This routine is used to enumerate entire pci bus system\r
20 in a given platform.\r
21\r
22 @param Controller Parent controller handle.\r
23\r
24 @retval EFI_SUCCESS PCI enumeration finished successfully.\r
25 @retval other Some error occurred when enumerating the pci bus system.\r
26\r
27**/\r
28EFI_STATUS\r
29PciEnumerator (\r
30 IN EFI_HANDLE Controller\r
31 )\r
32{\r
9060e3ec 33 EFI_HANDLE HostBridgeHandle;\r
34 EFI_STATUS Status;\r
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
37\r
38 //\r
39 // If PCI bus has already done the full enumeration, never do it again\r
40 //\r
41 if (!gFullEnumeration) {\r
42 return PciEnumeratorLight (Controller);\r
43 }\r
44\r
45 //\r
46 // Get the rootbridge Io protocol to find the host bridge handle\r
47 //\r
48 Status = gBS->OpenProtocol (\r
49 Controller,\r
50 &gEfiPciRootBridgeIoProtocolGuid,\r
51 (VOID **) &PciRootBridgeIo,\r
52 gPciBusDriverBinding.DriverBindingHandle,\r
53 Controller,\r
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
55 );\r
56\r
57 if (EFI_ERROR (Status)) {\r
58 return Status;\r
59 }\r
60\r
61 //\r
62 // Get the host bridge handle\r
63 //\r
64 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
65\r
66 //\r
67 // Get the pci host bridge resource allocation protocol\r
68 //\r
69 Status = gBS->OpenProtocol (\r
70 HostBridgeHandle,\r
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
72 (VOID **) &PciResAlloc,\r
73 gPciBusDriverBinding.DriverBindingHandle,\r
74 Controller,\r
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
76 );\r
77\r
78 if (EFI_ERROR (Status)) {\r
79 return Status;\r
80 }\r
81\r
82 //\r
83 // Notify the pci bus enumeration is about to begin\r
84 //\r
ea8d98fa
OM		 85 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);\r
86\r
87 if (EFI_ERROR (Status)) {\r
88 return Status;\r
89 }\r
9060e3ec 90\r
91 //\r
92 // Start the bus allocation phase\r
93 //\r
94 Status = PciHostBridgeEnumerator (PciResAlloc);\r
95\r
96 if (EFI_ERROR (Status)) {\r
97 return Status;\r
98 }\r
99\r
100 //\r
101 // Submit the resource request\r
102 //\r
103 Status = PciHostBridgeResourceAllocator (PciResAlloc);\r
104\r
105 if (EFI_ERROR (Status)) {\r
106 return Status;\r
107 }\r
108\r
109 //\r
110 // Notify the pci bus enumeration is about to complete\r
111 //\r
ea8d98fa
OM		 112 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);\r
113\r
114 if (EFI_ERROR (Status)) {\r
115 return Status;\r
116 }\r
9060e3ec 117\r
118 //\r
119 // Process P2C\r
120 //\r
121 Status = PciHostBridgeP2CProcess (PciResAlloc);\r
122\r
123 if (EFI_ERROR (Status)) {\r
124 return Status;\r
125 }\r
126\r
127 //\r
128 // Process attributes for devices on this host bridge\r
129 //\r
130 Status = PciHostBridgeDeviceAttribute (PciResAlloc);\r
131 if (EFI_ERROR (Status)) {\r
132 return Status;\r
133 }\r
134\r
135 gFullEnumeration = FALSE;\r
136\r
137 Status = gBS->InstallProtocolInterface (\r
d838c744 138 &HostBridgeHandle,\r
9060e3ec 139 &gEfiPciEnumerationCompleteProtocolGuid,\r
140 EFI_NATIVE_INTERFACE,\r
141 NULL\r
142 );\r
143 if (EFI_ERROR (Status)) {\r
144 return Status;\r
145 }\r
146\r
147 return EFI_SUCCESS;\r
148}\r
149\r
150/**\r
151 Enumerate PCI root bridge.\r
152\r
153 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
154 @param RootBridgeDev Instance of root bridge device.\r
155\r
156 @retval EFI_SUCCESS Successfully enumerated root bridge.\r
157 @retval other Failed to enumerate root bridge.\r
158\r
159**/\r
160EFI_STATUS\r
161PciRootBridgeEnumerator (\r
162 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
163 IN PCI_IO_DEVICE *RootBridgeDev\r
164 )\r
165{\r
166 EFI_STATUS Status;\r
167 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
306bbe82 168 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;\r
169 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;\r
170 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;\r
9060e3ec 171 UINT8 SubBusNumber;\r
172 UINT8 StartBusNumber;\r
173 UINT8 PaddedBusRange;\r
174 EFI_HANDLE RootBridgeHandle;\r
306bbe82 175 UINT8 Desc;\r
176 UINT64 AddrLen;\r
177 UINT64 AddrRangeMin;\r
9060e3ec 178\r
179 SubBusNumber = 0;\r
180 StartBusNumber = 0;\r
181 PaddedBusRange = 0;\r
182\r
183 //\r
184 // Get the root bridge handle\r
185 //\r
186 RootBridgeHandle = RootBridgeDev->Handle;\r
187\r
188 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
189 EFI_PROGRESS_CODE,\r
fe91c992 190 EFI_IO_BUS_PCI | EFI_IOB_PCI_BUS_ENUM,\r
9060e3ec 191 RootBridgeDev->DevicePath\r
192 );\r
193\r
194 //\r
195 // Get the Bus information\r
196 //\r
197 Status = PciResAlloc->StartBusEnumeration (\r
198 PciResAlloc,\r
199 RootBridgeHandle,\r
200 (VOID **) &Configuration\r
201 );\r
202\r
203 if (EFI_ERROR (Status)) {\r
204 return Status;\r
205 }\r
206\r
306bbe82 207 if (Configuration == NULL || Configuration->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
208 return EFI_INVALID_PARAMETER;\r
209 }\r
210 RootBridgeDev->BusNumberRanges = Configuration;\r
211\r
212 //\r
213 // Sort the descriptors in ascending order\r
214 //\r
215 for (Configuration1 = Configuration; Configuration1->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration1++) {\r
216 Configuration2 = Configuration1;\r
217 for (Configuration3 = Configuration1 + 1; Configuration3->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration3++) {\r
218 if (Configuration2->AddrRangeMin > Configuration3->AddrRangeMin) {\r
219 Configuration2 = Configuration3;\r
220 }\r
221 }\r
222 //\r
223 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,\r
224 // so only need to swap these two fields.\r
225 //\r
226 if (Configuration2 != Configuration1) {\r
227 AddrRangeMin = Configuration1->AddrRangeMin;\r
228 Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;\r
229 Configuration2->AddrRangeMin = AddrRangeMin;\r
230 \r
231 AddrLen = Configuration1->AddrLen;\r
232 Configuration1->AddrLen = Configuration2->AddrLen;\r
233 Configuration2->AddrLen = AddrLen;\r
234 }\r
235 }\r
236\r
9060e3ec 237 //\r
238 // Get the bus number to start with\r
239 //\r
240 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
9060e3ec 241\r
242 //\r
243 // Initialize the subordinate bus number\r
244 //\r
245 SubBusNumber = StartBusNumber;\r
246\r
247 //\r
248 // Reset all assigned PCI bus number\r
249 //\r
250 ResetAllPpbBusNumber (\r
251 RootBridgeDev,\r
252 StartBusNumber\r
253 );\r
254\r
255 //\r
256 // Assign bus number\r
257 //\r
258 Status = PciScanBus (\r
259 RootBridgeDev,\r
306bbe82 260 StartBusNumber,\r
9060e3ec 261 &SubBusNumber,\r
262 &PaddedBusRange\r
263 );\r
264\r
265 if (EFI_ERROR (Status)) {\r
266 return Status;\r
267 }\r
268\r
269\r
270 //\r
271 // Assign max bus number scanned\r
272 //\r
9060e3ec 273\r
306bbe82 274 Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);\r
275 if (EFI_ERROR (Status)) {\r
276 return Status;\r
277 } \r
278\r
279 //\r
280 // Find the bus range which contains the higest bus number, then returns the number of buses\r
281 // that should be decoded.\r
282 //\r
283 while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {\r
284 Configuration++;\r
285 }\r
286 AddrLen = Configuration->AddrLen;\r
287 Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;\r
288\r
289 //\r
290 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.\r
291 //\r
292 Configuration++;\r
293 Desc = Configuration->Desc;\r
294 Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;\r
295 \r
9060e3ec 296 //\r
297 // Set bus number\r
298 //\r
299 Status = PciResAlloc->SetBusNumbers (\r
300 PciResAlloc,\r
301 RootBridgeHandle,\r
306bbe82 302 RootBridgeDev->BusNumberRanges\r
9060e3ec 303 );\r
304\r
306bbe82 305 //\r
306 // Restore changed fields\r
307 //\r
308 Configuration->Desc = Desc;\r
309 (Configuration - 1)->AddrLen = AddrLen;\r
310 \r
311 return Status;\r
9060e3ec 312}\r
313\r
314/**\r
315 This routine is used to process all PCI devices' Option Rom\r
316 on a certain root bridge.\r
317\r
318 @param Bridge Given parent's root bridge.\r
319 @param RomBase Base address of ROM driver loaded from.\r
320 @param MaxLength Maximum rom size.\r
321\r
322**/\r
323VOID\r
324ProcessOptionRom (\r
325 IN PCI_IO_DEVICE *Bridge,\r
326 IN UINT64 RomBase,\r
327 IN UINT64 MaxLength\r
328 )\r
329{\r
330 LIST_ENTRY *CurrentLink;\r
331 PCI_IO_DEVICE *Temp;\r
332\r
333 //\r
334 // Go through bridges to reach all devices\r
335 //\r
336 CurrentLink = Bridge->ChildList.ForwardLink;\r
337 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
338 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
339 if (!IsListEmpty (&Temp->ChildList)) {\r
340\r
341 //\r
342 // Go further to process the option rom under this bridge\r
343 //\r
344 ProcessOptionRom (Temp, RomBase, MaxLength);\r
345 }\r
346\r
347 if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {\r
348\r
349 //\r
350 // Load and process the option rom\r
351 //\r
352 LoadOpRomImage (Temp, RomBase);\r
353 }\r
354\r
355 CurrentLink = CurrentLink->ForwardLink;\r
356 }\r
357}\r
358\r
359/**\r
360 This routine is used to assign bus number to the given PCI bus system\r
361\r
362 @param Bridge Parent root bridge instance.\r
363 @param StartBusNumber Number of beginning.\r
364 @param SubBusNumber The number of sub bus.\r
365\r
366 @retval EFI_SUCCESS Successfully assigned bus number.\r
367 @retval EFI_DEVICE_ERROR Failed to assign bus number.\r
368\r
369**/\r
370EFI_STATUS\r
371PciAssignBusNumber (\r
372 IN PCI_IO_DEVICE *Bridge,\r
373 IN UINT8 StartBusNumber,\r
374 OUT UINT8 *SubBusNumber\r
375 )\r
376{\r
377 EFI_STATUS Status;\r
378 PCI_TYPE00 Pci;\r
379 UINT8 Device;\r
380 UINT8 Func;\r
381 UINT64 Address;\r
382 UINTN SecondBus;\r
383 UINT16 Register;\r
384 UINT8 Register8;\r
385 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
386\r
387 PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
388\r
389 SecondBus = 0;\r
390 Register = 0;\r
391\r
392 *SubBusNumber = StartBusNumber;\r
393\r
394 //\r
395 // First check to see whether the parent is ppb\r
396 //\r
397 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
398 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
399\r
400 //\r
401 // Check to see whether a pci device is present\r
402 //\r
403 Status = PciDevicePresent (\r
404 PciRootBridgeIo,\r
405 &Pci,\r
406 StartBusNumber,\r
407 Device,\r
408 Func\r
409 );\r
410\r
25a26646
JS		 411 if (EFI_ERROR (Status) && Func == 0) {\r
412 //\r
413 // go to next device if there is no Function 0\r
414 //\r
415 break;\r
416 }\r
417\r
9060e3ec 418 if (!EFI_ERROR (Status) &&\r
419 (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
420\r
421 //\r
422 // Reserved one bus for cardbus bridge\r
423 //\r
306bbe82 424 Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);\r
425 if (EFI_ERROR (Status)) {\r
426 return Status;\r
427 }\r
428 SecondBus = *SubBusNumber;\r
9060e3ec 429\r
430 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
431\r
432 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
433\r
434 Status = PciRootBridgeIo->Pci.Write (\r
435 PciRootBridgeIo,\r
436 EfiPciWidthUint16,\r
437 Address,\r
438 1,\r
439 &Register\r
440 );\r
441\r
442 //\r
443 // Initialize SubBusNumber to SecondBus\r
444 //\r
445 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
446 Status = PciRootBridgeIo->Pci.Write (\r
447 PciRootBridgeIo,\r
448 EfiPciWidthUint8,\r
449 Address,\r
450 1,\r
451 SubBusNumber\r
452 );\r
453 //\r
454 // If it is PPB, resursively search down this bridge\r
455 //\r
456 if (IS_PCI_BRIDGE (&Pci)) {\r
457\r
458 Register8 = 0xFF;\r
459 Status = PciRootBridgeIo->Pci.Write (\r
460 PciRootBridgeIo,\r
461 EfiPciWidthUint8,\r
462 Address,\r
463 1,\r
464 &Register8\r
465 );\r
466\r
467 Status = PciAssignBusNumber (\r
468 Bridge,\r
469 (UINT8) (SecondBus),\r
470 SubBusNumber\r
471 );\r
472\r
473 if (EFI_ERROR (Status)) {\r
474 return EFI_DEVICE_ERROR;\r
475 }\r
476 }\r
477\r
478 //\r
479 // Set the current maximum bus number under the PPB\r
480 //\r
481 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
482\r
483 Status = PciRootBridgeIo->Pci.Write (\r
484 PciRootBridgeIo,\r
485 EfiPciWidthUint8,\r
486 Address,\r
487 1,\r
488 SubBusNumber\r
489 );\r
490\r
491 }\r
492\r
493 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
494\r
495 //\r
496 // Skip sub functions, this is not a multi function device\r
497 //\r
498 Func = PCI_MAX_FUNC;\r
499 }\r
500 }\r
501 }\r
502\r
503 return EFI_SUCCESS;\r
504}\r
505\r
506/**\r
507 This routine is used to determine the root bridge attribute by interfacing\r
508 the host bridge resource allocation protocol.\r
509\r
510 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
511 @param RootBridgeDev Root bridge instance\r
512\r
513 @retval EFI_SUCCESS Successfully got root bridge's attribute.\r
514 @retval other Failed to get attribute.\r
515\r
516**/\r
517EFI_STATUS\r
518DetermineRootBridgeAttributes (\r
519 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
520 IN PCI_IO_DEVICE *RootBridgeDev\r
521 )\r
522{\r
523 UINT64 Attributes;\r
524 EFI_STATUS Status;\r
525 EFI_HANDLE RootBridgeHandle;\r
526\r
527 Attributes = 0;\r
528 RootBridgeHandle = RootBridgeDev->Handle;\r
529\r
530 //\r
531 // Get root bridge attribute by calling into pci host bridge resource allocation protocol\r
532 //\r
533 Status = PciResAlloc->GetAllocAttributes (\r
534 PciResAlloc,\r
535 RootBridgeHandle,\r
536 &Attributes\r
537 );\r
538\r
539 if (EFI_ERROR (Status)) {\r
540 return Status;\r
541 }\r
542\r
543 //\r
544 // Here is the point where PCI bus driver calls HOST bridge allocation protocol\r
545 // Currently we hardcoded for ea815\r
546 //\r
547 if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
548 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;\r
549 }\r
550\r
551 if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {\r
60516202 552 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM64_DECODE_SUPPORTED;\r
9060e3ec 553 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;\r
554 }\r
555\r
556 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;\r
557 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;\r
558 RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;\r
559\r
560 return EFI_SUCCESS;\r
561}\r
562\r
563/**\r
564 Get Max Option Rom size on specified bridge.\r
565\r
566 @param Bridge Given bridge device instance.\r
567\r
568 @return Max size of option rom needed.\r
569\r
570**/\r
571UINT64\r
572GetMaxOptionRomSize (\r
573 IN PCI_IO_DEVICE *Bridge\r
574 )\r
575{\r
576 LIST_ENTRY *CurrentLink;\r
577 PCI_IO_DEVICE *Temp;\r
578 UINT64 MaxOptionRomSize;\r
579 UINT64 TempOptionRomSize;\r
580\r
581 MaxOptionRomSize = 0;\r
582\r
583 //\r
584 // Go through bridges to reach all devices\r
585 //\r
586 CurrentLink = Bridge->ChildList.ForwardLink;\r
587 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
588 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
589 if (!IsListEmpty (&Temp->ChildList)) {\r
590\r
591 //\r
592 // Get max option rom size under this bridge\r
593 //\r
594 TempOptionRomSize = GetMaxOptionRomSize (Temp);\r
595\r
596 //\r
597 // Compare with the option rom size of the bridge\r
598 // Get the larger one\r
599 //\r
600 if (Temp->RomSize > TempOptionRomSize) {\r
601 TempOptionRomSize = Temp->RomSize;\r
602 }\r
603\r
604 } else {\r
605\r
606 //\r
607 // For devices get the rom size directly\r
608 //\r
609 TempOptionRomSize = Temp->RomSize;\r
610 }\r
611\r
612 //\r
613 // Get the largest rom size on this bridge\r
614 //\r
615 if (TempOptionRomSize > MaxOptionRomSize) {\r
616 MaxOptionRomSize = TempOptionRomSize;\r
617 }\r
618\r
619 CurrentLink = CurrentLink->ForwardLink;\r
620 }\r
621\r
622 return MaxOptionRomSize;\r
623}\r
624\r
625/**\r
626 Process attributes of devices on this host bridge\r
627\r
628 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
629\r
630 @retval EFI_SUCCESS Successfully process attribute.\r
631 @retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
632 @retval other Failed to determine the root bridge device's attribute.\r
633\r
634**/\r
635EFI_STATUS\r
636PciHostBridgeDeviceAttribute (\r
637 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
638 )\r
639{\r
640 EFI_HANDLE RootBridgeHandle;\r
641 PCI_IO_DEVICE *RootBridgeDev;\r
642 EFI_STATUS Status;\r
643\r
644 RootBridgeHandle = NULL;\r
645\r
646 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
647\r
648 //\r
649 // Get RootBridg Device by handle\r
650 //\r
651 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
652\r
653 if (RootBridgeDev == NULL) {\r
654 return EFI_NOT_FOUND;\r
655 }\r
656\r
657 //\r
658 // Set the attributes for devcies behind the Root Bridge\r
659 //\r
660 Status = DetermineDeviceAttribute (RootBridgeDev);\r
661 if (EFI_ERROR (Status)) {\r
662 return Status;\r
663 }\r
664\r
665 }\r
666\r
667 return EFI_SUCCESS;\r
668}\r
669\r
670/**\r
671 Get resource allocation status from the ACPI resource descriptor.\r
672\r
673 @param AcpiConfig Point to Acpi configuration table.\r
674 @param IoResStatus Return the status of I/O resource.\r
675 @param Mem32ResStatus Return the status of 32-bit Memory resource.\r
676 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.\r
677 @param Mem64ResStatus Return the status of 64-bit Memory resource.\r
678 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.\r
679\r
680**/\r
681VOID\r
682GetResourceAllocationStatus (\r
683 VOID *AcpiConfig,\r
684 OUT UINT64 *IoResStatus,\r
685 OUT UINT64 *Mem32ResStatus,\r
686 OUT UINT64 *PMem32ResStatus,\r
687 OUT UINT64 *Mem64ResStatus,\r
688 OUT UINT64 *PMem64ResStatus\r
689 )\r
690{\r
691 UINT8 *Temp;\r
692 UINT64 ResStatus;\r
693 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
694\r
695 Temp = (UINT8 *) AcpiConfig;\r
696\r
697 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
698\r
699 ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
700 ResStatus = ACPIAddressDesc->AddrTranslationOffset;\r
701\r
702 switch (ACPIAddressDesc->ResType) {\r
703 case 0:\r
704 if (ACPIAddressDesc->AddrSpaceGranularity == 32) {\r
705 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
706 //\r
707 // Pmem32\r
708 //\r
709 *PMem32ResStatus = ResStatus;\r
710 } else {\r
711 //\r
712 // Mem32\r
713 //\r
714 *Mem32ResStatus = ResStatus;\r
715 }\r
716 }\r
717\r
718 if (ACPIAddressDesc->AddrSpaceGranularity == 64) {\r
719 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
720 //\r
721 // PMem64\r
722 //\r
723 *PMem64ResStatus = ResStatus;\r
724 } else {\r
725 //\r
726 // Mem64\r
727 //\r
728 *Mem64ResStatus = ResStatus;\r
729 }\r
730 }\r
731\r
732 break;\r
733\r
734 case 1:\r
735 //\r
736 // Io\r
737 //\r
738 *IoResStatus = ResStatus;\r
739 break;\r
740\r
741 default:\r
742 break;\r
743 }\r
744\r
745 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
746 }\r
747}\r
748\r
749/**\r
750 Remove a PCI device from device pool and mark its bar.\r
751\r
752 @param PciDevice Instance of Pci device.\r
753\r
754 @retval EFI_SUCCESS Successfully remove the PCI device.\r
755 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r
756\r
757**/\r
758EFI_STATUS\r
759RejectPciDevice (\r
760 IN PCI_IO_DEVICE *PciDevice\r
761 )\r
762{\r
763 PCI_IO_DEVICE *Bridge;\r
764 PCI_IO_DEVICE *Temp;\r
765 LIST_ENTRY *CurrentLink;\r
766\r
767 //\r
768 // Remove the padding resource from a bridge\r
769 //\r
770 if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&\r
771 PciDevice->ResourcePaddingDescriptors != NULL ) {\r
772 FreePool (PciDevice->ResourcePaddingDescriptors);\r
773 PciDevice->ResourcePaddingDescriptors = NULL;\r
774 return EFI_SUCCESS;\r
775 }\r
776\r
777 //\r
778 // Skip RB and PPB\r
779 //\r
780 if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {\r
781 return EFI_ABORTED;\r
782 }\r
783\r
784 if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {\r
785 //\r
786 // Get the root bridge device\r
787 //\r
788 Bridge = PciDevice;\r
789 while (Bridge->Parent != NULL) {\r
790 Bridge = Bridge->Parent;\r
791 }\r
792\r
793 RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);\r
794\r
795 //\r
796 // Mark its bar\r
797 //\r
798 InitializeP2C (PciDevice);\r
799 }\r
800\r
801 //\r
802 // Remove the device\r
803 //\r
804 Bridge = PciDevice->Parent;\r
805 CurrentLink = Bridge->ChildList.ForwardLink;\r
806 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
807 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
808 if (Temp == PciDevice) {\r
809 InitializePciDevice (Temp);\r
810 RemoveEntryList (CurrentLink);\r
9060e3ec 811 return EFI_SUCCESS;\r
812 }\r
813\r
814 CurrentLink = CurrentLink->ForwardLink;\r
815 }\r
816\r
817 return EFI_ABORTED;\r
818}\r
819\r
820/**\r
821 Determine whethter a PCI device can be rejected.\r
822\r
823 @param PciResNode Pointer to Pci resource node instance.\r
824\r
825 @retval TRUE The PCI device can be rejected.\r
826 @retval TRUE The PCI device cannot be rejected.\r
827\r
828**/\r
829BOOLEAN\r
830IsRejectiveDevice (\r
831 IN PCI_RESOURCE_NODE *PciResNode\r
832 )\r
833{\r
834 PCI_IO_DEVICE *Temp;\r
835\r
836 Temp = PciResNode->PciDev;\r
837\r
838 //\r
839 // Ensure the device is present\r
840 //\r
841 if (Temp == NULL) {\r
842 return FALSE;\r
843 }\r
844\r
845 //\r
846 // PPB and RB should go ahead\r
847 //\r
848 if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {\r
849 return TRUE;\r
850 }\r
851\r
852 //\r
853 // Skip device on Bus0\r
854 //\r
855 if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {\r
856 return FALSE;\r
857 }\r
858\r
859 //\r
860 // Skip VGA\r
861 //\r
862 if (IS_PCI_VGA (&Temp->Pci)) {\r
863 return FALSE;\r
864 }\r
865\r
866 return TRUE;\r
867}\r
868\r
869/**\r
870 Compare two resource nodes and get the larger resource consumer.\r
871\r
872 @param PciResNode1 resource node 1 want to be compared\r
873 @param PciResNode2 resource node 2 want to be compared\r
874\r
875 @return Larger resource node.\r
876\r
877**/\r
878PCI_RESOURCE_NODE *\r
879GetLargerConsumerDevice (\r
880 IN PCI_RESOURCE_NODE *PciResNode1,\r
881 IN PCI_RESOURCE_NODE *PciResNode2\r
882 )\r
883{\r
884 if (PciResNode2 == NULL) {\r
885 return PciResNode1;\r
886 }\r
887\r
888 if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \\r
889 && (PciResNode2->ResourceUsage != PciResUsagePadding) )\r
890 {\r
891 return PciResNode1;\r
892 }\r
893\r
894 if (PciResNode1 == NULL) {\r
895 return PciResNode2;\r
896 }\r
897\r
898 if ((PciResNode1->Length) > (PciResNode2->Length)) {\r
899 return PciResNode1;\r
900 }\r
901\r
902 return PciResNode2;\r
903}\r
904\r
905\r
906/**\r
907 Get the max resource consumer in the host resource pool.\r
908\r
909 @param ResPool Pointer to resource pool node.\r
910\r
911 @return The max resource consumer in the host resource pool.\r
912\r
913**/\r
914PCI_RESOURCE_NODE *\r
915GetMaxResourceConsumerDevice (\r
916 IN PCI_RESOURCE_NODE *ResPool\r
917 )\r
918{\r
919 PCI_RESOURCE_NODE *Temp;\r
920 LIST_ENTRY *CurrentLink;\r
921 PCI_RESOURCE_NODE *PciResNode;\r
922 PCI_RESOURCE_NODE *PPBResNode;\r
923\r
924 PciResNode = NULL;\r
925\r
926 CurrentLink = ResPool->ChildList.ForwardLink;\r
927 while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {\r
928\r
929 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
930\r
931 if (!IsRejectiveDevice (Temp)) {\r
932 CurrentLink = CurrentLink->ForwardLink;\r
933 continue;\r
934 }\r
935\r
936 if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \\r
937 && (Temp->ResourceUsage != PciResUsagePadding))\r
938 {\r
939 PPBResNode = GetMaxResourceConsumerDevice (Temp);\r
940 PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);\r
941 } else {\r
942 PciResNode = GetLargerConsumerDevice (PciResNode, Temp);\r
943 }\r
944\r
945 CurrentLink = CurrentLink->ForwardLink;\r
946 }\r
947\r
948 return PciResNode;\r
949}\r
950\r
951/**\r
952 Adjust host bridge allocation so as to reduce resource requirement\r
953\r
954 @param IoPool Pointer to instance of I/O resource Node.\r
955 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r
956 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.\r
957 @param Mem64Pool Pointer to instance of 64-bit memory resource node.\r
958 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.\r
959 @param IoResStatus Status of I/O resource Node.\r
960 @param Mem32ResStatus Status of 32-bit memory resource Node.\r
961 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.\r
962 @param Mem64ResStatus Status of 64-bit memory resource node.\r
963 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.\r
964\r
965 @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.\r
966 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.\r
967\r
968**/\r
969EFI_STATUS\r
970PciHostBridgeAdjustAllocation (\r
971 IN PCI_RESOURCE_NODE *IoPool,\r
972 IN PCI_RESOURCE_NODE *Mem32Pool,\r
973 IN PCI_RESOURCE_NODE *PMem32Pool,\r
974 IN PCI_RESOURCE_NODE *Mem64Pool,\r
975 IN PCI_RESOURCE_NODE *PMem64Pool,\r
976 IN UINT64 IoResStatus,\r
977 IN UINT64 Mem32ResStatus,\r
978 IN UINT64 PMem32ResStatus,\r
979 IN UINT64 Mem64ResStatus,\r
980 IN UINT64 PMem64ResStatus\r
981 )\r
982{\r
983 BOOLEAN AllocationAjusted;\r
984 PCI_RESOURCE_NODE *PciResNode;\r
985 PCI_RESOURCE_NODE *ResPool[5];\r
986 PCI_IO_DEVICE *RemovedPciDev[5];\r
987 UINT64 ResStatus[5];\r
988 UINTN RemovedPciDevNum;\r
989 UINTN DevIndex;\r
990 UINTN ResType;\r
991 EFI_STATUS Status;\r
992 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
993\r
994 PciResNode = NULL;\r
995 ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));\r
996 RemovedPciDevNum = 0;\r
997\r
998 ResPool[0] = IoPool;\r
999 ResPool[1] = Mem32Pool;\r
1000 ResPool[2] = PMem32Pool;\r
1001 ResPool[3] = Mem64Pool;\r
1002 ResPool[4] = PMem64Pool;\r
1003\r
1004 ResStatus[0] = IoResStatus;\r
1005 ResStatus[1] = Mem32ResStatus;\r
1006 ResStatus[2] = PMem32ResStatus;\r
1007 ResStatus[3] = Mem64ResStatus;\r
1008 ResStatus[4] = PMem64ResStatus;\r
1009\r
1010 AllocationAjusted = FALSE;\r
1011\r
1012 for (ResType = 0; ResType < 5; ResType++) {\r
1013\r
1014 if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {\r
1015 continue;\r
1016 }\r
1017\r
1018 if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {\r
1019 //\r
1020 // Host bridge hasn't this resource type\r
1021 //\r
1022 return EFI_ABORTED;\r
1023 }\r
1024\r
1025 //\r
1026 // Hostbridge hasn't enough resource\r
1027 //\r
1028 PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);\r
1029 if (PciResNode == NULL) {\r
1030 continue;\r
1031 }\r
1032\r
1033 //\r
1034 // Check if the device has been removed before\r
1035 //\r
1036 for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {\r
1037 if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {\r
1038 break;\r
1039 }\r
1040 }\r
1041\r
1042 if (DevIndex != RemovedPciDevNum) {\r
1043 continue;\r
1044 }\r
1045\r
1046 //\r
1047 // Remove the device if it isn't in the array\r
1048 //\r
1049 Status = RejectPciDevice (PciResNode->PciDev);\r
1050 if (Status == EFI_SUCCESS) {\r
724f26a9
RN		 1051 DEBUG ((\r
1052 EFI_D_ERROR,\r
1053 "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",\r
1054 PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber\r
1055 ));\r
9060e3ec 1056\r
1057 //\r
1058 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
1059 //\r
1060 //\r
1061 // Have no way to get ReqRes, AllocRes & Bar here\r
1062 //\r
1063 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
c9325700 1064 AllocFailExtendedData.DevicePathSize = (UINT16) sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
9060e3ec 1065 AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;\r
1066 AllocFailExtendedData.Bar = PciResNode->Bar;\r
1067\r
1068 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
1069 EFI_PROGRESS_CODE,\r
1070 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
1071 (VOID *) &AllocFailExtendedData,\r
1072 sizeof (AllocFailExtendedData)\r
1073 );\r
1074\r
1075 //\r
1076 // Add it to the array and indicate at least a device has been rejected\r
1077 //\r
1078 RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;\r
1079 AllocationAjusted = TRUE;\r
1080 }\r
1081 }\r
1082 //\r
1083 // End for\r
1084 //\r
1085\r
1086 if (AllocationAjusted) {\r
1087 return EFI_SUCCESS;\r
1088 } else {\r
1089 return EFI_ABORTED;\r
1090 }\r
1091}\r
1092\r
1093/**\r
1094 Summary requests for all resource type, and contruct ACPI resource\r
1095 requestor instance.\r
1096\r
1097 @param Bridge detecting bridge\r
1098 @param IoNode Pointer to instance of I/O resource Node\r
1099 @param Mem32Node Pointer to instance of 32-bit memory resource Node\r
1100 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node\r
1101 @param Mem64Node Pointer to instance of 64-bit memory resource node\r
1102 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r
1103 @param Config Output buffer holding new constructed APCI resource requestor\r
1104\r
1105 @retval EFI_SUCCESS Successfully constructed ACPI resource.\r
1106 @retval EFI_OUT_OF_RESOURCES No memory availabe.\r
1107\r
1108**/\r
1109EFI_STATUS\r
1110ConstructAcpiResourceRequestor (\r
1111 IN PCI_IO_DEVICE *Bridge,\r
1112 IN PCI_RESOURCE_NODE *IoNode,\r
1113 IN PCI_RESOURCE_NODE *Mem32Node,\r
1114 IN PCI_RESOURCE_NODE *PMem32Node,\r
1115 IN PCI_RESOURCE_NODE *Mem64Node,\r
1116 IN PCI_RESOURCE_NODE *PMem64Node,\r
1117 OUT VOID **Config\r
1118 )\r
1119{\r
1120 UINT8 NumConfig;\r
1121 UINT8 Aperture;\r
1122 UINT8 *Configuration;\r
1123 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1124 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
1125\r
1126 NumConfig = 0;\r
1127 Aperture = 0;\r
1128\r
1129 *Config = NULL;\r
1130\r
1131 //\r
1132 // if there is io request, add to the io aperture\r
1133 //\r
1134 if (ResourceRequestExisted (IoNode)) {\r
1135 NumConfig++;\r
1136 Aperture |= 0x01;\r
1137 }\r
1138\r
1139 //\r
1140 // if there is mem32 request, add to the mem32 aperture\r
1141 //\r
1142 if (ResourceRequestExisted (Mem32Node)) {\r
1143 NumConfig++;\r
1144 Aperture |= 0x02;\r
1145 }\r
1146\r
1147 //\r
1148 // if there is pmem32 request, add to the pmem32 aperture\r
1149 //\r
1150 if (ResourceRequestExisted (PMem32Node)) {\r
1151 NumConfig++;\r
1152 Aperture |= 0x04;\r
1153 }\r
1154\r
1155 //\r
1156 // if there is mem64 request, add to the mem64 aperture\r
1157 //\r
1158 if (ResourceRequestExisted (Mem64Node)) {\r
1159 NumConfig++;\r
1160 Aperture |= 0x08;\r
1161 }\r
1162\r
1163 //\r
1164 // if there is pmem64 request, add to the pmem64 aperture\r
1165 //\r
1166 if (ResourceRequestExisted (PMem64Node)) {\r
1167 NumConfig++;\r
1168 Aperture |= 0x10;\r
1169 }\r
1170\r
1171 if (NumConfig != 0) {\r
1172\r
1173 //\r
1174 // If there is at least one type of resource request,\r
1175 // allocate a acpi resource node\r
1176 //\r
1177 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1178 if (Configuration == NULL) {\r
1179 return EFI_OUT_OF_RESOURCES;\r
1180 }\r
1181\r
1182 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
1183\r
1184 //\r
1185 // Deal with io aperture\r
1186 //\r
1187 if ((Aperture & 0x01) != 0) {\r
1188 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
c9325700 1189 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1190 //\r
1191 // Io\r
1192 //\r
1193 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
1194 //\r
1195 // non ISA range\r
1196 //\r
1197 Ptr->SpecificFlag = 1;\r
1198 Ptr->AddrLen = IoNode->Length;\r
1199 Ptr->AddrRangeMax = IoNode->Alignment;\r
1200\r
1201 Ptr++;\r
1202 }\r
1203 //\r
1204 // Deal with mem32 aperture\r
1205 //\r
1206 if ((Aperture & 0x02) != 0) {\r
1207 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1208 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1209 //\r
1210 // Mem\r
1211 //\r
1212 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1213 //\r
1214 // Nonprefechable\r
1215 //\r
1216 Ptr->SpecificFlag = 0;\r
1217 //\r
1218 // 32 bit\r
1219 //\r
1220 Ptr->AddrSpaceGranularity = 32;\r
1221 Ptr->AddrLen = Mem32Node->Length;\r
1222 Ptr->AddrRangeMax = Mem32Node->Alignment;\r
1223\r
1224 Ptr++;\r
1225 }\r
1226\r
1227 //\r
1228 // Deal with Pmem32 aperture\r
1229 //\r
1230 if ((Aperture & 0x04) != 0) {\r
1231 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1232 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1233 //\r
1234 // Mem\r
1235 //\r
1236 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1237 //\r
1238 // prefechable\r
1239 //\r
1240 Ptr->SpecificFlag = 0x6;\r
1241 //\r
1242 // 32 bit\r
1243 //\r
1244 Ptr->AddrSpaceGranularity = 32;\r
1245 Ptr->AddrLen = PMem32Node->Length;\r
1246 Ptr->AddrRangeMax = PMem32Node->Alignment;\r
1247\r
1248 Ptr++;\r
1249 }\r
1250 //\r
1251 // Deal with mem64 aperture\r
1252 //\r
1253 if ((Aperture & 0x08) != 0) {\r
1254 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1255 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1256 //\r
1257 // Mem\r
1258 //\r
1259 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1260 //\r
1261 // nonprefechable\r
1262 //\r
1263 Ptr->SpecificFlag = 0;\r
1264 //\r
1265 // 64 bit\r
1266 //\r
1267 Ptr->AddrSpaceGranularity = 64;\r
1268 Ptr->AddrLen = Mem64Node->Length;\r
1269 Ptr->AddrRangeMax = Mem64Node->Alignment;\r
1270\r
1271 Ptr++;\r
1272 }\r
1273 //\r
1274 // Deal with Pmem64 aperture\r
1275 //\r
1276 if ((Aperture & 0x10) != 0) {\r
1277 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
cd7bfc2c 1278 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
9060e3ec 1279 //\r
1280 // Mem\r
1281 //\r
1282 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1283 //\r
1284 // prefechable\r
1285 //\r
1286 Ptr->SpecificFlag = 0x06;\r
1287 //\r
1288 // 64 bit\r
1289 //\r
1290 Ptr->AddrSpaceGranularity = 64;\r
1291 Ptr->AddrLen = PMem64Node->Length;\r
1292 Ptr->AddrRangeMax = PMem64Node->Alignment;\r
1293\r
1294 Ptr++;\r
1295 }\r
1296\r
1297 //\r
1298 // put the checksum\r
1299 //\r
1300 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;\r
1301\r
1302 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1303 PtrEnd->Checksum = 0;\r
1304\r
1305 } else {\r
1306\r
1307 //\r
1308 // If there is no resource request\r
1309 //\r
1310 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1311 if (Configuration == NULL) {\r
1312 return EFI_OUT_OF_RESOURCES;\r
1313 }\r
1314\r
1315 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);\r
1316 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1317\r
1318 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Ptr + 1);\r
1319 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1320 PtrEnd->Checksum = 0;\r
1321 }\r
1322\r
1323 *Config = Configuration;\r
1324\r
1325 return EFI_SUCCESS;\r
1326}\r
1327\r
1328/**\r
1329 Get resource base from an acpi configuration descriptor.\r
1330\r
1331 @param Config An acpi configuration descriptor.\r
1332 @param IoBase Output of I/O resource base address.\r
1333 @param Mem32Base Output of 32-bit memory base address.\r
1334 @param PMem32Base Output of 32-bit prefetchable memory base address.\r
1335 @param Mem64Base Output of 64-bit memory base address.\r
1336 @param PMem64Base Output of 64-bit prefetchable memory base address.\r
1337\r
1338**/\r
1339VOID\r
1340GetResourceBase (\r
1341 IN VOID *Config,\r
1342 OUT UINT64 *IoBase,\r
1343 OUT UINT64 *Mem32Base,\r
1344 OUT UINT64 *PMem32Base,\r
1345 OUT UINT64 *Mem64Base,\r
1346 OUT UINT64 *PMem64Base\r
1347 )\r
1348{\r
1349 UINT8 *Temp;\r
1350 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1351 UINT64 ResStatus;\r
1352\r
1353 ASSERT (Config != NULL);\r
1354\r
1355 *IoBase = 0xFFFFFFFFFFFFFFFFULL;\r
1356 *Mem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1357 *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1358 *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1359 *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1360\r
1361 Temp = (UINT8 *) Config;\r
1362\r
1363 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
1364\r
1365 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
1366 ResStatus = Ptr->AddrTranslationOffset;\r
1367\r
1368 if (ResStatus == EFI_RESOURCE_SATISFIED) {\r
1369\r
1370 switch (Ptr->ResType) {\r
1371\r
1372 //\r
1373 // Memory type aperture\r
1374 //\r
1375 case 0:\r
1376\r
1377 //\r
1378 // Check to see the granularity\r
1379 //\r
1380 if (Ptr->AddrSpaceGranularity == 32) {\r
1381 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
1382 *PMem32Base = Ptr->AddrRangeMin;\r
1383 } else {\r
1384 *Mem32Base = Ptr->AddrRangeMin;\r
1385 }\r
1386 }\r
1387\r
1388 if (Ptr->AddrSpaceGranularity == 64) {\r
1389 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
1390 *PMem64Base = Ptr->AddrRangeMin;\r
1391 } else {\r
1392 *Mem64Base = Ptr->AddrRangeMin;\r
1393 }\r
1394 }\r
1395 break;\r
1396\r
1397 case 1:\r
1398\r
1399 //\r
1400 // Io type aperture\r
1401 //\r
1402 *IoBase = Ptr->AddrRangeMin;\r
1403 break;\r
1404\r
1405 default:\r
1406 break;\r
1407\r
1408 }\r
1409 //\r
1410 // End switch\r
1411 //\r
1412 }\r
1413 //\r
1414 // End for\r
1415 //\r
1416 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
1417 }\r
1418}\r
1419\r
1420/**\r
1421 Enumerate pci bridge, allocate resource and determine attribute\r
1422 for devices on this bridge.\r
1423\r
1424 @param BridgeDev Pointer to instance of bridge device.\r
1425\r
1426 @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r
1427 @retval other Failed to enumerate.\r
1428\r
1429**/\r
1430EFI_STATUS\r
1431PciBridgeEnumerator (\r
1432 IN PCI_IO_DEVICE *BridgeDev\r
1433 )\r
1434{\r
1435 UINT8 SubBusNumber;\r
1436 UINT8 StartBusNumber;\r
1437 EFI_PCI_IO_PROTOCOL *PciIo;\r
1438 EFI_STATUS Status;\r
1439\r
1440 SubBusNumber = 0;\r
1441 StartBusNumber = 0;\r
1442 PciIo = &(BridgeDev->PciIo);\r
1443 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
1444\r
1445 if (EFI_ERROR (Status)) {\r
1446 return Status;\r
1447 }\r
1448\r
1449 Status = PciAssignBusNumber (\r
1450 BridgeDev,\r
1451 StartBusNumber,\r
1452 &SubBusNumber\r
1453 );\r
1454\r
1455 if (EFI_ERROR (Status)) {\r
1456 return Status;\r
1457 }\r
1458\r
1459 Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);\r
1460\r
1461 if (EFI_ERROR (Status)) {\r
1462 return Status;\r
1463 }\r
1464\r
1465 Status = PciBridgeResourceAllocator (BridgeDev);\r
1466\r
1467 if (EFI_ERROR (Status)) {\r
1468 return Status;\r
1469 }\r
1470\r
1471 Status = DetermineDeviceAttribute (BridgeDev);\r
1472\r
1473 if (EFI_ERROR (Status)) {\r
1474 return Status;\r
1475 }\r
1476\r
1477 return EFI_SUCCESS;\r
1478\r
1479}\r
1480\r
1481/**\r
1482 Allocate all kinds of resource for PCI bridge.\r
1483\r
1484 @param Bridge Pointer to bridge instance.\r
1485\r
1486 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r
1487 @retval other Failed to allocate resource for bridge.\r
1488\r
1489**/\r
1490EFI_STATUS\r
1491PciBridgeResourceAllocator (\r
1492 IN PCI_IO_DEVICE *Bridge\r
1493 )\r
1494{\r
1495 PCI_RESOURCE_NODE *IoBridge;\r
1496 PCI_RESOURCE_NODE *Mem32Bridge;\r
1497 PCI_RESOURCE_NODE *PMem32Bridge;\r
1498 PCI_RESOURCE_NODE *Mem64Bridge;\r
1499 PCI_RESOURCE_NODE *PMem64Bridge;\r
1500 UINT64 IoBase;\r
1501 UINT64 Mem32Base;\r
1502 UINT64 PMem32Base;\r
1503 UINT64 Mem64Base;\r
1504 UINT64 PMem64Base;\r
1505 EFI_STATUS Status;\r
1506\r
1507 IoBridge = CreateResourceNode (\r
1508 Bridge,\r
1509 0,\r
1ef26783 1510 Bridge->BridgeIoAlignment,\r
9060e3ec 1511 0,\r
1512 PciBarTypeIo16,\r
1513 PciResUsageTypical\r
1514 );\r
1515\r
1516 Mem32Bridge = CreateResourceNode (\r
1517 Bridge,\r
1518 0,\r
1519 0xFFFFF,\r
1520 0,\r
1521 PciBarTypeMem32,\r
1522 PciResUsageTypical\r
1523 );\r
1524\r
1525 PMem32Bridge = CreateResourceNode (\r
1526 Bridge,\r
1527 0,\r
1528 0xFFFFF,\r
1529 0,\r
1530 PciBarTypePMem32,\r
1531 PciResUsageTypical\r
1532 );\r
1533\r
1534 Mem64Bridge = CreateResourceNode (\r
1535 Bridge,\r
1536 0,\r
1537 0xFFFFF,\r
1538 0,\r
1539 PciBarTypeMem64,\r
1540 PciResUsageTypical\r
1541 );\r
1542\r
1543 PMem64Bridge = CreateResourceNode (\r
1544 Bridge,\r
1545 0,\r
1546 0xFFFFF,\r
1547 0,\r
1548 PciBarTypePMem64,\r
1549 PciResUsageTypical\r
1550 );\r
1551\r
1552 //\r
1553 // Create resourcemap by going through all the devices subject to this root bridge\r
1554 //\r
1555 CreateResourceMap (\r
1556 Bridge,\r
1557 IoBridge,\r
1558 Mem32Bridge,\r
1559 PMem32Bridge,\r
1560 Mem64Bridge,\r
1561 PMem64Bridge\r
1562 );\r
1563\r
1564 Status = GetResourceBaseFromBridge (\r
1565 Bridge,\r
1566 &IoBase,\r
1567 &Mem32Base,\r
1568 &PMem32Base,\r
1569 &Mem64Base,\r
1570 &PMem64Base\r
1571 );\r
1572\r
1573 if (EFI_ERROR (Status)) {\r
1574 return Status;\r
1575 }\r
1576\r
1577 //\r
1578 // Program IO resources\r
1579 //\r
1580 ProgramResource (\r
1581 IoBase,\r
1582 IoBridge\r
1583 );\r
1584\r
1585 //\r
1586 // Program Mem32 resources\r
1587 //\r
1588 ProgramResource (\r
1589 Mem32Base,\r
1590 Mem32Bridge\r
1591 );\r
1592\r
1593 //\r
1594 // Program PMem32 resources\r
1595 //\r
1596 ProgramResource (\r
1597 PMem32Base,\r
1598 PMem32Bridge\r
1599 );\r
1600\r
1601 //\r
1602 // Program Mem64 resources\r
1603 //\r
1604 ProgramResource (\r
1605 Mem64Base,\r
1606 Mem64Bridge\r
1607 );\r
1608\r
1609 //\r
1610 // Program PMem64 resources\r
1611 //\r
1612 ProgramResource (\r
1613 PMem64Base,\r
1614 PMem64Bridge\r
1615 );\r
1616\r
1617 DestroyResourceTree (IoBridge);\r
1618 DestroyResourceTree (Mem32Bridge);\r
1619 DestroyResourceTree (PMem32Bridge);\r
1620 DestroyResourceTree (PMem64Bridge);\r
1621 DestroyResourceTree (Mem64Bridge);\r
1622\r
1623 gBS->FreePool (IoBridge);\r
1624 gBS->FreePool (Mem32Bridge);\r
1625 gBS->FreePool (PMem32Bridge);\r
1626 gBS->FreePool (PMem64Bridge);\r
1627 gBS->FreePool (Mem64Bridge);\r
1628\r
1629 return EFI_SUCCESS;\r
1630}\r
1631\r
1632/**\r
1633 Get resource base address for a pci bridge device.\r
1634\r
1635 @param Bridge Given Pci driver instance.\r
1636 @param IoBase Output for base address of I/O type resource.\r
1637 @param Mem32Base Output for base address of 32-bit memory type resource.\r
1638 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r
1639 @param Mem64Base Output for base address of 64-bit memory type resource.\r
1640 @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r
1641\r
1642 @retval EFI_SUCCESS Successfully got resource base address.\r
1643 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.\r
1644\r
1645**/\r
1646EFI_STATUS\r
1647GetResourceBaseFromBridge (\r
1648 IN PCI_IO_DEVICE *Bridge,\r
1649 OUT UINT64 *IoBase,\r
1650 OUT UINT64 *Mem32Base,\r
1651 OUT UINT64 *PMem32Base,\r
1652 OUT UINT64 *Mem64Base,\r
1653 OUT UINT64 *PMem64Base\r
1654 )\r
1655{\r
1656 if (!Bridge->Allocated) {\r
1657 return EFI_OUT_OF_RESOURCES;\r
1658 }\r
1659\r
1660 *IoBase = gAllOne;\r
1661 *Mem32Base = gAllOne;\r
1662 *PMem32Base = gAllOne;\r
1663 *Mem64Base = gAllOne;\r
1664 *PMem64Base = gAllOne;\r
1665\r
1666 if (IS_PCI_BRIDGE (&Bridge->Pci)) {\r
1667\r
1668 if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {\r
1669 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;\r
1670 }\r
1671\r
1672 if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {\r
1673 *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;\r
1674 }\r
1675\r
1676 if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {\r
1677 *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;\r
1678 }\r
1679\r
1680 if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {\r
1681 *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;\r
1682 } else {\r
1683 *PMem64Base = gAllOne;\r
1684 }\r
1685\r
1686 }\r
1687\r
1688 if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {\r
1689 if (Bridge->PciBar[P2C_IO_1].Length > 0) {\r
1690 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;\r
1691 } else {\r
1692 if (Bridge->PciBar[P2C_IO_2].Length > 0) {\r
1693 *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;\r
1694 }\r
1695 }\r
1696\r
1697 if (Bridge->PciBar[P2C_MEM_1].Length > 0) {\r
1698 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {\r
1699 *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1700 }\r
1701\r
1702 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {\r
1703 *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1704 }\r
1705 }\r
1706\r
1707 if (Bridge->PciBar[P2C_MEM_2].Length > 0) {\r
1708 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {\r
1709 *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1710 }\r
1711\r
1712 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {\r
1713 *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1714 }\r
1715 }\r
1716 }\r
1717\r
1718 return EFI_SUCCESS;\r
1719}\r
1720\r
1721/**\r
1722 These are the notifications from the PCI bus driver that it is about to enter a certain\r
1723 phase of the PCI enumeration process.\r
1724\r
1725 This member function can be used to notify the host bridge driver to perform specific actions,\r
1726 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
1727 Eight notification points are defined at this time. See belows:\r
1728 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
1729 structures. The PCI enumerator should issue this notification\r
1730 before starting a fresh enumeration process. Enumeration cannot\r
1731 be restarted after sending any other notification such as\r
1732 EfiPciHostBridgeBeginBusAllocation.\r
1733 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
1734 required here. This notification can be used to perform any\r
1735 chipset-specific programming.\r
1736 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
1737 specific action is required here. This notification can be used to\r
1738 perform any chipset-specific programming.\r
1739 EfiPciHostBridgeBeginResourceAllocation\r
1740 The resource allocation phase is about to begin. No specific\r
1741 action is required here. This notification can be used to perform\r
1742 any chipset-specific programming.\r
1743 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
1744 root bridges. These resource settings are returned on the next call to\r
1745 GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
1746 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
1747 for gathering I/O and memory requests for\r
1748 all the PCI root bridges and submitting these requests using\r
1749 SubmitResources(). This function pads the resource amount\r
1750 to suit the root bridge hardware, takes care of dependencies between\r
1751 the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
1752 with the allocation request. In the case of padding, the allocated range\r
1753 could be bigger than what was requested.\r
1754 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
1755 resources (proposed resources) for all the PCI root bridges. After the\r
1756 hardware is programmed, reassigning resources will not be supported.\r
1757 The bus settings are not affected.\r
1758 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
1759 root bridges and resets the I/O and memory apertures to their initial\r
1760 state. The bus settings are not affected. If the request to allocate\r
1761 resources fails, the PCI enumerator can use this notification to\r
1762 deallocate previous resources, adjust the requests, and retry\r
1763 allocation.\r
1764 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
1765 required here. This notification can be used to perform any chipsetspecific\r
1766 programming.\r
1767\r
1768 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
1769 @param[in] Phase The phase during enumeration\r
1770\r
1771 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
1772 is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
1773 SubmitResources() has not been called for one or more\r
1774 PCI root bridges before this call\r
1775 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
1776 for a Phase of EfiPciHostBridgeSetResources.\r
1777 @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
1778 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1779 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
1780 previously submitted resource requests cannot be fulfilled or\r
1781 were only partially fulfilled.\r
1782 @retval EFI_SUCCESS The notification was accepted without any errors.\r
1783\r
1784**/\r
1785EFI_STATUS\r
1786NotifyPhase (\r
1787 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
1788 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
1789 )\r
1790{\r
1791 EFI_HANDLE HostBridgeHandle;\r
1792 EFI_HANDLE RootBridgeHandle;\r
1793 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
1794 EFI_STATUS Status;\r
1795\r
1796 HostBridgeHandle = NULL;\r
1797 RootBridgeHandle = NULL;\r
1798 if (gPciPlatformProtocol != NULL) {\r
1799 //\r
1800 // Get Host Bridge Handle.\r
1801 //\r
1802 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
1803\r
1804 //\r
1805 // Get the rootbridge Io protocol to find the host bridge handle\r
1806 //\r
1807 Status = gBS->HandleProtocol (\r
1808 RootBridgeHandle,\r
1809 &gEfiPciRootBridgeIoProtocolGuid,\r
1810 (VOID **) &PciRootBridgeIo\r
1811 );\r
1812\r
1813 if (EFI_ERROR (Status)) {\r
1814 return EFI_NOT_FOUND;\r
1815 }\r
1816\r
1817 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
1818\r
1819 //\r
1820 // Call PlatformPci::PlatformNotify() if the protocol is present.\r
1821 //\r
1822 gPciPlatformProtocol->PlatformNotify (\r
1823 gPciPlatformProtocol,\r
1824 HostBridgeHandle,\r
1825 Phase,\r
1826 ChipsetEntry\r
1827 );\r
1828 } else if (gPciOverrideProtocol != NULL){\r
1829 //\r
1830 // Get Host Bridge Handle.\r
1831 //\r
1832 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
1833\r
1834 //\r
1835 // Get the rootbridge Io protocol to find the host bridge handle\r
1836 //\r
1837 Status = gBS->HandleProtocol (\r
1838 RootBridgeHandle,\r
1839 &gEfiPciRootBridgeIoProtocolGuid,\r
1840 (VOID **) &PciRootBridgeIo\r
1841 );\r
1842\r
1843 if (EFI_ERROR (Status)) {\r
1844 return EFI_NOT_FOUND;\r
1845 }\r
1846\r
1847 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
1848\r
1849 //\r
1850 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1851 //\r
1852 gPciOverrideProtocol->PlatformNotify (\r
1853 gPciOverrideProtocol,\r
1854 HostBridgeHandle,\r
1855 Phase,\r
1856 ChipsetEntry\r
1857 );\r
1858 } \r
1859\r
1860 Status = PciResAlloc->NotifyPhase (\r
1861 PciResAlloc,\r
1862 Phase\r
1863 );\r
1864\r
1865 if (gPciPlatformProtocol != NULL) {\r
1866 //\r
1867 // Call PlatformPci::PlatformNotify() if the protocol is present.\r
1868 //\r
1869 gPciPlatformProtocol->PlatformNotify (\r
1870 gPciPlatformProtocol,\r
1871 HostBridgeHandle,\r
1872 Phase,\r
1873 ChipsetExit\r
1874 );\r
1875\r
1876 } else if (gPciOverrideProtocol != NULL) {\r
1877 //\r
1878 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1879 //\r
1880 gPciOverrideProtocol->PlatformNotify (\r
1881 gPciOverrideProtocol,\r
1882 HostBridgeHandle,\r
1883 Phase,\r
1884 ChipsetExit\r
1885 );\r
1886 }\r
1887\r
724f26a9 1888 return Status;\r
9060e3ec 1889}\r
1890\r
1891/**\r
1892 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
1893 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
1894 PCI controllers before enumeration.\r
1895\r
1896 This function is called during the PCI enumeration process. No specific action is expected from this\r
1897 member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
1898 enumeration.\r
1899\r
1900 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
1901 @param Bus The bus number of the pci device.\r
1902 @param Device The device number of the pci device.\r
1903 @param Func The function number of the pci device.\r
1904 @param Phase The phase of the PCI device enumeration.\r
1905\r
1906 @retval EFI_SUCCESS The requested parameters were returned.\r
1907 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
1908 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
1909 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
1910 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
1911 not enumerate this device, including its child devices if it is a PCI-to-PCI\r
1912 bridge.\r
1913\r
1914**/\r
1915EFI_STATUS\r
1916PreprocessController (\r
1917 IN PCI_IO_DEVICE *Bridge,\r
1918 IN UINT8 Bus,\r
1919 IN UINT8 Device,\r
1920 IN UINT8 Func,\r
1921 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
1922 )\r
1923{\r
1924 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;\r
1925 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
1926 EFI_HANDLE RootBridgeHandle;\r
1927 EFI_HANDLE HostBridgeHandle;\r
1928 EFI_STATUS Status;\r
1929\r
1930 //\r
1931 // Get the host bridge handle\r
1932 //\r
1933 HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;\r
1934\r
1935 //\r
1936 // Get the pci host bridge resource allocation protocol\r
1937 //\r
1938 Status = gBS->OpenProtocol (\r
1939 HostBridgeHandle,\r
1940 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
1941 (VOID **) &PciResAlloc,\r
1942 NULL,\r
1943 NULL,\r
1944 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
1945 );\r
1946\r
1947 if (EFI_ERROR (Status)) {\r
1948 return EFI_UNSUPPORTED;\r
1949 }\r
1950\r
1951 //\r
1952 // Get Root Brige Handle\r
1953 //\r
1954 while (Bridge->Parent != NULL) {\r
1955 Bridge = Bridge->Parent;\r
1956 }\r
1957\r
1958 RootBridgeHandle = Bridge->Handle;\r
1959\r
1960 RootBridgePciAddress.Register = 0;\r
1961 RootBridgePciAddress.Function = Func;\r
1962 RootBridgePciAddress.Device = Device;\r
1963 RootBridgePciAddress.Bus = Bus;\r
1964 RootBridgePciAddress.ExtendedRegister = 0;\r
1965\r
1966 if (gPciPlatformProtocol != NULL) {\r
1967 //\r
1968 // Call PlatformPci::PrepController() if the protocol is present.\r
1969 //\r
1970 gPciPlatformProtocol->PlatformPrepController (\r
1971 gPciPlatformProtocol,\r
1972 HostBridgeHandle,\r
1973 RootBridgeHandle,\r
1974 RootBridgePciAddress,\r
1975 Phase,\r
1976 ChipsetEntry\r
1977 );\r
1978 } else if (gPciOverrideProtocol != NULL) {\r
1979 //\r
1980 // Call PlatformPci::PrepController() if the protocol is present.\r
1981 //\r
1982 gPciOverrideProtocol->PlatformPrepController (\r
1983 gPciOverrideProtocol,\r
1984 HostBridgeHandle,\r
1985 RootBridgeHandle,\r
1986 RootBridgePciAddress,\r
1987 Phase,\r
1988 ChipsetEntry\r
1989 );\r
1990 }\r
1991\r
1992 Status = PciResAlloc->PreprocessController (\r
1993 PciResAlloc,\r
1994 RootBridgeHandle,\r
1995 RootBridgePciAddress,\r
1996 Phase\r
1997 );\r
1998\r
1999 if (gPciPlatformProtocol != NULL) {\r
2000 //\r
2001 // Call PlatformPci::PrepController() if the protocol is present.\r
2002 //\r
2003 gPciPlatformProtocol->PlatformPrepController (\r
2004 gPciPlatformProtocol,\r
2005 HostBridgeHandle,\r
2006 RootBridgeHandle,\r
2007 RootBridgePciAddress,\r
2008 Phase,\r
2009 ChipsetExit\r
2010 );\r
2011 } else if (gPciOverrideProtocol != NULL) {\r
2012 //\r
2013 // Call PlatformPci::PrepController() if the protocol is present.\r
2014 //\r
2015 gPciOverrideProtocol->PlatformPrepController (\r
2016 gPciOverrideProtocol,\r
2017 HostBridgeHandle,\r
2018 RootBridgeHandle,\r
2019 RootBridgePciAddress,\r
2020 Phase,\r
2021 ChipsetExit\r
2022 );\r
2023 }\r
2024\r
2025 return EFI_SUCCESS;\r
2026}\r
2027\r
2028/**\r
2029 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r
2030 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r
2031\r
2032 @param This A pointer to the hot plug request protocol.\r
2033 @param Operation The operation the PCI bus driver is requested to make.\r
2034 @param Controller The handle of the hot-plug controller.\r
2035 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.\r
2036 @param NumberOfChildren The number of child handles.\r
2037 For a add operation, it is an output parameter.\r
2038 For a remove operation, it's an input parameter.\r
2039 @param ChildHandleBuffer The buffer which contains the child handles.\r
2040\r
2041 @retval EFI_INVALID_PARAMETER Operation is not a legal value.\r
2042 Controller is NULL or not a valid handle.\r
2043 NumberOfChildren is NULL.\r
2044 ChildHandleBuffer is NULL while Operation is add.\r
2045 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.\r
2046 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
2047 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed\r
2048 as requested, and for an add operation, the new handles are\r
2049 returned in ChildHandleBuffer.\r
2050**/\r
2051EFI_STATUS\r
2052EFIAPI\r
2053PciHotPlugRequestNotify (\r
2054 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,\r
2055 IN EFI_PCI_HOTPLUG_OPERATION Operation,\r
2056 IN EFI_HANDLE Controller,\r
2057 IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,\r
2058 IN OUT UINT8 *NumberOfChildren,\r
2059 IN OUT EFI_HANDLE * ChildHandleBuffer\r
2060 )\r
2061{\r
2062 PCI_IO_DEVICE *Bridge;\r
2063 PCI_IO_DEVICE *Temp;\r
2064 EFI_PCI_IO_PROTOCOL *PciIo;\r
2065 UINTN Index;\r
2066 EFI_HANDLE RootBridgeHandle;\r
2067 EFI_STATUS Status;\r
2068\r
2069 //\r
2070 // Check input parameter validity\r
2071 //\r
2072 if ((Controller == NULL) || (NumberOfChildren == NULL)){\r
2073 return EFI_INVALID_PARAMETER;\r
2074 }\r
2075\r
2076 if ((Operation != EfiPciHotPlugRequestAdd) && (Operation != EfiPciHotplugRequestRemove)) {\r
2077 return EFI_INVALID_PARAMETER;\r
2078 }\r
2079\r
2080 if (Operation == EfiPciHotPlugRequestAdd){\r
2081 if (ChildHandleBuffer == NULL) {\r
2082 return EFI_INVALID_PARAMETER;\r
2083 }\r
2084 } else if ((Operation == EfiPciHotplugRequestRemove) && (*NumberOfChildren != 0)) {\r
2085 if (ChildHandleBuffer == NULL) {\r
2086 return EFI_INVALID_PARAMETER;\r
2087 }\r
2088 }\r
2089 \r
2090 Status = gBS->OpenProtocol (\r
2091 Controller,\r
2092 &gEfiPciIoProtocolGuid,\r
2093 (VOID **) &PciIo,\r
2094 gPciBusDriverBinding.DriverBindingHandle,\r
2095 Controller,\r
2096 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
2097 );\r
2098\r
2099 if (EFI_ERROR (Status)) {\r
2100 return EFI_NOT_FOUND;\r
2101 }\r
2102\r
2103 Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
2104\r
2105 //\r
2106 // Get root bridge handle\r
2107 //\r
2108 Temp = Bridge;\r
2109 while (Temp->Parent != NULL) {\r
2110 Temp = Temp->Parent;\r
2111 }\r
2112\r
2113 RootBridgeHandle = Temp->Handle;\r
2114\r
2115 if (Operation == EfiPciHotPlugRequestAdd) {\r
37623a5c 2116 //\r
2117 // Report Status Code to indicate hot plug happens\r
2118 //\r
2119 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
2120 EFI_PROGRESS_CODE,\r
2121 (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),\r
2122 Temp->DevicePath\r
2123 );\r
9060e3ec 2124\r
2125 if (NumberOfChildren != NULL) {\r
2126 *NumberOfChildren = 0;\r
2127 }\r
2128\r
2129 if (IsListEmpty (&Bridge->ChildList)) {\r
2130\r
2131 Status = PciBridgeEnumerator (Bridge);\r
2132\r
2133 if (EFI_ERROR (Status)) {\r
2134 return Status;\r
2135 }\r
2136 }\r
2137\r
2138 Status = StartPciDevicesOnBridge (\r
2139 RootBridgeHandle,\r
2140 Bridge,\r
2141 RemainingDevicePath,\r
2142 NumberOfChildren,\r
2143 ChildHandleBuffer\r
2144 );\r
2145\r
2146 return Status;\r
2147 }\r
2148\r
2149 if (Operation == EfiPciHotplugRequestRemove) {\r
2150\r
2151 if (*NumberOfChildren == 0) {\r
2152 //\r
2153 // Remove all devices on the bridge\r
2154 //\r
2155 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);\r
2156 return EFI_SUCCESS;\r
2157\r
2158 }\r
2159\r
2160 for (Index = 0; Index < *NumberOfChildren; Index++) {\r
2161 //\r
2162 // De register all the pci device\r
2163 //\r
2164 Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);\r
2165\r
2166 if (EFI_ERROR (Status)) {\r
2167 return Status;\r
2168 }\r
2169\r
2170 }\r
2171 //\r
2172 // End for\r
2173 //\r
2174 return EFI_SUCCESS;\r
2175 }\r
2176\r
2177 return EFI_SUCCESS;\r
2178}\r
2179\r
2180/**\r
2181 Search hostbridge according to given handle\r
2182\r
2183 @param RootBridgeHandle Host bridge handle.\r
2184\r
2185 @retval TRUE Found host bridge handle.\r
2186 @retval FALSE Not found hot bridge handle.\r
2187\r
2188**/\r
2189BOOLEAN\r
2190SearchHostBridgeHandle (\r
2191 IN EFI_HANDLE RootBridgeHandle\r
2192 )\r
2193{\r
2194 EFI_HANDLE HostBridgeHandle;\r
2195 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
2196 UINTN Index;\r
2197 EFI_STATUS Status;\r
2198\r
2199 //\r
2200 // Get the rootbridge Io protocol to find the host bridge handle\r
2201 //\r
2202 Status = gBS->OpenProtocol (\r
2203 RootBridgeHandle,\r
2204 &gEfiPciRootBridgeIoProtocolGuid,\r
2205 (VOID **) &PciRootBridgeIo,\r
2206 gPciBusDriverBinding.DriverBindingHandle,\r
2207 RootBridgeHandle,\r
2208 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
2209 );\r
2210\r
2211 if (EFI_ERROR (Status)) {\r
2212 return FALSE;\r
2213 }\r
2214\r
2215 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
2216 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2217 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2218 return TRUE;\r
2219 }\r
2220 }\r
2221\r
2222 return FALSE;\r
2223}\r
2224\r
2225/**\r
2226 Add host bridge handle to global variable for enumerating.\r
2227\r
2228 @param HostBridgeHandle Host bridge handle.\r
2229\r
2230 @retval EFI_SUCCESS Successfully added host bridge.\r
2231 @retval EFI_ABORTED Host bridge is NULL, or given host bridge\r
2232 has been in host bridge list.\r
2233\r
2234**/\r
2235EFI_STATUS\r
2236AddHostBridgeEnumerator (\r
2237 IN EFI_HANDLE HostBridgeHandle\r
2238 )\r
2239{\r
2240 UINTN Index;\r
2241\r
2242 if (HostBridgeHandle == NULL) {\r
2243 return EFI_ABORTED;\r
2244 }\r
2245\r
2246 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2247 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2248 return EFI_ABORTED;\r
2249 }\r
2250 }\r
2251\r
2252 if (Index < PCI_MAX_HOST_BRIDGE_NUM) {\r
2253 gPciHostBrigeHandles[Index] = HostBridgeHandle;\r
2254 gPciHostBridgeNumber++;\r
2255 }\r
2256\r
2257 return EFI_SUCCESS;\r
2258}\r
2259\r
EFI Development Kit II mirror for PVE