[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciLib.c

/** @file\r
  Internal library implementation for PCI Bus module.\r
\r
Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "PciBus.h"\r
\r
GLOBAL_REMOVE_IF_UNREFERENCED\r
CHAR16  *mBarTypeStr[] = {\r
  L"Unknow",\r
  L"  Io16",\r
  L"  Io32",\r
  L" Mem32",\r
  L"PMem32",\r
  L" Mem64",\r
  L"PMem64",\r
  L" OpRom",\r
  L"    Io",\r
  L"   Mem",\r
  L"Unknow"\r
};\r
\r
/**\r
  Retrieve the max bus number that is assigned to the Root Bridge hierarchy.\r
  It can support the case that there are multiple bus ranges.\r
\r
  @param  Bridge           Bridge device instance.\r
\r
  @retval                  The max bus number that is assigned to this Root Bridge hierarchy.\r
\r
**/\r
UINT16\r
PciGetMaxBusNumber (\r
  IN PCI_IO_DEVICE  *Bridge\r
  )\r
{\r
  PCI_IO_DEVICE                      *RootBridge;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *BusNumberRanges;\r
  UINT64                             MaxNumberInRange;\r
\r
  //\r
  // Get PCI Root Bridge device\r
  //\r
  RootBridge = Bridge;\r
  while (RootBridge->Parent != NULL) {\r
    RootBridge = RootBridge->Parent;\r
  }\r
\r
  MaxNumberInRange = 0;\r
  //\r
  // Iterate the bus number ranges to get max PCI bus number\r
  //\r
  BusNumberRanges = RootBridge->BusNumberRanges;\r
  while (BusNumberRanges->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
    MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;\r
    BusNumberRanges++;\r
  }\r
\r
  return (UINT16)MaxNumberInRange;\r
}\r
\r
/**\r
  Retrieve the PCI Card device BAR information via PciIo interface.\r
\r
  @param PciIoDevice        PCI Card device instance.\r
\r
**/\r
VOID\r
GetBackPcCardBar (\r
  IN  PCI_IO_DEVICE  *PciIoDevice\r
  )\r
{\r
  UINT32  Address;\r
\r
  if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
    return;\r
  }\r
\r
  //\r
  // Read PciBar information from the bar register\r
  //\r
  if (!gFullEnumeration) {\r
    Address = 0;\r
    PciIoDevice->PciIo.Pci.Read (\r
                             &(PciIoDevice->PciIo),\r
                             EfiPciIoWidthUint32,\r
                             PCI_CARD_MEMORY_BASE_0,\r
                             1,\r
                             &Address\r
                             );\r
\r
    (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64)(Address);\r
    (PciIoDevice->PciBar)[P2C_MEM_1].Length      = 0x2000000;\r
    (PciIoDevice->PciBar)[P2C_MEM_1].BarType     = PciBarTypeMem32;\r
\r
    Address = 0;\r
    PciIoDevice->PciIo.Pci.Read (\r
                             &(PciIoDevice->PciIo),\r
                             EfiPciIoWidthUint32,\r
                             PCI_CARD_MEMORY_BASE_1,\r
                             1,\r
                             &Address\r
                             );\r
    (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64)(Address);\r
    (PciIoDevice->PciBar)[P2C_MEM_2].Length      = 0x2000000;\r
    (PciIoDevice->PciBar)[P2C_MEM_2].BarType     = PciBarTypePMem32;\r
\r
    Address = 0;\r
    PciIoDevice->PciIo.Pci.Read (\r
                             &(PciIoDevice->PciIo),\r
                             EfiPciIoWidthUint32,\r
                             PCI_CARD_IO_BASE_0_LOWER,\r
                             1,\r
                             &Address\r
                             );\r
    (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64)(Address);\r
    (PciIoDevice->PciBar)[P2C_IO_1].Length      = 0x100;\r
    (PciIoDevice->PciBar)[P2C_IO_1].BarType     = PciBarTypeIo16;\r
\r
    Address = 0;\r
    PciIoDevice->PciIo.Pci.Read (\r
                             &(PciIoDevice->PciIo),\r
                             EfiPciIoWidthUint32,\r
                             PCI_CARD_IO_BASE_1_LOWER,\r
                             1,\r
                             &Address\r
                             );\r
    (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64)(Address);\r
    (PciIoDevice->PciBar)[P2C_IO_2].Length      = 0x100;\r
    (PciIoDevice->PciBar)[P2C_IO_2].BarType     = PciBarTypeIo16;\r
  }\r
\r
  if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
    GetResourcePaddingForHpb (PciIoDevice);\r
  }\r
}\r
\r
/**\r
  Remove rejected pci device from specific root bridge\r
  handle.\r
\r
  @param RootBridgeHandle  Specific parent root bridge handle.\r
  @param Bridge            Bridge device instance.\r
\r
**/\r
VOID\r
RemoveRejectedPciDevices (\r
  IN EFI_HANDLE     RootBridgeHandle,\r
  IN PCI_IO_DEVICE  *Bridge\r
  )\r
{\r
  PCI_IO_DEVICE  *Temp;\r
  LIST_ENTRY     *CurrentLink;\r
  LIST_ENTRY     *LastLink;\r
\r
  if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
    return;\r
  }\r
\r
  CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
\r
    if (IS_PCI_BRIDGE (&Temp->Pci)) {\r
      //\r
      // Remove rejected devices recusively\r
      //\r
      RemoveRejectedPciDevices (RootBridgeHandle, Temp);\r
    } else {\r
      //\r
      // Skip rejection for all PPBs, while detect rejection for others\r
      //\r
      if (IsPciDeviceRejected (Temp)) {\r
        //\r
        // For P2C, remove all devices on it\r
        //\r
        if (!IsListEmpty (&Temp->ChildList)) {\r
          RemoveAllPciDeviceOnBridge (RootBridgeHandle, Temp);\r
        }\r
\r
        //\r
        // Finally remove itself\r
        //\r
        LastLink = CurrentLink->BackLink;\r
        RemoveEntryList (CurrentLink);\r
        FreePciDevice (Temp);\r
\r
        CurrentLink = LastLink;\r
      }\r
    }\r
\r
    CurrentLink = CurrentLink->ForwardLink;\r
  }\r
}\r
\r
/**\r
  Dump the resourc map of the bridge device.\r
\r
  @param[in] BridgeResource   Resource descriptor of the bridge device.\r
**/\r
VOID\r
DumpBridgeResource (\r
  IN PCI_RESOURCE_NODE  *BridgeResource\r
  )\r
{\r
  LIST_ENTRY         *Link;\r
  PCI_RESOURCE_NODE  *Resource;\r
  PCI_BAR            *Bar;\r
\r
  if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",\r
      mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],\r
      BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,\r
      BridgeResource->Length,\r
      BridgeResource->Alignment\r
      ));\r
    for ( Link = GetFirstNode (&BridgeResource->ChildList)\r
          ; !IsNull (&BridgeResource->ChildList, Link)\r
          ; Link = GetNextNode (&BridgeResource->ChildList, Link)\r
          )\r
    {\r
      Resource = RESOURCE_NODE_FROM_LINK (Link);\r
      if (Resource->ResourceUsage == PciResUsageTypical) {\r
        Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;\r
        DEBUG ((\r
          DEBUG_INFO,\r
          "   Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s [%02x|%02x|%02x:",\r
          Bar[Resource->Bar].BaseAddress,\r
          Resource->Length,\r
          Resource->Alignment,\r
          IS_PCI_BRIDGE (&Resource->PciDev->Pci)     ? L"PPB" :\r
          IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :\r
          L"PCI",\r
          Resource->PciDev->BusNumber,\r
          Resource->PciDev->DeviceNumber,\r
          Resource->PciDev->FunctionNumber\r
          ));\r
\r
        if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||\r
            (IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||\r
            (IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))\r
            )\r
        {\r
          //\r
          // The resource requirement comes from the device itself.\r
          //\r
          DEBUG ((DEBUG_INFO, "%02x]", Bar[Resource->Bar].Offset));\r
        } else {\r
          //\r
          // The resource requirement comes from the subordinate devices.\r
          //\r
          DEBUG ((DEBUG_INFO, "**]"));\r
        }\r
      } else {\r
        DEBUG ((DEBUG_INFO, "   Base = Padding;\tLength = 0x%lx;\tAlignment = 0x%lx", Resource->Length, Resource->Alignment));\r
      }\r
\r
      if (BridgeResource->ResType != Resource->ResType) {\r
        DEBUG ((DEBUG_INFO, "; Type = %s", mBarTypeStr[MIN (Resource->ResType, PciBarTypeMaxType)]));\r
      }\r
\r
      DEBUG ((DEBUG_INFO, "\n"));\r
    }\r
  }\r
}\r
\r
/**\r
  Find the corresponding resource node for the Device in child list of BridgeResource.\r
\r
  @param[in]  Device          Pointer to PCI_IO_DEVICE.\r
  @param[in]  BridgeResource  Pointer to PCI_RESOURCE_NODE.\r
  @param[out] DeviceResources Pointer to a buffer to receive resources for the Device.\r
\r
  @return Count of the resource descriptors returned.\r
**/\r
UINTN\r
FindResourceNode (\r
  IN  PCI_IO_DEVICE      *Device,\r
  IN  PCI_RESOURCE_NODE  *BridgeResource,\r
  OUT PCI_RESOURCE_NODE  **DeviceResources OPTIONAL\r
  )\r
{\r
  LIST_ENTRY         *Link;\r
  PCI_RESOURCE_NODE  *Resource;\r
  UINTN              Count;\r
\r
  Count = 0;\r
  for ( Link = BridgeResource->ChildList.ForwardLink\r
        ; Link != &BridgeResource->ChildList\r
        ; Link = Link->ForwardLink\r
        )\r
  {\r
    Resource = RESOURCE_NODE_FROM_LINK (Link);\r
    if (Resource->PciDev == Device) {\r
      if (DeviceResources != NULL) {\r
        DeviceResources[Count] = Resource;\r
      }\r
\r
      Count++;\r
    }\r
  }\r
\r
  return Count;\r
}\r
\r
/**\r
  Dump the resource map of all the devices under Bridge.\r
\r
  @param[in] Bridge        Bridge device instance.\r
  @param[in] Resources     Resource descriptors for the bridge device.\r
  @param[in] ResourceCount Count of resource descriptors.\r
**/\r
VOID\r
DumpResourceMap (\r
  IN PCI_IO_DEVICE      *Bridge,\r
  IN PCI_RESOURCE_NODE  **Resources,\r
  IN UINTN              ResourceCount\r
  )\r
{\r
  EFI_STATUS         Status;\r
  LIST_ENTRY         *Link;\r
  PCI_IO_DEVICE      *Device;\r
  UINTN              Index;\r
  CHAR16             *Str;\r
  PCI_RESOURCE_NODE  **ChildResources;\r
  UINTN              ChildResourceCount;\r
\r
  DEBUG ((DEBUG_INFO, "PciBus: Resource Map for "));\r
\r
  Status = gBS->OpenProtocol (\r
                  Bridge->Handle,\r
                  &gEfiPciRootBridgeIoProtocolGuid,\r
                  NULL,\r
                  NULL,\r
                  NULL,\r
                  EFI_OPEN_PROTOCOL_TEST_PROTOCOL\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "Bridge [%02x|%02x|%02x]\n",\r
      Bridge->BusNumber,\r
      Bridge->DeviceNumber,\r
      Bridge->FunctionNumber\r
      ));\r
  } else {\r
    Str = ConvertDevicePathToText (\r
            DevicePathFromHandle (Bridge->Handle),\r
            FALSE,\r
            FALSE\r
            );\r
    DEBUG ((DEBUG_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));\r
    if (Str != NULL) {\r
      FreePool (Str);\r
    }\r
  }\r
\r
  for (Index = 0; Index < ResourceCount; Index++) {\r
    DumpBridgeResource (Resources[Index]);\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "\n"));\r
\r
  for ( Link = Bridge->ChildList.ForwardLink\r
        ; Link != &Bridge->ChildList\r
        ; Link = Link->ForwardLink\r
        )\r
  {\r
    Device = PCI_IO_DEVICE_FROM_LINK (Link);\r
    if (IS_PCI_BRIDGE (&Device->Pci)) {\r
      ChildResourceCount = 0;\r
      for (Index = 0; Index < ResourceCount; Index++) {\r
        ChildResourceCount += FindResourceNode (Device, Resources[Index], NULL);\r
      }\r
\r
      ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * ChildResourceCount);\r
      ASSERT (ChildResources != NULL);\r
      ChildResourceCount = 0;\r
      for (Index = 0; Index < ResourceCount; Index++) {\r
        ChildResourceCount += FindResourceNode (Device, Resources[Index], &ChildResources[ChildResourceCount]);\r
      }\r
\r
      DumpResourceMap (Device, ChildResources, ChildResourceCount);\r
      FreePool (ChildResources);\r
    }\r
  }\r
}\r
\r
/**\r
  Adjust the Devices' BAR size to minimum value if it support Resizeable BAR capability.\r
\r
  @param RootBridgeDev  Pointer to instance of PCI_IO_DEVICE..\r
\r
  @return TRUE if BAR size is adjusted.\r
\r
**/\r
BOOLEAN\r
AdjustPciDeviceBarSize (\r
  IN PCI_IO_DEVICE  *RootBridgeDev\r
  )\r
{\r
  PCI_IO_DEVICE  *PciIoDevice;\r
  LIST_ENTRY     *CurrentLink;\r
  BOOLEAN        Adjusted;\r
  UINTN          Offset;\r
  UINTN          BarIndex;\r
\r
  Adjusted    = FALSE;\r
  CurrentLink = RootBridgeDev->ChildList.ForwardLink;\r
\r
  while (CurrentLink != NULL && CurrentLink != &RootBridgeDev->ChildList) {\r
    PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
\r
    if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
      if (AdjustPciDeviceBarSize (PciIoDevice)) {\r
        Adjusted = TRUE;\r
      }\r
    } else {\r
      if (PciIoDevice->ResizableBarOffset != 0) {\r
        DEBUG ((\r
          DEBUG_ERROR,\r
          "PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar Size\n",\r
          PciIoDevice->BusNumber,\r
          PciIoDevice->DeviceNumber,\r
          PciIoDevice->FunctionNumber\r
          ));\r
        PciProgramResizableBar (PciIoDevice, PciResizableBarMin);\r
        //\r
        // Start to parse the bars\r
        //\r
        for (Offset = 0x10, BarIndex = 0; Offset <= 0x24 && BarIndex < PCI_MAX_BAR; BarIndex++) {\r
          Offset = PciParseBar (PciIoDevice, Offset, BarIndex);\r
        }\r
\r
        Adjusted = TRUE;\r
        DEBUG_CODE (\r
          DumpPciBars (PciIoDevice);\r
          );\r
      }\r
    }\r
\r
    CurrentLink = CurrentLink->ForwardLink;\r
  }\r
\r
  return Adjusted;\r
}\r
\r
/**\r
  Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
\r
  @param PciResAlloc  Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
\r
  @retval EFI_SUCCESS           Successfully finished resource allocation.\r
  @retval EFI_NOT_FOUND         Cannot get root bridge instance.\r
  @retval EFI_OUT_OF_RESOURCES  Platform failed to program the resources if no hot plug supported.\r
  @retval other                 Some error occurred when allocating resources for the PCI Host Bridge.\r
\r
  @note   Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeResourceAllocator (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc\r
  )\r
{\r
  PCI_IO_DEVICE                                  *RootBridgeDev;\r
  EFI_HANDLE                                     RootBridgeHandle;\r
  VOID                                           *AcpiConfig;\r
  EFI_STATUS                                     Status;\r
  UINT64                                         IoBase;\r
  UINT64                                         Mem32Base;\r
  UINT64                                         PMem32Base;\r
  UINT64                                         Mem64Base;\r
  UINT64                                         PMem64Base;\r
  UINT64                                         IoResStatus;\r
  UINT64                                         Mem32ResStatus;\r
  UINT64                                         PMem32ResStatus;\r
  UINT64                                         Mem64ResStatus;\r
  UINT64                                         PMem64ResStatus;\r
  UINT32                                         MaxOptionRomSize;\r
  PCI_RESOURCE_NODE                              *IoBridge;\r
  PCI_RESOURCE_NODE                              *Mem32Bridge;\r
  PCI_RESOURCE_NODE                              *PMem32Bridge;\r
  PCI_RESOURCE_NODE                              *Mem64Bridge;\r
  PCI_RESOURCE_NODE                              *PMem64Bridge;\r
  PCI_RESOURCE_NODE                              IoPool;\r
  PCI_RESOURCE_NODE                              Mem32Pool;\r
  PCI_RESOURCE_NODE                              PMem32Pool;\r
  PCI_RESOURCE_NODE                              Mem64Pool;\r
  PCI_RESOURCE_NODE                              PMem64Pool;\r
  EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD        HandleExtendedData;\r
  EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD  AllocFailExtendedData;\r
  BOOLEAN                                        ResizableBarNeedAdjust;\r
  BOOLEAN                                        ResizableBarAdjusted;\r
\r
  ResizableBarNeedAdjust = PcdGetBool (PcdPcieResizableBarSupport);\r
\r
  //\r
  // It may try several times if the resource allocation fails\r
  //\r
  while (TRUE) {\r
    //\r
    // Initialize resource pool\r
    //\r
    InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
    InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
    InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
    InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
    InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
\r
    RootBridgeDev    = NULL;\r
    RootBridgeHandle = 0;\r
\r
    while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
      //\r
      // Get Root Bridge Device by handle\r
      //\r
      RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
\r
      if (RootBridgeDev == NULL) {\r
        return EFI_NOT_FOUND;\r
      }\r
\r
      //\r
      // Create the entire system resource map from the information collected by\r
      // enumerator. Several resource tree was created\r
      //\r
\r
      //\r
      // If non-standard PCI Bridge I/O window alignment is supported,\r
      // set I/O aligment to minimum possible alignment for root bridge.\r
      //\r
      IoBridge = CreateResourceNode (\r
                   RootBridgeDev,\r
                   0,\r
                   FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF : 0xFFF,\r
                   RB_IO_RANGE,\r
                   PciBarTypeIo16,\r
                   PciResUsageTypical\r
                   );\r
\r
      Mem32Bridge = CreateResourceNode (\r
                      RootBridgeDev,\r
                      0,\r
                      0xFFFFF,\r
                      RB_MEM32_RANGE,\r
                      PciBarTypeMem32,\r
                      PciResUsageTypical\r
                      );\r
\r
      PMem32Bridge = CreateResourceNode (\r
                       RootBridgeDev,\r
                       0,\r
                       0xFFFFF,\r
                       RB_PMEM32_RANGE,\r
                       PciBarTypePMem32,\r
                       PciResUsageTypical\r
                       );\r
\r
      Mem64Bridge = CreateResourceNode (\r
                      RootBridgeDev,\r
                      0,\r
                      0xFFFFF,\r
                      RB_MEM64_RANGE,\r
                      PciBarTypeMem64,\r
                      PciResUsageTypical\r
                      );\r
\r
      PMem64Bridge = CreateResourceNode (\r
                       RootBridgeDev,\r
                       0,\r
                       0xFFFFF,\r
                       RB_PMEM64_RANGE,\r
                       PciBarTypePMem64,\r
                       PciResUsageTypical\r
                       );\r
\r
      //\r
      // Get the max ROM size that the root bridge can process\r
      // Insert to resource map so that there will be dedicate MEM32 resource range for Option ROM.\r
      // All devices' Option ROM share the same MEM32 resource.\r
      //\r
      MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
      if (MaxOptionRomSize != 0) {\r
        RootBridgeDev->PciBar[0].BarType   = PciBarTypeOpRom;\r
        RootBridgeDev->PciBar[0].Length    = MaxOptionRomSize;\r
        RootBridgeDev->PciBar[0].Alignment = MaxOptionRomSize - 1;\r
        GetResourceFromDevice (RootBridgeDev, IoBridge, Mem32Bridge, PMem32Bridge, Mem64Bridge, PMem64Bridge);\r
      }\r
\r
      //\r
      // Create resourcemap by going through all the devices subject to this root bridge\r
      //\r
      CreateResourceMap (\r
        RootBridgeDev,\r
        IoBridge,\r
        Mem32Bridge,\r
        PMem32Bridge,\r
        Mem64Bridge,\r
        PMem64Bridge\r
        );\r
\r
      //\r
      // Based on the all the resource tree, construct ACPI resource node to\r
      // submit the resource aperture to pci host bridge protocol\r
      //\r
      Status = ConstructAcpiResourceRequestor (\r
                 RootBridgeDev,\r
                 IoBridge,\r
                 Mem32Bridge,\r
                 PMem32Bridge,\r
                 Mem64Bridge,\r
                 PMem64Bridge,\r
                 &AcpiConfig\r
                 );\r
\r
      //\r
      // Insert these resource nodes into the database\r
      //\r
      InsertResourceNode (&IoPool, IoBridge);\r
      InsertResourceNode (&Mem32Pool, Mem32Bridge);\r
      InsertResourceNode (&PMem32Pool, PMem32Bridge);\r
      InsertResourceNode (&Mem64Pool, Mem64Bridge);\r
      InsertResourceNode (&PMem64Pool, PMem64Bridge);\r
\r
      if (Status == EFI_SUCCESS) {\r
        //\r
        // Submit the resource requirement\r
        //\r
        Status = PciResAlloc->SubmitResources (\r
                                PciResAlloc,\r
                                RootBridgeDev->Handle,\r
                                AcpiConfig\r
                                );\r
        //\r
        // If SubmitResources returns error, PciBus isn't able to start.\r
        // It's a fatal error so assertion is added.\r
        //\r
        DEBUG ((DEBUG_INFO, "PciBus: HostBridge->SubmitResources() - %r\n", Status));\r
        ASSERT_EFI_ERROR (Status);\r
      }\r
\r
      //\r
      // Free acpi resource node\r
      //\r
      if (AcpiConfig != NULL) {\r
        FreePool (AcpiConfig);\r
      }\r
\r
      if (EFI_ERROR (Status)) {\r
        //\r
        // Destroy all the resource tree\r
        //\r
        DestroyResourceTree (&IoPool);\r
        DestroyResourceTree (&Mem32Pool);\r
        DestroyResourceTree (&PMem32Pool);\r
        DestroyResourceTree (&Mem64Pool);\r
        DestroyResourceTree (&PMem64Pool);\r
        return Status;\r
      }\r
    }\r
\r
    //\r
    // End while, at least one Root Bridge should be found.\r
    //\r
    ASSERT (RootBridgeDev != NULL);\r
\r
    //\r
    // Notify platform to start to program the resource\r
    //\r
    Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
    DEBUG ((DEBUG_INFO, "PciBus: HostBridge->NotifyPhase(AllocateResources) - %r\n", Status));\r
    if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
      //\r
      // If Hot Plug is not supported\r
      //\r
      if (EFI_ERROR (Status)) {\r
        //\r
        // Allocation failed, then return\r
        //\r
        return EFI_OUT_OF_RESOURCES;\r
      }\r
\r
      //\r
      // Allocation succeed.\r
      // Get host bridge handle for status report, and then skip the main while\r
      //\r
      HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
\r
      break;\r
    } else {\r
      //\r
      // If Hot Plug is supported\r
      //\r
      if (!EFI_ERROR (Status)) {\r
        //\r
        // Allocation succeed, then continue the following\r
        //\r
        break;\r
      }\r
\r
      //\r
      // If the resource allocation is unsuccessful, free resources on bridge\r
      //\r
\r
      RootBridgeDev    = NULL;\r
      RootBridgeHandle = 0;\r
\r
      IoResStatus     = EFI_RESOURCE_SATISFIED;\r
      Mem32ResStatus  = EFI_RESOURCE_SATISFIED;\r
      PMem32ResStatus = EFI_RESOURCE_SATISFIED;\r
      Mem64ResStatus  = EFI_RESOURCE_SATISFIED;\r
      PMem64ResStatus = EFI_RESOURCE_SATISFIED;\r
\r
      while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
        //\r
        // Get RootBridg Device by handle\r
        //\r
        RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
        if (RootBridgeDev == NULL) {\r
          return EFI_NOT_FOUND;\r
        }\r
\r
        //\r
        // Get host bridge handle for status report\r
        //\r
        HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
\r
        //\r
        // Get acpi resource node for all the resource types\r
        //\r
        AcpiConfig = NULL;\r
\r
        Status = PciResAlloc->GetProposedResources (\r
                                PciResAlloc,\r
                                RootBridgeDev->Handle,\r
                                &AcpiConfig\r
                                );\r
\r
        if (EFI_ERROR (Status)) {\r
          return Status;\r
        }\r
\r
        if (AcpiConfig != NULL) {\r
          //\r
          // Adjust resource allocation policy for each RB\r
          //\r
          GetResourceAllocationStatus (\r
            AcpiConfig,\r
            &IoResStatus,\r
            &Mem32ResStatus,\r
            &PMem32ResStatus,\r
            &Mem64ResStatus,\r
            &PMem64ResStatus\r
            );\r
          FreePool (AcpiConfig);\r
        }\r
      }\r
\r
      //\r
      // End while\r
      //\r
\r
      //\r
      // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
      //\r
      //\r
      // It is very difficult to follow the spec here\r
      // Device path , Bar index can not be get here\r
      //\r
      ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
\r
      REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
        EFI_PROGRESS_CODE,\r
        EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
        (VOID *)&AllocFailExtendedData,\r
        sizeof (AllocFailExtendedData)\r
        );\r
\r
      //\r
      // When resource conflict happens, adjust the BAR size first.\r
      // Only when adjusting BAR size doesn't help or BAR size cannot be adjusted,\r
      // reject the device who requests largest resource that causes conflict.\r
      //\r
      ResizableBarAdjusted = FALSE;\r
      if (ResizableBarNeedAdjust) {\r
        ResizableBarAdjusted   = AdjustPciDeviceBarSize (RootBridgeDev);\r
        ResizableBarNeedAdjust = FALSE;\r
      }\r
\r
      if (!ResizableBarAdjusted) {\r
        Status = PciHostBridgeAdjustAllocation (\r
                   &IoPool,\r
                   &Mem32Pool,\r
                   &PMem32Pool,\r
                   &Mem64Pool,\r
                   &PMem64Pool,\r
                   IoResStatus,\r
                   Mem32ResStatus,\r
                   PMem32ResStatus,\r
                   Mem64ResStatus,\r
                   PMem64ResStatus\r
                   );\r
      }\r
\r
      //\r
      // Destroy all the resource tree\r
      //\r
      DestroyResourceTree (&IoPool);\r
      DestroyResourceTree (&Mem32Pool);\r
      DestroyResourceTree (&PMem32Pool);\r
      DestroyResourceTree (&Mem64Pool);\r
      DestroyResourceTree (&PMem64Pool);\r
\r
      NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);\r
\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
    }\r
  }\r
\r
  //\r
  // End main while\r
  //\r
\r
  //\r
  // Raise the EFI_IOB_PCI_RES_ALLOC status code\r
  //\r
  REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
    EFI_PROGRESS_CODE,\r
    EFI_IO_BUS_PCI | EFI_IOB_PCI_RES_ALLOC,\r
    (VOID *)&HandleExtendedData,\r
    sizeof (HandleExtendedData)\r
    );\r
\r
  //\r
  // Notify pci bus driver starts to program the resource\r
  //\r
  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  RootBridgeDev = NULL;\r
\r
  RootBridgeHandle = 0;\r
\r
  while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
    //\r
    // Get RootBridg Device by handle\r
    //\r
    RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
\r
    if (RootBridgeDev == NULL) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    //\r
    // Get acpi resource node for all the resource types\r
    //\r
    AcpiConfig = NULL;\r
    Status     = PciResAlloc->GetProposedResources (\r
                                PciResAlloc,\r
                                RootBridgeDev->Handle,\r
                                &AcpiConfig\r
                                );\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    //\r
    // Get the resource base by interpreting acpi resource node\r
    //\r
    //\r
    GetResourceBase (\r
      AcpiConfig,\r
      &IoBase,\r
      &Mem32Base,\r
      &PMem32Base,\r
      &Mem64Base,\r
      &PMem64Base\r
      );\r
\r
    //\r
    // Create the entire system resource map from the information collected by\r
    // enumerator. Several resource tree was created\r
    //\r
    FindResourceNode (RootBridgeDev, &IoPool, &IoBridge);\r
    FindResourceNode (RootBridgeDev, &Mem32Pool, &Mem32Bridge);\r
    FindResourceNode (RootBridgeDev, &PMem32Pool, &PMem32Bridge);\r
    FindResourceNode (RootBridgeDev, &Mem64Pool, &Mem64Bridge);\r
    FindResourceNode (RootBridgeDev, &PMem64Pool, &PMem64Bridge);\r
\r
    ASSERT (IoBridge     != NULL);\r
    ASSERT (Mem32Bridge  != NULL);\r
    ASSERT (PMem32Bridge != NULL);\r
    ASSERT (Mem64Bridge  != NULL);\r
    ASSERT (PMem64Bridge != NULL);\r
\r
    //\r
    // Program IO resources\r
    //\r
    ProgramResource (\r
      IoBase,\r
      IoBridge\r
      );\r
\r
    //\r
    // Program Mem32 resources\r
    //\r
    ProgramResource (\r
      Mem32Base,\r
      Mem32Bridge\r
      );\r
\r
    //\r
    // Program PMem32 resources\r
    //\r
    ProgramResource (\r
      PMem32Base,\r
      PMem32Bridge\r
      );\r
\r
    //\r
    // Program Mem64 resources\r
    //\r
    ProgramResource (\r
      Mem64Base,\r
      Mem64Bridge\r
      );\r
\r
    //\r
    // Program PMem64 resources\r
    //\r
    ProgramResource (\r
      PMem64Base,\r
      PMem64Bridge\r
      );\r
\r
    //\r
    // Process Option ROM for this root bridge after all BARs are programmed.\r
    // The PPB's MEM32 RANGE BAR is re-programmed to the Option ROM BAR Base in order to\r
    // shadow the Option ROM of the devices under the PPB.\r
    // After the shadow, Option ROM BAR decoding is turned off and the PPB's MEM32 RANGE\r
    // BAR is restored back to the original value.\r
    // The original value is programmed by ProgramResource() above.\r
    //\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "Process Option ROM: BAR Base/Length = %lx/%lx\n",\r
      RootBridgeDev->PciBar[0].BaseAddress,\r
      RootBridgeDev->PciBar[0].Length\r
      ));\r
    ProcessOptionRom (RootBridgeDev, RootBridgeDev->PciBar[0].BaseAddress, RootBridgeDev->PciBar[0].Length);\r
\r
    IoBridge->PciDev->PciBar[IoBridge->Bar].BaseAddress         = IoBase;\r
    Mem32Bridge->PciDev->PciBar[Mem32Bridge->Bar].BaseAddress   = Mem32Base;\r
    PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;\r
    Mem64Bridge->PciDev->PciBar[Mem64Bridge->Bar].BaseAddress   = Mem64Base;\r
    PMem64Bridge->PciDev->PciBar[PMem64Bridge->Bar].BaseAddress = PMem64Base;\r
\r
    //\r
    // Dump the resource map for current root bridge\r
    //\r
    DEBUG_CODE (\r
      PCI_RESOURCE_NODE *Resources[5];\r
      Resources[0] = IoBridge;\r
      Resources[1] = Mem32Bridge;\r
      Resources[2] = PMem32Bridge;\r
      Resources[3] = Mem64Bridge;\r
      Resources[4] = PMem64Bridge;\r
      DumpResourceMap (RootBridgeDev, Resources, ARRAY_SIZE (Resources));\r
      );\r
\r
    FreePool (AcpiConfig);\r
  }\r
\r
  //\r
  // Destroy all the resource tree\r
  //\r
  DestroyResourceTree (&IoPool);\r
  DestroyResourceTree (&Mem32Pool);\r
  DestroyResourceTree (&PMem32Pool);\r
  DestroyResourceTree (&Mem64Pool);\r
  DestroyResourceTree (&PMem64Pool);\r
\r
  //\r
  // Notify the resource allocation phase is to end\r
  //\r
  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
\r
  return Status;\r
}\r
\r
/**\r
  Allocate NumberOfBuses buses and return the next available PCI bus number.\r
\r
  @param  Bridge           Bridge device instance.\r
  @param  StartBusNumber   Current available PCI bus number.\r
  @param  NumberOfBuses    Number of buses enumerated below the StartBusNumber.\r
  @param  NextBusNumber    Next available PCI bus number.\r
\r
  @retval EFI_SUCCESS           Available bus number resource is enough. Next available PCI bus number\r
                                is returned in NextBusNumber.\r
  @retval EFI_OUT_OF_RESOURCES  Available bus number resource is not enough for allocation.\r
\r
**/\r
EFI_STATUS\r
PciAllocateBusNumber (\r
  IN PCI_IO_DEVICE  *Bridge,\r
  IN UINT8          StartBusNumber,\r
  IN UINT8          NumberOfBuses,\r
  OUT UINT8         *NextBusNumber\r
  )\r
{\r
  PCI_IO_DEVICE                      *RootBridge;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *BusNumberRanges;\r
  UINT8                              NextNumber;\r
  UINT64                             MaxNumberInRange;\r
\r
  //\r
  // Get PCI Root Bridge device\r
  //\r
  RootBridge = Bridge;\r
  while (RootBridge->Parent != NULL) {\r
    RootBridge = RootBridge->Parent;\r
  }\r
\r
  //\r
  // Get next available PCI bus number\r
  //\r
  BusNumberRanges = RootBridge->BusNumberRanges;\r
  while (BusNumberRanges->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
    MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;\r
    if ((StartBusNumber >= BusNumberRanges->AddrRangeMin) && (StartBusNumber <=  MaxNumberInRange)) {\r
      NextNumber = (UINT8)(StartBusNumber + NumberOfBuses);\r
      while (NextNumber > MaxNumberInRange) {\r
        ++BusNumberRanges;\r
        if (BusNumberRanges->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
          return EFI_OUT_OF_RESOURCES;\r
        }\r
\r
        NextNumber       = (UINT8)(NextNumber + (BusNumberRanges->AddrRangeMin - (MaxNumberInRange + 1)));\r
        MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;\r
      }\r
\r
      *NextBusNumber = NextNumber;\r
      return EFI_SUCCESS;\r
    }\r
\r
    BusNumberRanges++;\r
  }\r
\r
  return EFI_OUT_OF_RESOURCES;\r
}\r
\r
/**\r
  Scan pci bus and assign bus number to the given PCI bus system.\r
\r
  @param  Bridge           Bridge device instance.\r
  @param  StartBusNumber   start point.\r
  @param  SubBusNumber     Point to sub bus number.\r
  @param  PaddedBusRange   Customized bus number.\r
\r
  @retval EFI_SUCCESS      Successfully scanned and assigned bus number.\r
  @retval other            Some error occurred when scanning pci bus.\r
\r
  @note   Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
\r
**/\r
EFI_STATUS\r
PciScanBus (\r
  IN PCI_IO_DEVICE  *Bridge,\r
  IN UINT8          StartBusNumber,\r
  OUT UINT8         *SubBusNumber,\r
  OUT UINT8         *PaddedBusRange\r
  )\r
{\r
  EFI_STATUS                         Status;\r
  PCI_TYPE00                         Pci;\r
  UINT8                              Device;\r
  UINT8                              Func;\r
  UINT64                             Address;\r
  UINT8                              SecondBus;\r
  UINT8                              PaddedSubBus;\r
  UINT16                             Register;\r
  UINTN                              HpIndex;\r
  PCI_IO_DEVICE                      *PciDevice;\r
  EFI_EVENT                          Event;\r
  EFI_HPC_STATE                      State;\r
  UINT64                             PciAddress;\r
  EFI_HPC_PADDING_ATTRIBUTES         Attributes;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Descriptors;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *NextDescriptors;\r
  UINT16                             BusRange;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *PciRootBridgeIo;\r
  BOOLEAN                            BusPadding;\r
  UINT32                             TempReservedBusNum;\r
  BOOLEAN                            IsAriEnabled;\r
\r
  PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
  SecondBus       = 0;\r
  Register        = 0;\r
  State           = 0;\r
  Attributes      = (EFI_HPC_PADDING_ATTRIBUTES)0;\r
  BusRange        = 0;\r
  BusPadding      = FALSE;\r
  PciDevice       = NULL;\r
  PciAddress      = 0;\r
  IsAriEnabled    = FALSE;\r
\r
  for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
    if (!IsAriEnabled) {\r
      TempReservedBusNum = 0;\r
    }\r
\r
    for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
      //\r
      // Check to see whether a pci device is present\r
      //\r
      Status = PciDevicePresent (\r
                 PciRootBridgeIo,\r
                 &Pci,\r
                 StartBusNumber,\r
                 Device,\r
                 Func\r
                 );\r
\r
      if (EFI_ERROR (Status) && (Func == 0)) {\r
        //\r
        // go to next device if there is no Function 0\r
        //\r
        break;\r
      }\r
\r
      if (EFI_ERROR (Status)) {\r
        continue;\r
      }\r
\r
      //\r
      // Get the PCI device information\r
      //\r
      Status = PciSearchDevice (\r
                 Bridge,\r
                 &Pci,\r
                 StartBusNumber,\r
                 Device,\r
                 Func,\r
                 &PciDevice\r
                 );\r
\r
      if (EFI_ERROR (Status)) {\r
        continue;\r
      }\r
\r
      //\r
      // Per Pcie spec ARI Extended Capability\r
      // This capability must be implemented by each function in an ARI device.\r
      // It is not applicable to a Root Port, a Switch Downstream Port, an RCiEP, or a Root Complex Event Collector\r
      //\r
      if (((Device == 0) && (Func == 0)) && (PciDevice->IsAriEnabled)) {\r
        IsAriEnabled = TRUE;\r
      }\r
\r
      if (PciDevice->IsAriEnabled != IsAriEnabled) {\r
        DEBUG ((\r
          DEBUG_ERROR,\r
          "ERROR: %02x:%02x:%02x device ARI Feature(%x) is not consistent with others Function\n",\r
          StartBusNumber,\r
          Device,\r
          Func,\r
          PciDevice->IsAriEnabled\r
          ));\r
        return EFI_DEVICE_ERROR;\r
      }\r
\r
      PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
\r
      if (!IS_PCI_BRIDGE (&Pci)) {\r
        //\r
        // PCI bridges will be called later\r
        // Here just need for PCI device or PCI to cardbus controller\r
        // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
        //\r
        PreprocessController (\r
          PciDevice,\r
          PciDevice->BusNumber,\r
          PciDevice->DeviceNumber,\r
          PciDevice->FunctionNumber,\r
          EfiPciBeforeChildBusEnumeration\r
          );\r
      }\r
\r
      if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
        //\r
        // For Pci Hotplug controller devcie only\r
        //\r
        if (gPciHotPlugInit != NULL) {\r
          //\r
          // Check if it is a Hotplug PCI controller\r
          //\r
          if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {\r
            gPciRootHpcData[HpIndex].Found = TRUE;\r
\r
            if (!gPciRootHpcData[HpIndex].Initialized) {\r
              Status = CreateEventForHpc (HpIndex, &Event);\r
\r
              ASSERT (!EFI_ERROR (Status));\r
\r
              Status = gPciHotPlugInit->InitializeRootHpc (\r
                                          gPciHotPlugInit,\r
                                          gPciRootHpcPool[HpIndex].HpcDevicePath,\r
                                          PciAddress,\r
                                          Event,\r
                                          &State\r
                                          );\r
\r
              PreprocessController (\r
                PciDevice,\r
                PciDevice->BusNumber,\r
                PciDevice->DeviceNumber,\r
                PciDevice->FunctionNumber,\r
                EfiPciBeforeChildBusEnumeration\r
                );\r
            }\r
          }\r
        }\r
      }\r
\r
      if (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)) {\r
        //\r
        // For PPB\r
        //\r
        if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
          //\r
          // If Hot Plug is supported,\r
          // Get the bridge information\r
          //\r
          BusPadding = FALSE;\r
          if (gPciHotPlugInit != NULL) {\r
            if (IsPciHotPlugBus (PciDevice)) {\r
              //\r
              // If it is initialized, get the padded bus range\r
              //\r
              Status = gPciHotPlugInit->GetResourcePadding (\r
                                          gPciHotPlugInit,\r
                                          PciDevice->DevicePath,\r
                                          PciAddress,\r
                                          &State,\r
                                          (VOID **)&Descriptors,\r
                                          &Attributes\r
                                          );\r
\r
              if (EFI_ERROR (Status)) {\r
                return Status;\r
              }\r
\r
              BusRange        = 0;\r
              NextDescriptors = Descriptors;\r
              Status          = PciGetBusRange (\r
                                  &NextDescriptors,\r
                                  NULL,\r
                                  NULL,\r
                                  &BusRange\r
                                  );\r
\r
              FreePool (Descriptors);\r
\r
              if (!EFI_ERROR (Status)) {\r
                BusPadding = TRUE;\r
              } else if (Status != EFI_NOT_FOUND) {\r
                //\r
                // EFI_NOT_FOUND is not a real error. It indicates no bus number padding requested.\r
                //\r
                return Status;\r
              }\r
            }\r
          }\r
        }\r
\r
        Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);\r
        if (EFI_ERROR (Status)) {\r
          return Status;\r
        }\r
\r
        SecondBus = *SubBusNumber;\r
\r
        Register = (UINT16)((SecondBus << 8) | (UINT16)StartBusNumber);\r
        Address  = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);\r
\r
        Status = PciRootBridgeIo->Pci.Write (\r
                                        PciRootBridgeIo,\r
                                        EfiPciWidthUint16,\r
                                        Address,\r
                                        1,\r
                                        &Register\r
                                        );\r
\r
        //\r
        // If it is PPB, resursively search down this bridge\r
        //\r
        if (IS_PCI_BRIDGE (&Pci)) {\r
          //\r
          // Temporarily initialize SubBusNumber to maximum bus number to ensure the\r
          // PCI configuration transaction to go through any PPB\r
          //\r
          Register = PciGetMaxBusNumber (Bridge);\r
          Address  = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
          Status   = PciRootBridgeIo->Pci.Write (\r
                                            PciRootBridgeIo,\r
                                            EfiPciWidthUint8,\r
                                            Address,\r
                                            1,\r
                                            &Register\r
                                            );\r
\r
          //\r
          // Nofify EfiPciBeforeChildBusEnumeration for PCI Brige\r
          //\r
          PreprocessController (\r
            PciDevice,\r
            PciDevice->BusNumber,\r
            PciDevice->DeviceNumber,\r
            PciDevice->FunctionNumber,\r
            EfiPciBeforeChildBusEnumeration\r
            );\r
\r
          Status = PciScanBus (\r
                     PciDevice,\r
                     SecondBus,\r
                     SubBusNumber,\r
                     PaddedBusRange\r
                     );\r
          if (EFI_ERROR (Status)) {\r
            return Status;\r
          }\r
        }\r
\r
        if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport) && BusPadding) {\r
          //\r
          // Ensure the device is enabled and initialized\r
          //\r
          if ((Attributes == EfiPaddingPciRootBridge) &&\r
              ((State & EFI_HPC_STATE_ENABLED) != 0) &&\r
              ((State & EFI_HPC_STATE_INITIALIZED) != 0))\r
          {\r
            *PaddedBusRange = (UINT8)((UINT8)(BusRange) + *PaddedBusRange);\r
          } else {\r
            //\r
            // Reserve the larger one between the actual occupied bus number and padded bus number\r
            //\r
            Status = PciAllocateBusNumber (PciDevice, SecondBus, (UINT8)(BusRange), &PaddedSubBus);\r
            if (EFI_ERROR (Status)) {\r
              return Status;\r
            }\r
\r
            *SubBusNumber = MAX (PaddedSubBus, *SubBusNumber);\r
          }\r
        }\r
\r
        //\r
        // Set the current maximum bus number under the PPB\r
        //\r
        Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
\r
        Status = PciRootBridgeIo->Pci.Write (\r
                                        PciRootBridgeIo,\r
                                        EfiPciWidthUint8,\r
                                        Address,\r
                                        1,\r
                                        SubBusNumber\r
                                        );\r
      } else {\r
        //\r
        // It is device. Check PCI IOV for Bus reservation\r
        // Go through each function, just reserve the MAX ReservedBusNum for one device\r
        //\r
        if (PcdGetBool (PcdSrIovSupport) && (PciDevice->SrIovCapabilityOffset != 0)) {\r
          if (TempReservedBusNum < PciDevice->ReservedBusNum) {\r
            Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);\r
            if (EFI_ERROR (Status)) {\r
              return Status;\r
            }\r
\r
            TempReservedBusNum = PciDevice->ReservedBusNum;\r
\r
            if (Func == 0) {\r
              DEBUG ((DEBUG_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x\n", *SubBusNumber));\r
            } else {\r
              DEBUG ((DEBUG_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x (Update)\n", *SubBusNumber));\r
            }\r
          }\r
        }\r
      }\r
\r
      if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {\r
        //\r
        // Skip sub functions, this is not a multi function device\r
        //\r
\r
        Func = PCI_MAX_FUNC;\r
      }\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Process Option Rom on the specified root bridge.\r
\r
  @param Bridge  Pci root bridge device instance.\r
\r
  @retval EFI_SUCCESS   Success process.\r
  @retval other         Some error occurred when processing Option Rom on the root bridge.\r
\r
**/\r
EFI_STATUS\r
PciRootBridgeP2CProcess (\r
  IN PCI_IO_DEVICE  *Bridge\r
  )\r
{\r
  LIST_ENTRY     *CurrentLink;\r
  PCI_IO_DEVICE  *Temp;\r
  EFI_HPC_STATE  State;\r
  UINT64         PciAddress;\r
  EFI_STATUS     Status;\r
\r
  CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
  while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
    Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
\r
    if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
      if ((gPciHotPlugInit != NULL) && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
        //\r
        // Raise the EFI_IOB_PCI_HPC_INIT status code\r
        //\r
        REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
          EFI_PROGRESS_CODE,\r
          EFI_IO_BUS_PCI | EFI_IOB_PCI_HPC_INIT,\r
          Temp->DevicePath\r
          );\r
\r
        PciAddress = EFI_PCI_ADDRESS (Temp->BusNumber, Temp->DeviceNumber, Temp->FunctionNumber, 0);\r
        Status     = gPciHotPlugInit->InitializeRootHpc (\r
                                        gPciHotPlugInit,\r
                                        Temp->DevicePath,\r
                                        PciAddress,\r
                                        NULL,\r
                                        &State\r
                                        );\r
\r
        if (!EFI_ERROR (Status)) {\r
          Status = PciBridgeEnumerator (Temp);\r
\r
          if (EFI_ERROR (Status)) {\r
            return Status;\r
          }\r
        }\r
\r
        CurrentLink = CurrentLink->ForwardLink;\r
        continue;\r
      }\r
    }\r
\r
    if (!IsListEmpty (&Temp->ChildList)) {\r
      Status = PciRootBridgeP2CProcess (Temp);\r
    }\r
\r
    CurrentLink = CurrentLink->ForwardLink;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Process Option Rom on the specified host bridge.\r
\r
  @param PciResAlloc    Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
\r
  @retval EFI_SUCCESS   Success process.\r
  @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
  @retval other         Some error occurred when processing Option Rom on the host bridge.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeP2CProcess (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc\r
  )\r
{\r
  EFI_HANDLE     RootBridgeHandle;\r
  PCI_IO_DEVICE  *RootBridgeDev;\r
  EFI_STATUS     Status;\r
\r
  if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  RootBridgeHandle = NULL;\r
\r
  while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
    //\r
    // Get RootBridg Device by handle\r
    //\r
    RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
\r
    if (RootBridgeDev == NULL) {\r
      return EFI_NOT_FOUND;\r
    }\r
\r
    Status = PciRootBridgeP2CProcess (RootBridgeDev);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This function is used to enumerate the entire host bridge\r
  in a given platform.\r
\r
  @param PciResAlloc   A pointer to the PCI Host Resource Allocation protocol.\r
\r
  @retval EFI_SUCCESS            Successfully enumerated the host bridge.\r
  @retval EFI_OUT_OF_RESOURCES   No enough memory available.\r
  @retval other                  Some error occurred when enumerating the host bridge.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeEnumerator (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc\r
  )\r
{\r
  EFI_HANDLE                         RootBridgeHandle;\r
  PCI_IO_DEVICE                      *RootBridgeDev;\r
  EFI_STATUS                         Status;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *PciRootBridgeIo;\r
  UINT16                             MinBus;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Descriptors;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Configuration;\r
  UINT8                              StartBusNumber;\r
  LIST_ENTRY                         RootBridgeList;\r
  LIST_ENTRY                         *Link;\r
  EFI_STATUS                         RootBridgeEnumerationStatus;\r
\r
  if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
    InitializeHotPlugSupport ();\r
  }\r
\r
  InitializeListHead (&RootBridgeList);\r
\r
  //\r
  // Notify the bus allocation phase is about to start\r
  //\r
  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "PCI Bus First Scanning\n"));\r
  RootBridgeHandle            = NULL;\r
  RootBridgeEnumerationStatus = EFI_SUCCESS;\r
  while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
    //\r
    // if a root bridge instance is found, create root bridge device for it\r
    //\r
\r
    RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
\r
    if (RootBridgeDev == NULL) {\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
\r
    //\r
    // Enumerate all the buses under this root bridge\r
    //\r
    Status = PciRootBridgeEnumerator (\r
               PciResAlloc,\r
               RootBridgeDev\r
               );\r
\r
    if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
      InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));\r
    } else {\r
      DestroyRootBridge (RootBridgeDev);\r
    }\r
\r
    if (EFI_ERROR (Status)) {\r
      RootBridgeEnumerationStatus = Status;\r
    }\r
  }\r
\r
  //\r
  // Notify the bus allocation phase is finished for the first time\r
  //\r
  NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
\r
  if (EFI_ERROR (RootBridgeEnumerationStatus)) {\r
    return RootBridgeEnumerationStatus;\r
  }\r
\r
  if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
    //\r
    // Reset all assigned PCI bus number in all PPB\r
    //\r
    RootBridgeHandle = NULL;\r
    Link             = GetFirstNode (&RootBridgeList);\r
    while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&\r
           (!IsNull (&RootBridgeList, Link)))\r
    {\r
      RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);\r
      //\r
      // Get the Bus information\r
      //\r
      Status = PciResAlloc->StartBusEnumeration (\r
                              PciResAlloc,\r
                              RootBridgeHandle,\r
                              (VOID **)&Configuration\r
                              );\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
\r
      //\r
      // Get the bus number to start with\r
      //\r
      StartBusNumber = (UINT8)(Configuration->AddrRangeMin);\r
\r
      ResetAllPpbBusNumber (\r
        RootBridgeDev,\r
        StartBusNumber\r
        );\r
\r
      FreePool (Configuration);\r
      Link = RemoveEntryList (Link);\r
      DestroyRootBridge (RootBridgeDev);\r
    }\r
\r
    //\r
    // Wait for all HPC initialized\r
    //\r
    Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_ERROR, "Some root HPC failed to initialize\n"));\r
      return Status;\r
    }\r
\r
    //\r
    // Notify the bus allocation phase is about to start for the 2nd time\r
    //\r
    Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    DEBUG ((DEBUG_INFO, "PCI Bus Second Scanning\n"));\r
    RootBridgeHandle = NULL;\r
    while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
      //\r
      // if a root bridge instance is found, create root bridge device for it\r
      //\r
      RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
\r
      if (RootBridgeDev == NULL) {\r
        return EFI_OUT_OF_RESOURCES;\r
      }\r
\r
      //\r
      // Enumerate all the buses under this root bridge\r
      //\r
      Status = PciRootBridgeEnumerator (\r
                 PciResAlloc,\r
                 RootBridgeDev\r
                 );\r
\r
      DestroyRootBridge (RootBridgeDev);\r
      if (EFI_ERROR (Status)) {\r
        RootBridgeEnumerationStatus = Status;\r
      }\r
    }\r
\r
    //\r
    // Notify the bus allocation phase is to end for the 2nd time\r
    //\r
    NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
\r
    if (EFI_ERROR (RootBridgeEnumerationStatus)) {\r
      return RootBridgeEnumerationStatus;\r
    }\r
  }\r
\r
  //\r
  // Notify the resource allocation phase is to start\r
  //\r
  Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  RootBridgeHandle = NULL;\r
  while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
    //\r
    // if a root bridge instance is found, create root bridge device for it\r
    //\r
    RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
\r
    if (RootBridgeDev == NULL) {\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
\r
    Status = StartManagingRootBridge (RootBridgeDev);\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    PciRootBridgeIo = RootBridgeDev->PciRootBridgeIo;\r
    Status          = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **)&Descriptors);\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    Status = PciGetBusRange (&Descriptors, &MinBus, NULL, NULL);\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    //\r
    // Determine root bridge attribute by calling interface of Pcihostbridge\r
    // protocol\r
    //\r
    DetermineRootBridgeAttributes (\r
      PciResAlloc,\r
      RootBridgeDev\r
      );\r
\r
    //\r
    // Collect all the resource information under this root bridge\r
    // A database that records all the information about pci device subject to this\r
    // root bridge will then be created\r
    //\r
    Status = PciPciDeviceInfoCollector (\r
               RootBridgeDev,\r
               (UINT8)MinBus\r
               );\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    InsertRootBridge (RootBridgeDev);\r
\r
    //\r
    // Record the hostbridge handle\r
    //\r
    AddHostBridgeEnumerator (RootBridgeDev->PciRootBridgeIo->ParentHandle);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This function is used to program the Resizable BAR Register.\r
\r
  @param PciIoDevice            A pointer to the PCI_IO_DEVICE.\r
  @param ResizableBarOp         PciResizableBarMax: Set BAR to max size\r
                                PciResizableBarMin: set BAR to min size.\r
\r
  @retval EFI_SUCCESS           Successfully enumerated the host bridge.\r
  @retval other                 Some error occurred when enumerating the host bridge.\r
\r
**/\r
EFI_STATUS\r
PciProgramResizableBar (\r
  IN PCI_IO_DEVICE                *PciIoDevice,\r
  IN PCI_RESIZABLE_BAR_OPERATION  ResizableBarOp\r
  )\r
{\r
  EFI_PCI_IO_PROTOCOL                                    *PciIo;\r
  UINT64                                                 Capabilities;\r
  UINT32                                                 Index;\r
  UINT32                                                 Offset;\r
  INTN                                                   Bit;\r
  UINTN                                                  ResizableBarNumber;\r
  EFI_STATUS                                             Status;\r
  PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY  Entries[PCI_MAX_BAR];\r
\r
  ASSERT (PciIoDevice->ResizableBarOffset != 0);\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "   Programs Resizable BAR register, offset: 0x%08x, number: %d\n",\r
    PciIoDevice->ResizableBarOffset,\r
    PciIoDevice->ResizableBarNumber\r
    ));\r
\r
  ResizableBarNumber = MIN (PciIoDevice->ResizableBarNumber, PCI_MAX_BAR);\r
  PciIo              = &PciIoDevice->PciIo;\r
  Status             = PciIo->Pci.Read (\r
                                    PciIo,\r
                                    EfiPciIoWidthUint8,\r
                                    PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER),\r
                                    sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) * ResizableBarNumber,\r
                                    (VOID *)(&Entries)\r
                                    );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  for (Index = 0; Index < ResizableBarNumber; Index++) {\r
    //\r
    // When the bit of Capabilities Set, indicates that the Function supports\r
    // operating with the BAR sized to (2^Bit) MB.\r
    // Example:\r
    // Bit 0 is set: supports operating with the BAR sized to 1 MB\r
    // Bit 1 is set: supports operating with the BAR sized to 2 MB\r
    // Bit n is set: supports operating with the BAR sized to (2^n) MB\r
    //\r
    Capabilities = LShiftU64 (Entries[Index].ResizableBarControl.Bits.BarSizeCapability, 28)\r
                   | Entries[Index].ResizableBarCapability.Bits.BarSizeCapability;\r
\r
    if (ResizableBarOp == PciResizableBarMax) {\r
      Bit = HighBitSet64 (Capabilities);\r
    } else {\r
      ASSERT (ResizableBarOp == PciResizableBarMin);\r
      Bit = LowBitSet64 (Capabilities);\r
    }\r
\r
    ASSERT (Bit >= 0);\r
\r
    Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)\r
             + Index * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY)\r
             + OFFSET_OF (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, ResizableBarControl);\r
\r
    Entries[Index].ResizableBarControl.Bits.BarSize = (UINT32)Bit;\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "   Resizable Bar: Offset = 0x%x, Bar Size Capability = 0x%016lx, New Bar Size = 0x%lx\n",\r
      OFFSET_OF (PCI_TYPE00, Device.Bar[Entries[Index].ResizableBarControl.Bits.BarIndex]),\r
      Capabilities,\r
      LShiftU64 (SIZE_1MB, Bit)\r
      ));\r
    PciIo->Pci.Write (\r
                 PciIo,\r
                 EfiPciIoWidthUint32,\r
                 Offset,\r
                 1,\r
                 &Entries[Index].ResizableBarControl.Uint32\r
                 );\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r