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9060e3ec 1/** @file\r
2 Internal library implementation for PCI Bus module.\r
3\r
4Copyright (c) 2006 - 2009, Intel Corporation\r
5All rights reserved. This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "PciBus.h"\r
16\r
17\r
18/**\r
19 Retrieve the PCI Card device BAR information via PciIo interface.\r
20\r
21 @param PciIoDevice PCI Card device instance.\r
22\r
23**/\r
24VOID\r
25GetBackPcCardBar (\r
26 IN PCI_IO_DEVICE *PciIoDevice\r
27 )\r
28{\r
29 UINT32 Address;\r
30\r
31 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
32 return;\r
33 }\r
34\r
35 //\r
36 // Read PciBar information from the bar register\r
37 //\r
38 if (!gFullEnumeration) {\r
39 Address = 0;\r
40 PciIoDevice->PciIo.Pci.Read (\r
41 &(PciIoDevice->PciIo),\r
42 EfiPciIoWidthUint32,\r
43 PCI_CARD_MEMORY_BASE_0,\r
44 1,\r
45 &Address\r
46 );\r
47\r
48 (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);\r
49 (PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;\r
50 (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;\r
51\r
52 Address = 0;\r
53 PciIoDevice->PciIo.Pci.Read (\r
54 &(PciIoDevice->PciIo),\r
55 EfiPciIoWidthUint32,\r
56 PCI_CARD_MEMORY_BASE_1,\r
57 1,\r
58 &Address\r
59 );\r
60 (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);\r
61 (PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;\r
62 (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;\r
63\r
64 Address = 0;\r
65 PciIoDevice->PciIo.Pci.Read (\r
66 &(PciIoDevice->PciIo),\r
67 EfiPciIoWidthUint32,\r
68 PCI_CARD_IO_BASE_0_LOWER,\r
69 1,\r
70 &Address\r
71 );\r
72 (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);\r
73 (PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;\r
74 (PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;\r
75\r
76 Address = 0;\r
77 PciIoDevice->PciIo.Pci.Read (\r
78 &(PciIoDevice->PciIo),\r
79 EfiPciIoWidthUint32,\r
80 PCI_CARD_IO_BASE_1_LOWER,\r
81 1,\r
82 &Address\r
83 );\r
84 (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);\r
85 (PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;\r
86 (PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;\r
87\r
88 }\r
89\r
90 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
91 GetResourcePaddingForHpb (PciIoDevice);\r
92 }\r
93}\r
94\r
95/**\r
96 Remove rejected pci device from specific root bridge\r
97 handle.\r
98\r
99 @param RootBridgeHandle Specific parent root bridge handle.\r
100 @param Bridge Bridge device instance.\r
101\r
102**/\r
103VOID\r
104RemoveRejectedPciDevices (\r
105 IN EFI_HANDLE RootBridgeHandle,\r
106 IN PCI_IO_DEVICE *Bridge\r
107 )\r
108{\r
109 PCI_IO_DEVICE *Temp;\r
110 LIST_ENTRY *CurrentLink;\r
111 LIST_ENTRY *LastLink;\r
112\r
113 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
114 return;\r
115 }\r
116\r
117 CurrentLink = Bridge->ChildList.ForwardLink;\r
118\r
119 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
120\r
121 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
122\r
123 if (IS_PCI_BRIDGE (&Temp->Pci)) {\r
124 //\r
125 // Remove rejected devices recusively\r
126 //\r
127 RemoveRejectedPciDevices (RootBridgeHandle, Temp);\r
128 } else {\r
129 //\r
130 // Skip rejection for all PPBs, while detect rejection for others\r
131 //\r
132 if (IsPciDeviceRejected (Temp)) {\r
133\r
134 //\r
135 // For P2C, remove all devices on it\r
136 //\r
137 if (!IsListEmpty (&Temp->ChildList)) {\r
138 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Temp);\r
139 }\r
140\r
141 //\r
142 // Finally remove itself\r
143 //\r
144 LastLink = CurrentLink->BackLink;\r
145 RemoveEntryList (CurrentLink);\r
146 FreePciDevice (Temp);\r
147\r
148 CurrentLink = LastLink;\r
149 }\r
150 }\r
151\r
152 CurrentLink = CurrentLink->ForwardLink;\r
153 }\r
154}\r
155\r
156/**\r
157 Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
158\r
159 @param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
160\r
161 @retval EFI_SUCCESS Successfully finished resource allocation.\r
162 @retval EFI_NOT_FOUND Cannot get root bridge instance.\r
163 @retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.\r
164 @retval other Some error occurred when allocating resources for the PCI Host Bridge.\r
165\r
166 @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
167\r
168**/\r
169EFI_STATUS\r
170PciHostBridgeResourceAllocator (\r
171 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
172 )\r
173{\r
174 PCI_IO_DEVICE *RootBridgeDev;\r
175 EFI_HANDLE RootBridgeHandle;\r
176 VOID *AcpiConfig;\r
177 EFI_STATUS Status;\r
178 UINT64 IoBase;\r
179 UINT64 Mem32Base;\r
180 UINT64 PMem32Base;\r
181 UINT64 Mem64Base;\r
182 UINT64 PMem64Base;\r
183 UINT64 IoResStatus;\r
184 UINT64 Mem32ResStatus;\r
185 UINT64 PMem32ResStatus;\r
186 UINT64 Mem64ResStatus;\r
187 UINT64 PMem64ResStatus;\r
188 UINT64 MaxOptionRomSize;\r
189 PCI_RESOURCE_NODE *IoBridge;\r
190 PCI_RESOURCE_NODE *Mem32Bridge;\r
191 PCI_RESOURCE_NODE *PMem32Bridge;\r
192 PCI_RESOURCE_NODE *Mem64Bridge;\r
193 PCI_RESOURCE_NODE *PMem64Bridge;\r
194 PCI_RESOURCE_NODE IoPool;\r
195 PCI_RESOURCE_NODE Mem32Pool;\r
196 PCI_RESOURCE_NODE PMem32Pool;\r
197 PCI_RESOURCE_NODE Mem64Pool;\r
198 PCI_RESOURCE_NODE PMem64Pool;\r
199 BOOLEAN ReAllocate;\r
200 EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;\r
201 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
202\r
203 //\r
204 // Reallocate flag\r
205 //\r
206 ReAllocate = FALSE;\r
207\r
208 //\r
209 // It may try several times if the resource allocation fails\r
210 //\r
211 while (TRUE) {\r
212 //\r
213 // Initialize resource pool\r
214 //\r
215 InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
216 InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
217 InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
218 InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
219 InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
220\r
221 RootBridgeDev = NULL;\r
222 RootBridgeHandle = 0;\r
223\r
224 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
225 //\r
226 // Get Root Bridge Device by handle\r
227 //\r
228 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
229\r
230 if (RootBridgeDev == NULL) {\r
231 return EFI_NOT_FOUND;\r
232 }\r
233\r
234 //\r
235 // Create the entire system resource map from the information collected by\r
236 // enumerator. Several resource tree was created\r
237 //\r
238\r
1ef26783 239 //\r
240 // If non-stardard PCI Bridge I/O window alignment is supported,\r
241 // set I/O aligment to minimum possible alignment for root bridge.\r
242 //\r
9060e3ec 243 IoBridge = CreateResourceNode (\r
244 RootBridgeDev,\r
245 0,\r
1ef26783 246 FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,\r
9060e3ec 247 0,\r
248 PciBarTypeIo16,\r
249 PciResUsageTypical\r
250 );\r
251\r
252 Mem32Bridge = CreateResourceNode (\r
253 RootBridgeDev,\r
254 0,\r
255 0xFFFFF,\r
256 0,\r
257 PciBarTypeMem32,\r
258 PciResUsageTypical\r
259 );\r
260\r
261 PMem32Bridge = CreateResourceNode (\r
262 RootBridgeDev,\r
263 0,\r
264 0xFFFFF,\r
265 0,\r
266 PciBarTypePMem32,\r
267 PciResUsageTypical\r
268 );\r
269\r
270 Mem64Bridge = CreateResourceNode (\r
271 RootBridgeDev,\r
272 0,\r
273 0xFFFFF,\r
274 0,\r
275 PciBarTypeMem64,\r
276 PciResUsageTypical\r
277 );\r
278\r
279 PMem64Bridge = CreateResourceNode (\r
280 RootBridgeDev,\r
281 0,\r
282 0xFFFFF,\r
283 0,\r
284 PciBarTypePMem64,\r
285 PciResUsageTypical\r
286 );\r
287\r
288 //\r
289 // Create resourcemap by going through all the devices subject to this root bridge\r
290 //\r
291 CreateResourceMap (\r
292 RootBridgeDev,\r
293 IoBridge,\r
294 Mem32Bridge,\r
295 PMem32Bridge,\r
296 Mem64Bridge,\r
297 PMem64Bridge\r
298 );\r
299\r
300 //\r
301 // Get the max ROM size that the root bridge can process\r
302 //\r
303 RootBridgeDev->RomSize = Mem32Bridge->Length;\r
304\r
305 //\r
306 // Skip to enlarge the resource request during realloction\r
307 //\r
308 if (!ReAllocate) {\r
309 //\r
310 // Get Max Option Rom size for current root bridge\r
311 //\r
312 MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
313\r
314 //\r
315 // Enlarger the mem32 resource to accomdate the option rom\r
316 // if the mem32 resource is not enough to hold the rom\r
317 //\r
318 if (MaxOptionRomSize > Mem32Bridge->Length) {\r
319\r
320 Mem32Bridge->Length = MaxOptionRomSize;\r
321 RootBridgeDev->RomSize = MaxOptionRomSize;\r
322\r
323 //\r
324 // Alignment should be adjusted as well\r
325 //\r
326 if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
327 Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
328 }\r
329 }\r
330 }\r
331\r
332 //\r
333 // Based on the all the resource tree, contruct ACPI resource node to\r
334 // submit the resource aperture to pci host bridge protocol\r
335 //\r
336 Status = ConstructAcpiResourceRequestor (\r
337 RootBridgeDev,\r
338 IoBridge,\r
339 Mem32Bridge,\r
340 PMem32Bridge,\r
341 Mem64Bridge,\r
342 PMem64Bridge,\r
343 &AcpiConfig\r
344 );\r
345\r
346 //\r
347 // Insert these resource nodes into the database\r
348 //\r
349 InsertResourceNode (&IoPool, IoBridge);\r
350 InsertResourceNode (&Mem32Pool, Mem32Bridge);\r
351 InsertResourceNode (&PMem32Pool, PMem32Bridge);\r
352 InsertResourceNode (&Mem64Pool, Mem64Bridge);\r
353 InsertResourceNode (&PMem64Pool, PMem64Bridge);\r
354\r
355 if (Status == EFI_SUCCESS) {\r
356 //\r
357 // Submit the resource requirement\r
358 //\r
359 Status = PciResAlloc->SubmitResources (\r
360 PciResAlloc,\r
361 RootBridgeDev->Handle,\r
362 AcpiConfig\r
363 );\r
364 }\r
365\r
366 //\r
367 // Free acpi resource node\r
368 //\r
369 if (AcpiConfig != NULL) {\r
370 FreePool (AcpiConfig);\r
371 }\r
372\r
373 if (EFI_ERROR (Status)) {\r
374 //\r
375 // Destroy all the resource tree\r
376 //\r
377 DestroyResourceTree (&IoPool);\r
378 DestroyResourceTree (&Mem32Pool);\r
379 DestroyResourceTree (&PMem32Pool);\r
380 DestroyResourceTree (&Mem64Pool);\r
381 DestroyResourceTree (&PMem64Pool);\r
382 return Status;\r
383 }\r
384 }\r
385 //\r
386 // End while, at least one Root Bridge should be found.\r
387 //\r
388 ASSERT (RootBridgeDev != NULL);\r
389\r
390 //\r
391 // Notify platform to start to program the resource\r
392 //\r
393 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
394 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
395 //\r
396 // If Hot Plug is not supported\r
397 //\r
398 if (EFI_ERROR (Status)) {\r
399 //\r
400 // Allocation failed, then return\r
401 //\r
402 return EFI_OUT_OF_RESOURCES;\r
403 }\r
404 //\r
405 // Allocation succeed.\r
406 // Get host bridge handle for status report, and then skip the main while\r
407 //\r
408 HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
409\r
410 break;\r
411\r
412 } else {\r
413 //\r
414 // If Hot Plug is supported\r
415 //\r
416 if (!EFI_ERROR (Status)) {\r
417 //\r
418 // Allocation succeed, then continue the following\r
419 //\r
420 break;\r
421 }\r
422\r
423 //\r
424 // If the resource allocation is unsuccessful, free resources on bridge\r
425 //\r
426\r
427 RootBridgeDev = NULL;\r
428 RootBridgeHandle = 0;\r
429\r
430 IoResStatus = EFI_RESOURCE_SATISFIED;\r
431 Mem32ResStatus = EFI_RESOURCE_SATISFIED;\r
432 PMem32ResStatus = EFI_RESOURCE_SATISFIED;\r
433 Mem64ResStatus = EFI_RESOURCE_SATISFIED;\r
434 PMem64ResStatus = EFI_RESOURCE_SATISFIED;\r
435\r
436 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
437 //\r
438 // Get RootBridg Device by handle\r
439 //\r
440 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
441 if (RootBridgeDev == NULL) {\r
442 return EFI_NOT_FOUND;\r
443 }\r
444\r
445 //\r
446 // Get host bridge handle for status report\r
447 //\r
448 HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
449\r
450 //\r
451 // Get acpi resource node for all the resource types\r
452 //\r
453 AcpiConfig = NULL;\r
454\r
455 Status = PciResAlloc->GetProposedResources (\r
456 PciResAlloc,\r
457 RootBridgeDev->Handle,\r
458 &AcpiConfig\r
459 );\r
460\r
461 if (EFI_ERROR (Status)) {\r
462 return Status;\r
463 }\r
464\r
465 if (AcpiConfig != NULL) {\r
466 //\r
467 // Adjust resource allocation policy for each RB\r
468 //\r
469 GetResourceAllocationStatus (\r
470 AcpiConfig,\r
471 &IoResStatus,\r
472 &Mem32ResStatus,\r
473 &PMem32ResStatus,\r
474 &Mem64ResStatus,\r
475 &PMem64ResStatus\r
476 );\r
477 FreePool (AcpiConfig);\r
478 }\r
479 }\r
480 //\r
481 // End while\r
482 //\r
483\r
484 //\r
485 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
486 //\r
487 //\r
488 // It is very difficult to follow the spec here\r
489 // Device path , Bar index can not be get here\r
490 //\r
491 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
492\r
493 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
494 EFI_PROGRESS_CODE,\r
495 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
496 (VOID *) &AllocFailExtendedData,\r
497 sizeof (AllocFailExtendedData)\r
498 );\r
499\r
500 Status = PciHostBridgeAdjustAllocation (\r
501 &IoPool,\r
502 &Mem32Pool,\r
503 &PMem32Pool,\r
504 &Mem64Pool,\r
505 &PMem64Pool,\r
506 IoResStatus,\r
507 Mem32ResStatus,\r
508 PMem32ResStatus,\r
509 Mem64ResStatus,\r
510 PMem64ResStatus\r
511 );\r
512\r
513 //\r
514 // Destroy all the resource tree\r
515 //\r
516 DestroyResourceTree (&IoPool);\r
517 DestroyResourceTree (&Mem32Pool);\r
518 DestroyResourceTree (&PMem32Pool);\r
519 DestroyResourceTree (&Mem64Pool);\r
520 DestroyResourceTree (&PMem64Pool);\r
521\r
522 NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);\r
523\r
524 if (EFI_ERROR (Status)) {\r
525 return Status;\r
526 }\r
527\r
528 ReAllocate = TRUE;\r
529 }\r
530 }\r
531 //\r
532 // End main while\r
533 //\r
534\r
535 //\r
536 // Raise the EFI_IOB_PCI_RES_ALLOC status code\r
537 //\r
538 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
539 EFI_PROGRESS_CODE,\r
540 EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_RES_ALLOC,\r
541 (VOID *) &HandleExtendedData,\r
542 sizeof (HandleExtendedData)\r
543 );\r
544\r
545 //\r
546 // Notify pci bus driver starts to program the resource\r
547 //\r
548 NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
549\r
550 RootBridgeDev = NULL;\r
551\r
552 RootBridgeHandle = 0;\r
553\r
554 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
555 //\r
556 // Get RootBridg Device by handle\r
557 //\r
558 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
559\r
560 if (RootBridgeDev == NULL) {\r
561 return EFI_NOT_FOUND;\r
562 }\r
563\r
564 //\r
565 // Get acpi resource node for all the resource types\r
566 //\r
567 AcpiConfig = NULL;\r
568 Status = PciResAlloc->GetProposedResources (\r
569 PciResAlloc,\r
570 RootBridgeDev->Handle,\r
571 &AcpiConfig\r
572 );\r
573\r
574 if (EFI_ERROR (Status)) {\r
575 return Status;\r
576 }\r
577\r
578 //\r
579 // Get the resource base by interpreting acpi resource node\r
580 //\r
581 //\r
582 GetResourceBase (\r
583 AcpiConfig,\r
584 &IoBase,\r
585 &Mem32Base,\r
586 &PMem32Base,\r
587 &Mem64Base,\r
588 &PMem64Base\r
589 );\r
590\r
591 //\r
592 // Process option rom for this root bridge\r
593 //\r
594 ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
595\r
596 //\r
597 // Create the entire system resource map from the information collected by\r
598 // enumerator. Several resource tree was created\r
599 //\r
600 GetResourceMap (\r
601 RootBridgeDev,\r
602 &IoBridge,\r
603 &Mem32Bridge,\r
604 &PMem32Bridge,\r
605 &Mem64Bridge,\r
606 &PMem64Bridge,\r
607 &IoPool,\r
608 &Mem32Pool,\r
609 &PMem32Pool,\r
610 &Mem64Pool,\r
611 &PMem64Pool\r
612 );\r
613\r
614 //\r
615 // Program IO resources\r
616 //\r
617 ProgramResource (\r
618 IoBase,\r
619 IoBridge\r
620 );\r
621\r
622 //\r
623 // Program Mem32 resources\r
624 //\r
625 ProgramResource (\r
626 Mem32Base,\r
627 Mem32Bridge\r
628 );\r
629\r
630 //\r
631 // Program PMem32 resources\r
632 //\r
633 ProgramResource (\r
634 PMem32Base,\r
635 PMem32Bridge\r
636 );\r
637\r
638 //\r
639 // Program Mem64 resources\r
640 //\r
641 ProgramResource (\r
642 Mem64Base,\r
643 Mem64Bridge\r
644 );\r
645\r
646 //\r
647 // Program PMem64 resources\r
648 //\r
649 ProgramResource (\r
650 PMem64Base,\r
651 PMem64Bridge\r
652 );\r
653\r
654 FreePool (AcpiConfig);\r
655 }\r
656\r
657 //\r
658 // Destroy all the resource tree\r
659 //\r
660 DestroyResourceTree (&IoPool);\r
661 DestroyResourceTree (&Mem32Pool);\r
662 DestroyResourceTree (&PMem32Pool);\r
663 DestroyResourceTree (&Mem64Pool);\r
664 DestroyResourceTree (&PMem64Pool);\r
665\r
666 //\r
667 // Notify the resource allocation phase is to end\r
668 //\r
669 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
670\r
671 return EFI_SUCCESS;\r
672}\r
673\r
674/**\r
675 Scan pci bus and assign bus number to the given PCI bus system.\r
676\r
677 @param Bridge Bridge device instance.\r
678 @param StartBusNumber start point.\r
679 @param SubBusNumber Point to sub bus number.\r
680 @param PaddedBusRange Customized bus number.\r
681\r
682 @retval EFI_SUCCESS Successfully scanned and assigned bus number.\r
683 @retval other Some error occurred when scanning pci bus.\r
684\r
685 @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
686\r
687**/\r
688EFI_STATUS\r
689PciScanBus (\r
690 IN PCI_IO_DEVICE *Bridge,\r
691 IN UINT8 StartBusNumber,\r
692 OUT UINT8 *SubBusNumber,\r
693 OUT UINT8 *PaddedBusRange\r
694 )\r
695{\r
696 EFI_STATUS Status;\r
697 PCI_TYPE00 Pci;\r
698 UINT8 Device;\r
699 UINT8 Func;\r
700 UINT64 Address;\r
701 UINTN SecondBus;\r
702 UINT16 Register;\r
703 UINTN HpIndex;\r
704 PCI_IO_DEVICE *PciDevice;\r
705 EFI_EVENT Event;\r
706 EFI_HPC_STATE State;\r
707 UINT64 PciAddress;\r
708 EFI_HPC_PADDING_ATTRIBUTES Attributes;\r
709 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
710 UINT16 BusRange;\r
711 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
712 BOOLEAN BusPadding;\r
713 UINT32 TempReservedBusNum;\r
714\r
715 PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
716 SecondBus = 0;\r
717 Register = 0;\r
718 State = 0;\r
719 Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;\r
720 BusRange = 0;\r
721 BusPadding = FALSE;\r
722 PciDevice = NULL;\r
723 PciAddress = 0;\r
724\r
725 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
726 TempReservedBusNum = 0;\r
727 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
728\r
729 //\r
730 // Check to see whether a pci device is present\r
731 //\r
732 Status = PciDevicePresent (\r
733 PciRootBridgeIo,\r
734 &Pci,\r
735 StartBusNumber,\r
736 Device,\r
737 Func\r
738 );\r
739\r
740 if (EFI_ERROR (Status)) {\r
741 if (Func == 0) {\r
742 //\r
743 // Skip sub functions, this is not a multi function device\r
744 //\r
745 Func = PCI_MAX_FUNC;\r
746 }\r
747\r
748 continue;\r
749 }\r
750\r
751 DEBUG((EFI_D_INFO, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
752\r
753 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
754 //\r
755 // Get the PCI device information\r
756 //\r
757 Status = PciSearchDevice (\r
758 Bridge,\r
759 &Pci,\r
760 StartBusNumber,\r
761 Device,\r
762 Func,\r
763 &PciDevice\r
764 );\r
765\r
766 ASSERT (!EFI_ERROR (Status));\r
767\r
768 PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
769\r
770 if (!IS_PCI_BRIDGE (&Pci)) {\r
771 //\r
772 // PCI bridges will be called later\r
773 // Here just need for PCI device or PCI to cardbus controller\r
774 // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
775 //\r
776 PreprocessController (\r
777 PciDevice,\r
778 PciDevice->BusNumber,\r
779 PciDevice->DeviceNumber,\r
780 PciDevice->FunctionNumber,\r
781 EfiPciBeforeChildBusEnumeration\r
782 );\r
783 }\r
784\r
785 //\r
786 // For Pci Hotplug controller devcie only\r
787 //\r
788 if (gPciHotPlugInit != NULL) {\r
789 //\r
790 // Check if it is a Hotplug PCI controller\r
791 //\r
792 if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {\r
793\r
794 if (!gPciRootHpcData[HpIndex].Initialized) {\r
795\r
796 Status = CreateEventForHpc (HpIndex, &Event);\r
797\r
798 ASSERT (!EFI_ERROR (Status));\r
799\r
800 Status = gPciHotPlugInit->InitializeRootHpc (\r
801 gPciHotPlugInit,\r
802 gPciRootHpcPool[HpIndex].HpcDevicePath,\r
803 PciAddress,\r
804 Event,\r
805 &State\r
806 );\r
807\r
808 PreprocessController (\r
809 PciDevice,\r
810 PciDevice->BusNumber,\r
811 PciDevice->DeviceNumber,\r
812 PciDevice->FunctionNumber,\r
813 EfiPciBeforeChildBusEnumeration\r
814 );\r
815 }\r
816 }\r
817 }\r
818 }\r
819\r
820 if (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)) {\r
821 //\r
822 // For PPB\r
823 //\r
824 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
825 //\r
826 // If Hot Plug is not supported,\r
827 // get the bridge information\r
828 //\r
829 Status = PciSearchDevice (\r
830 Bridge,\r
831 &Pci,\r
832 StartBusNumber,\r
833 Device,\r
834 Func,\r
835 &PciDevice\r
836 );\r
837\r
838 if (EFI_ERROR (Status)) {\r
839 return Status;\r
840 }\r
841 } else {\r
842 //\r
843 // If Hot Plug is supported,\r
844 // Get the bridge information\r
845 //\r
846 BusPadding = FALSE;\r
847 if (gPciHotPlugInit != NULL) {\r
848\r
849 if (IsRootPciHotPlugBus (PciDevice->DevicePath, &HpIndex)) {\r
850\r
851 //\r
852 // If it is initialized, get the padded bus range\r
853 //\r
854 Status = gPciHotPlugInit->GetResourcePadding (\r
855 gPciHotPlugInit,\r
856 gPciRootHpcPool[HpIndex].HpbDevicePath,\r
857 PciAddress,\r
858 &State,\r
859 (VOID **) &Descriptors,\r
860 &Attributes\r
861 );\r
862\r
863 if (EFI_ERROR (Status)) {\r
864 return Status;\r
865 }\r
866\r
867 BusRange = 0;\r
868 Status = PciGetBusRange (\r
869 &Descriptors,\r
870 NULL,\r
871 NULL,\r
872 &BusRange\r
873 );\r
874\r
875 FreePool (Descriptors);\r
876\r
877 if (EFI_ERROR (Status)) {\r
878 return Status;\r
879 }\r
880\r
881 BusPadding = TRUE;\r
882 }\r
883 }\r
884 }\r
885\r
886 //\r
887 // Add feature to support customized secondary bus number\r
888 //\r
889 if (*SubBusNumber == 0) {\r
890 *SubBusNumber = *PaddedBusRange;\r
891 *PaddedBusRange = 0;\r
892 }\r
893\r
894 (*SubBusNumber)++;\r
895 SecondBus = *SubBusNumber;\r
896\r
897 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
898 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);\r
899\r
900 Status = PciRootBridgeIo->Pci.Write (\r
901 PciRootBridgeIo,\r
902 EfiPciWidthUint16,\r
903 Address,\r
904 1,\r
905 &Register\r
906 );\r
907\r
908\r
909 //\r
910 // If it is PPB, resursively search down this bridge\r
911 //\r
912 if (IS_PCI_BRIDGE (&Pci)) {\r
913\r
914 //\r
915 // Temporarily initialize SubBusNumber to maximum bus number to ensure the\r
916 // PCI configuration transaction to go through any PPB\r
917 //\r
918 Register = 0xFF;\r
919 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
920 Status = PciRootBridgeIo->Pci.Write (\r
921 PciRootBridgeIo,\r
922 EfiPciWidthUint8,\r
923 Address,\r
924 1,\r
925 &Register\r
926 );\r
927\r
928 //\r
929 // Nofify EfiPciBeforeChildBusEnumeration for PCI Brige\r
930 //\r
931 PreprocessController (\r
932 PciDevice,\r
933 PciDevice->BusNumber,\r
934 PciDevice->DeviceNumber,\r
935 PciDevice->FunctionNumber,\r
936 EfiPciBeforeChildBusEnumeration\r
937 );\r
938\r
939 DEBUG((EFI_D_INFO, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber));\r
940 Status = PciScanBus (\r
941 PciDevice,\r
942 (UINT8) (SecondBus),\r
943 SubBusNumber,\r
944 PaddedBusRange\r
945 );\r
946 if (EFI_ERROR (Status)) {\r
947 return Status;\r
948 }\r
949 }\r
950\r
951 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport) && BusPadding) {\r
952 //\r
953 // Ensure the device is enabled and initialized\r
954 //\r
955 if ((Attributes == EfiPaddingPciRootBridge) &&\r
956 (State & EFI_HPC_STATE_ENABLED) != 0 &&\r
957 (State & EFI_HPC_STATE_INITIALIZED) != 0) {\r
958 *PaddedBusRange = (UINT8) ((UINT8) (BusRange) +*PaddedBusRange);\r
959 } else {\r
960 *SubBusNumber = (UINT8) ((UINT8) (BusRange) +*SubBusNumber);\r
961 }\r
962 }\r
963\r
964 //\r
965 // Set the current maximum bus number under the PPB\r
966 //\r
967 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
968\r
969 Status = PciRootBridgeIo->Pci.Write (\r
970 PciRootBridgeIo,\r
971 EfiPciWidthUint8,\r
972 Address,\r
973 1,\r
974 SubBusNumber\r
975 );\r
976 } else {\r
977 //\r
978 // It is device. Check PCI IOV for Bus reservation\r
979 //\r
980 if (PciDevice == NULL) {\r
981 //\r
982 // No PciDevice found, conitue Scan\r
983 //\r
984 continue;\r
985 }\r
986 //\r
987 // Go through each function, just reserve the MAX ReservedBusNum for one device\r
988 //\r
989 if ((PciDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {\r
990\r
991 if (TempReservedBusNum < PciDevice->ReservedBusNum) {\r
992\r
993 (*SubBusNumber) = (UINT8)((*SubBusNumber) + PciDevice->ReservedBusNum - TempReservedBusNum);\r
994 TempReservedBusNum = PciDevice->ReservedBusNum;\r
995\r
996 if (Func == 0) {\r
997 DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x\n", *SubBusNumber));\r
998 } else {\r
999 DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x (Update)\n", *SubBusNumber));\r
1000 }\r
1001 }\r
1002 }\r
1003 }\r
1004\r
1005 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
1006\r
1007 //\r
1008 // Skip sub functions, this is not a multi function device\r
1009 //\r
1010\r
1011 Func = PCI_MAX_FUNC;\r
1012 }\r
1013 }\r
1014 }\r
1015\r
1016 return EFI_SUCCESS;\r
1017}\r
1018\r
1019/**\r
1020 Process Option Rom on the specified root bridge.\r
1021\r
1022 @param Bridge Pci root bridge device instance.\r
1023\r
1024 @retval EFI_SUCCESS Success process.\r
1025 @retval other Some error occurred when processing Option Rom on the root bridge.\r
1026\r
1027**/\r
1028EFI_STATUS\r
1029PciRootBridgeP2CProcess (\r
1030 IN PCI_IO_DEVICE *Bridge\r
1031 )\r
1032{\r
1033 LIST_ENTRY *CurrentLink;\r
1034 PCI_IO_DEVICE *Temp;\r
1035 EFI_HPC_STATE State;\r
1036 UINT64 PciAddress;\r
1037 EFI_STATUS Status;\r
1038\r
1039 CurrentLink = Bridge->ChildList.ForwardLink;\r
1040\r
1041 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
1042\r
1043 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
1044\r
1045 if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
1046\r
1047 if (gPciHotPlugInit != NULL && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
1048\r
1049 //\r
1050 // Raise the EFI_IOB_PCI_HPC_INIT status code\r
1051 //\r
1052 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1053 EFI_PROGRESS_CODE,\r
1054 EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_HPC_INIT,\r
1055 Temp->DevicePath\r
1056 );\r
1057\r
1058 PciAddress = EFI_PCI_ADDRESS (Temp->BusNumber, Temp->DeviceNumber, Temp->FunctionNumber, 0);\r
1059 Status = gPciHotPlugInit->InitializeRootHpc (\r
1060 gPciHotPlugInit,\r
1061 Temp->DevicePath,\r
1062 PciAddress,\r
1063 NULL,\r
1064 &State\r
1065 );\r
1066\r
1067 if (!EFI_ERROR (Status)) {\r
1068 Status = PciBridgeEnumerator (Temp);\r
1069\r
1070 if (EFI_ERROR (Status)) {\r
1071 return Status;\r
1072 }\r
1073 }\r
1074\r
1075 CurrentLink = CurrentLink->ForwardLink;\r
1076 continue;\r
1077\r
1078 }\r
1079 }\r
1080\r
1081 if (!IsListEmpty (&Temp->ChildList)) {\r
1082 Status = PciRootBridgeP2CProcess (Temp);\r
1083 }\r
1084\r
1085 CurrentLink = CurrentLink->ForwardLink;\r
1086 }\r
1087\r
1088 return EFI_SUCCESS;\r
1089}\r
1090\r
1091/**\r
1092 Process Option Rom on the specified host bridge.\r
1093\r
1094 @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
1095\r
1096 @retval EFI_SUCCESS Success process.\r
1097 @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
1098 @retval other Some error occurred when processing Option Rom on the host bridge.\r
1099\r
1100**/\r
1101EFI_STATUS\r
1102PciHostBridgeP2CProcess (\r
1103 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
1104 )\r
1105{\r
1106 EFI_HANDLE RootBridgeHandle;\r
1107 PCI_IO_DEVICE *RootBridgeDev;\r
1108 EFI_STATUS Status;\r
1109\r
1110 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
1111 return EFI_SUCCESS;\r
1112 }\r
1113\r
1114 RootBridgeHandle = NULL;\r
1115\r
1116 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
1117\r
1118 //\r
1119 // Get RootBridg Device by handle\r
1120 //\r
1121 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
1122\r
1123 if (RootBridgeDev == NULL) {\r
1124 return EFI_NOT_FOUND;\r
1125 }\r
1126\r
1127 Status = PciRootBridgeP2CProcess (RootBridgeDev);\r
1128 if (EFI_ERROR (Status)) {\r
1129 return Status;\r
1130 }\r
1131\r
1132 }\r
1133\r
1134 return EFI_SUCCESS;\r
1135}\r
1136\r
1137/**\r
1138 This function is used to enumerate the entire host bridge\r
1139 in a given platform.\r
1140\r
1141 @param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.\r
1142\r
1143 @retval EFI_SUCCESS Successfully enumerated the host bridge.\r
1144 @retval EFI_OUT_OF_RESOURCES No enough memory available.\r
1145 @retval other Some error occurred when enumerating the host bridge.\r
1146\r
1147**/\r
1148EFI_STATUS\r
1149PciHostBridgeEnumerator (\r
1150 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
1151 )\r
1152{\r
1153 EFI_HANDLE RootBridgeHandle;\r
1154 PCI_IO_DEVICE *RootBridgeDev;\r
1155 EFI_STATUS Status;\r
1156 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
1157 UINT16 MinBus;\r
1158 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
1159 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
1160 UINT8 StartBusNumber;\r
1161 LIST_ENTRY RootBridgeList;\r
1162 LIST_ENTRY *Link;\r
1163\r
1164 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
1165 InitializeHotPlugSupport ();\r
1166 }\r
1167\r
1168 InitializeListHead (&RootBridgeList);\r
1169\r
1170 //\r
1171 // Notify the bus allocation phase is about to start\r
1172 //\r
1173 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
1174\r
1175 DEBUG((EFI_D_INFO, "PCI Bus First Scanning\n"));\r
1176 RootBridgeHandle = NULL;\r
1177 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
1178\r
1179 //\r
1180 // if a root bridge instance is found, create root bridge device for it\r
1181 //\r
1182\r
1183 RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
1184\r
1185 if (RootBridgeDev == NULL) {\r
1186 return EFI_OUT_OF_RESOURCES;\r
1187 }\r
1188\r
1189 //\r
1190 // Enumerate all the buses under this root bridge\r
1191 //\r
1192 Status = PciRootBridgeEnumerator (\r
1193 PciResAlloc,\r
1194 RootBridgeDev\r
1195 );\r
1196\r
1197 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
1198 InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));\r
1199 } else {\r
1200 DestroyRootBridge (RootBridgeDev);\r
1201 }\r
1202 if (EFI_ERROR (Status)) {\r
1203 return Status;\r
1204 }\r
1205 }\r
1206\r
1207 //\r
1208 // Notify the bus allocation phase is finished for the first time\r
1209 //\r
1210 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
1211\r
1212 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
1213 //\r
1214 // Reset all assigned PCI bus number in all PPB\r
1215 //\r
1216 RootBridgeHandle = NULL;\r
1217 Link = GetFirstNode (&RootBridgeList);\r
1218 while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&\r
1219 (!IsNull (&RootBridgeList, Link))) {\r
1220 RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);\r
1221 //\r
1222 // Get the Bus information\r
1223 //\r
1224 Status = PciResAlloc->StartBusEnumeration (\r
1225 PciResAlloc,\r
1226 RootBridgeHandle,\r
1227 (VOID **) &Configuration\r
1228 );\r
1229 if (EFI_ERROR (Status)) {\r
1230 return Status;\r
1231 }\r
1232\r
1233 //\r
1234 // Get the bus number to start with\r
1235 //\r
1236 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
1237\r
1238 ResetAllPpbBusNumber (\r
1239 RootBridgeDev,\r
1240 StartBusNumber\r
1241 );\r
1242\r
1243 FreePool (Configuration);\r
1244 Link = GetNextNode (&RootBridgeList, Link);\r
1245 DestroyRootBridge (RootBridgeDev);\r
1246 }\r
1247\r
1248 //\r
1249 // Wait for all HPC initialized\r
1250 //\r
1251 Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
1252\r
1253 if (EFI_ERROR (Status)) {\r
1254 return Status;\r
1255 }\r
1256\r
1257 //\r
1258 // Notify the bus allocation phase is about to start for the 2nd time\r
1259 //\r
1260 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
1261\r
1262 DEBUG((EFI_D_INFO, "PCI Bus Second Scanning\n"));\r
1263 RootBridgeHandle = NULL;\r
1264 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
1265\r
1266 //\r
1267 // if a root bridge instance is found, create root bridge device for it\r
1268 //\r
1269 RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
1270\r
1271 if (RootBridgeDev == NULL) {\r
1272 return EFI_OUT_OF_RESOURCES;\r
1273 }\r
1274\r
1275 //\r
1276 // Enumerate all the buses under this root bridge\r
1277 //\r
1278 Status = PciRootBridgeEnumerator (\r
1279 PciResAlloc,\r
1280 RootBridgeDev\r
1281 );\r
1282\r
1283 DestroyRootBridge (RootBridgeDev);\r
1284 if (EFI_ERROR (Status)) {\r
1285 return Status;\r
1286 }\r
1287 }\r
1288\r
1289 //\r
1290 // Notify the bus allocation phase is to end for the 2nd time\r
1291 //\r
1292 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
1293 }\r
1294\r
1295 //\r
1296 // Notify the resource allocation phase is to start\r
1297 //\r
1298 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);\r
1299\r
1300 RootBridgeHandle = NULL;\r
1301 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
1302\r
1303 //\r
1304 // if a root bridge instance is found, create root bridge device for it\r
1305 //\r
1306 RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
1307\r
1308 if (RootBridgeDev == NULL) {\r
1309 return EFI_OUT_OF_RESOURCES;\r
1310 }\r
1311\r
1312 Status = StartManagingRootBridge (RootBridgeDev);\r
1313\r
1314 if (EFI_ERROR (Status)) {\r
1315 return Status;\r
1316 }\r
1317\r
1318 PciRootBridgeIo = RootBridgeDev->PciRootBridgeIo;\r
1319 Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);\r
1320\r
1321 if (EFI_ERROR (Status)) {\r
1322 return Status;\r
1323 }\r
1324\r
1325 Status = PciGetBusRange (&Descriptors, &MinBus, NULL, NULL);\r
1326\r
1327 if (EFI_ERROR (Status)) {\r
1328 return Status;\r
1329 }\r
1330\r
1331 //\r
1332 // Determine root bridge attribute by calling interface of Pcihostbridge\r
1333 // protocol\r
1334 //\r
1335 DetermineRootBridgeAttributes (\r
1336 PciResAlloc,\r
1337 RootBridgeDev\r
1338 );\r
1339\r
1340 //\r
1341 // Collect all the resource information under this root bridge\r
1342 // A database that records all the information about pci device subject to this\r
1343 // root bridge will then be created\r
1344 //\r
1345 Status = PciPciDeviceInfoCollector (\r
1346 RootBridgeDev,\r
1347 (UINT8) MinBus\r
1348 );\r
1349\r
1350 if (EFI_ERROR (Status)) {\r
1351 return Status;\r
1352 }\r
1353\r
1354 InsertRootBridge (RootBridgeDev);\r
1355\r
1356 //\r
1357 // Record the hostbridge handle\r
1358 //\r
1359 AddHostBridgeEnumerator (RootBridgeDev->PciRootBridgeIo->ParentHandle);\r
1360 }\r
1361\r
1362 return EFI_SUCCESS;\r
1363}\r
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