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Commit | Line | Data |
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4a50cf4e RN |
1 | /** @file\r |
2 | \r | |
3 | PCI Root Bridge Io Protocol code.\r | |
4 | \r | |
0edb7ec5 | 5 | Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4a50cf4e RN |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include "PciHostBridge.h"\r | |
11 | #include "PciRootBridge.h"\r | |
12 | #include "PciHostResource.h"\r | |
13 | \r | |
ccf66016 | 14 | #define NO_MAPPING (VOID *) (UINTN) -1\r |
4a50cf4e | 15 | \r |
1436aea4 | 16 | #define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)\r |
b8bfb92b | 17 | \r |
4a50cf4e RN |
18 | //\r |
19 | // Lookup table for increment values based on transfer widths\r | |
20 | //\r | |
1436aea4 | 21 | UINT8 mInStride[] = {\r |
4a50cf4e RN |
22 | 1, // EfiPciWidthUint8\r |
23 | 2, // EfiPciWidthUint16\r | |
24 | 4, // EfiPciWidthUint32\r | |
25 | 8, // EfiPciWidthUint64\r | |
26 | 0, // EfiPciWidthFifoUint8\r | |
27 | 0, // EfiPciWidthFifoUint16\r | |
28 | 0, // EfiPciWidthFifoUint32\r | |
29 | 0, // EfiPciWidthFifoUint64\r | |
30 | 1, // EfiPciWidthFillUint8\r | |
31 | 2, // EfiPciWidthFillUint16\r | |
32 | 4, // EfiPciWidthFillUint32\r | |
33 | 8 // EfiPciWidthFillUint64\r | |
34 | };\r | |
35 | \r | |
36 | //\r | |
37 | // Lookup table for increment values based on transfer widths\r | |
38 | //\r | |
1436aea4 | 39 | UINT8 mOutStride[] = {\r |
4a50cf4e RN |
40 | 1, // EfiPciWidthUint8\r |
41 | 2, // EfiPciWidthUint16\r | |
42 | 4, // EfiPciWidthUint32\r | |
43 | 8, // EfiPciWidthUint64\r | |
44 | 1, // EfiPciWidthFifoUint8\r | |
45 | 2, // EfiPciWidthFifoUint16\r | |
46 | 4, // EfiPciWidthFifoUint32\r | |
47 | 8, // EfiPciWidthFifoUint64\r | |
48 | 0, // EfiPciWidthFillUint8\r | |
49 | 0, // EfiPciWidthFillUint16\r | |
50 | 0, // EfiPciWidthFillUint32\r | |
51 | 0 // EfiPciWidthFillUint64\r | |
52 | };\r | |
53 | \r | |
54 | /**\r | |
55 | Construct the Pci Root Bridge instance.\r | |
56 | \r | |
57 | @param Bridge The root bridge instance.\r | |
4a50cf4e RN |
58 | \r |
59 | @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created\r | |
60 | or NULL if creation fails.\r | |
61 | **/\r | |
62 | PCI_ROOT_BRIDGE_INSTANCE *\r | |
63 | CreateRootBridge (\r | |
1436aea4 | 64 | IN PCI_ROOT_BRIDGE *Bridge\r |
4a50cf4e RN |
65 | )\r |
66 | {\r | |
1436aea4 MK |
67 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r |
68 | PCI_RESOURCE_TYPE Index;\r | |
69 | CHAR16 *DevicePathStr;\r | |
70 | PCI_ROOT_BRIDGE_APERTURE *Aperture;\r | |
4a50cf4e RN |
71 | \r |
72 | DevicePathStr = NULL;\r | |
73 | \r | |
87000d77 MK |
74 | DEBUG ((DEBUG_INFO, "RootBridge: "));\r |
75 | DEBUG ((DEBUG_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));\r | |
76 | DEBUG ((DEBUG_INFO, " Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));\r | |
77 | DEBUG ((DEBUG_INFO, " DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));\r | |
78 | DEBUG ((DEBUG_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));\r | |
74d0a339 | 79 | DEBUG ((\r |
1436aea4 MK |
80 | DEBUG_INFO,\r |
81 | " AllocAttr: %lx (%s%s)\n",\r | |
82 | Bridge->AllocationAttributes,\r | |
83 | (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",\r | |
84 | (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""\r | |
85 | ));\r | |
86 | DEBUG ((\r | |
87 | DEBUG_INFO,\r | |
88 | " Bus: %lx - %lx Translation=%lx\n",\r | |
89 | Bridge->Bus.Base,\r | |
90 | Bridge->Bus.Limit,\r | |
91 | Bridge->Bus.Translation\r | |
74d0a339 HG |
92 | ));\r |
93 | //\r | |
94 | // Translation for bus is not supported.\r | |
95 | //\r | |
96 | ASSERT (Bridge->Bus.Translation == 0);\r | |
97 | if (Bridge->Bus.Translation != 0) {\r | |
98 | return NULL;\r | |
99 | }\r | |
100 | \r | |
101 | DEBUG ((\r | |
1436aea4 MK |
102 | DEBUG_INFO,\r |
103 | " Io: %lx - %lx Translation=%lx\n",\r | |
104 | Bridge->Io.Base,\r | |
105 | Bridge->Io.Limit,\r | |
106 | Bridge->Io.Translation\r | |
74d0a339 HG |
107 | ));\r |
108 | DEBUG ((\r | |
1436aea4 MK |
109 | DEBUG_INFO,\r |
110 | " Mem: %lx - %lx Translation=%lx\n",\r | |
111 | Bridge->Mem.Base,\r | |
112 | Bridge->Mem.Limit,\r | |
113 | Bridge->Mem.Translation\r | |
74d0a339 HG |
114 | ));\r |
115 | DEBUG ((\r | |
1436aea4 MK |
116 | DEBUG_INFO,\r |
117 | " MemAbove4G: %lx - %lx Translation=%lx\n",\r | |
118 | Bridge->MemAbove4G.Base,\r | |
119 | Bridge->MemAbove4G.Limit,\r | |
120 | Bridge->MemAbove4G.Translation\r | |
74d0a339 HG |
121 | ));\r |
122 | DEBUG ((\r | |
1436aea4 MK |
123 | DEBUG_INFO,\r |
124 | " PMem: %lx - %lx Translation=%lx\n",\r | |
125 | Bridge->PMem.Base,\r | |
126 | Bridge->PMem.Limit,\r | |
127 | Bridge->PMem.Translation\r | |
74d0a339 HG |
128 | ));\r |
129 | DEBUG ((\r | |
1436aea4 MK |
130 | DEBUG_INFO,\r |
131 | " PMemAbove4G: %lx - %lx Translation=%lx\n",\r | |
132 | Bridge->PMemAbove4G.Base,\r | |
133 | Bridge->PMemAbove4G.Limit,\r | |
134 | Bridge->PMemAbove4G.Translation\r | |
74d0a339 | 135 | ));\r |
4a50cf4e RN |
136 | \r |
137 | //\r | |
138 | // Make sure Mem and MemAbove4G apertures are valid\r | |
139 | //\r | |
b8bfb92b | 140 | if (RESOURCE_VALID (&Bridge->Mem)) {\r |
4a50cf4e RN |
141 | ASSERT (Bridge->Mem.Limit < SIZE_4GB);\r |
142 | if (Bridge->Mem.Limit >= SIZE_4GB) {\r | |
143 | return NULL;\r | |
144 | }\r | |
145 | }\r | |
1436aea4 | 146 | \r |
b8bfb92b | 147 | if (RESOURCE_VALID (&Bridge->MemAbove4G)) {\r |
4a50cf4e RN |
148 | ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);\r |
149 | if (Bridge->MemAbove4G.Base < SIZE_4GB) {\r | |
150 | return NULL;\r | |
151 | }\r | |
152 | }\r | |
1436aea4 | 153 | \r |
b8bfb92b | 154 | if (RESOURCE_VALID (&Bridge->PMem)) {\r |
4a50cf4e RN |
155 | ASSERT (Bridge->PMem.Limit < SIZE_4GB);\r |
156 | if (Bridge->PMem.Limit >= SIZE_4GB) {\r | |
157 | return NULL;\r | |
158 | }\r | |
159 | }\r | |
1436aea4 | 160 | \r |
b8bfb92b | 161 | if (RESOURCE_VALID (&Bridge->PMemAbove4G)) {\r |
4a50cf4e RN |
162 | ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);\r |
163 | if (Bridge->PMemAbove4G.Base < SIZE_4GB) {\r | |
164 | return NULL;\r | |
165 | }\r | |
166 | }\r | |
167 | \r | |
401f8cd1 RN |
168 | //\r |
169 | // Ignore AllocationAttributes when resources were already assigned.\r | |
170 | //\r | |
171 | if (!Bridge->ResourceAssigned) {\r | |
172 | if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r | |
173 | //\r | |
174 | // If this bit is set, then the PCI Root Bridge does not\r | |
175 | // support separate windows for Non-prefetchable and Prefetchable\r | |
176 | // memory.\r | |
177 | //\r | |
b8bfb92b RN |
178 | ASSERT (!RESOURCE_VALID (&Bridge->PMem));\r |
179 | ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));\r | |
180 | if (RESOURCE_VALID (&Bridge->PMem) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {\r | |
401f8cd1 RN |
181 | return NULL;\r |
182 | }\r | |
4a50cf4e | 183 | }\r |
4a50cf4e | 184 | \r |
401f8cd1 RN |
185 | if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {\r |
186 | //\r | |
187 | // If this bit is not set, then the PCI Root Bridge does not support\r | |
188 | // 64 bit memory windows.\r | |
189 | //\r | |
b8bfb92b RN |
190 | ASSERT (!RESOURCE_VALID (&Bridge->MemAbove4G));\r |
191 | ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));\r | |
192 | if (RESOURCE_VALID (&Bridge->MemAbove4G) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {\r | |
401f8cd1 RN |
193 | return NULL;\r |
194 | }\r | |
4a50cf4e RN |
195 | }\r |
196 | }\r | |
197 | \r | |
198 | RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));\r | |
199 | ASSERT (RootBridge != NULL);\r | |
200 | \r | |
1436aea4 MK |
201 | RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r |
202 | RootBridge->Supports = Bridge->Supports;\r | |
203 | RootBridge->Attributes = Bridge->Attributes;\r | |
204 | RootBridge->DmaAbove4G = Bridge->DmaAbove4G;\r | |
014b4720 | 205 | RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;\r |
1436aea4 MK |
206 | RootBridge->AllocationAttributes = Bridge->AllocationAttributes;\r |
207 | RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);\r | |
208 | RootBridge->DevicePathStr = DevicePathStr;\r | |
209 | RootBridge->ConfigBuffer = AllocatePool (\r | |
210 | TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r | |
211 | );\r | |
4a50cf4e RN |
212 | ASSERT (RootBridge->ConfigBuffer != NULL);\r |
213 | InitializeListHead (&RootBridge->Maps);\r | |
214 | \r | |
215 | CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
216 | CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
217 | CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
218 | CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
814f4306 RN |
219 | CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r |
220 | CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
4a50cf4e RN |
221 | \r |
222 | for (Index = TypeIo; Index < TypeMax; Index++) {\r | |
401f8cd1 | 223 | switch (Index) {\r |
1436aea4 MK |
224 | case TypeBus:\r |
225 | Aperture = &RootBridge->Bus;\r | |
226 | break;\r | |
227 | case TypeIo:\r | |
228 | Aperture = &RootBridge->Io;\r | |
229 | break;\r | |
230 | case TypeMem32:\r | |
231 | Aperture = &RootBridge->Mem;\r | |
232 | break;\r | |
233 | case TypeMem64:\r | |
234 | Aperture = &RootBridge->MemAbove4G;\r | |
235 | break;\r | |
236 | case TypePMem32:\r | |
237 | Aperture = &RootBridge->PMem;\r | |
238 | break;\r | |
239 | case TypePMem64:\r | |
240 | Aperture = &RootBridge->PMemAbove4G;\r | |
241 | break;\r | |
242 | default:\r | |
243 | ASSERT (FALSE);\r | |
244 | Aperture = NULL;\r | |
245 | break;\r | |
401f8cd1 | 246 | }\r |
1436aea4 MK |
247 | \r |
248 | RootBridge->ResAllocNode[Index].Type = Index;\r | |
401f8cd1 | 249 | if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {\r |
74d0a339 HG |
250 | //\r |
251 | // Base in ResAllocNode is a host address, while Base in Aperture is a\r | |
252 | // device address.\r | |
253 | //\r | |
1436aea4 MK |
254 | RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (\r |
255 | Aperture->Base,\r | |
256 | Aperture->Translation\r | |
257 | );\r | |
401f8cd1 RN |
258 | RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;\r |
259 | RootBridge->ResAllocNode[Index].Status = ResAllocated;\r | |
260 | } else {\r | |
261 | RootBridge->ResAllocNode[Index].Base = 0;\r | |
262 | RootBridge->ResAllocNode[Index].Length = 0;\r | |
263 | RootBridge->ResAllocNode[Index].Status = ResNone;\r | |
264 | }\r | |
4a50cf4e RN |
265 | }\r |
266 | \r | |
267 | RootBridge->RootBridgeIo.SegmentNumber = Bridge->Segment;\r | |
4a50cf4e RN |
268 | RootBridge->RootBridgeIo.PollMem = RootBridgeIoPollMem;\r |
269 | RootBridge->RootBridgeIo.PollIo = RootBridgeIoPollIo;\r | |
270 | RootBridge->RootBridgeIo.Mem.Read = RootBridgeIoMemRead;\r | |
271 | RootBridge->RootBridgeIo.Mem.Write = RootBridgeIoMemWrite;\r | |
272 | RootBridge->RootBridgeIo.Io.Read = RootBridgeIoIoRead;\r | |
273 | RootBridge->RootBridgeIo.Io.Write = RootBridgeIoIoWrite;\r | |
274 | RootBridge->RootBridgeIo.CopyMem = RootBridgeIoCopyMem;\r | |
275 | RootBridge->RootBridgeIo.Pci.Read = RootBridgeIoPciRead;\r | |
276 | RootBridge->RootBridgeIo.Pci.Write = RootBridgeIoPciWrite;\r | |
277 | RootBridge->RootBridgeIo.Map = RootBridgeIoMap;\r | |
278 | RootBridge->RootBridgeIo.Unmap = RootBridgeIoUnmap;\r | |
279 | RootBridge->RootBridgeIo.AllocateBuffer = RootBridgeIoAllocateBuffer;\r | |
280 | RootBridge->RootBridgeIo.FreeBuffer = RootBridgeIoFreeBuffer;\r | |
281 | RootBridge->RootBridgeIo.Flush = RootBridgeIoFlush;\r | |
282 | RootBridge->RootBridgeIo.GetAttributes = RootBridgeIoGetAttributes;\r | |
283 | RootBridge->RootBridgeIo.SetAttributes = RootBridgeIoSetAttributes;\r | |
284 | RootBridge->RootBridgeIo.Configuration = RootBridgeIoConfiguration;\r | |
285 | \r | |
286 | return RootBridge;\r | |
287 | }\r | |
288 | \r | |
289 | /**\r | |
290 | Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r | |
291 | \r | |
292 | The I/O operations are carried out exactly as requested. The caller is\r | |
293 | responsible for satisfying any alignment and I/O width restrictions that a PI\r | |
294 | System on a platform might require. For example on some platforms, width\r | |
295 | requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other\r | |
296 | hand, will be handled by the driver.\r | |
297 | \r | |
298 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
299 | \r | |
300 | @param[in] OperationType I/O operation type: IO/MMIO/PCI.\r | |
301 | \r | |
302 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
303 | \r | |
304 | @param[in] Address The base address of the I/O operation.\r | |
305 | \r | |
306 | @param[in] Count The number of I/O operations to perform. The number\r | |
307 | of bytes moved is Width size * Count, starting at\r | |
308 | Address.\r | |
309 | \r | |
310 | @param[in] Buffer For read operations, the destination buffer to\r | |
311 | store the results. For write operations, the source\r | |
312 | buffer from which to write data.\r | |
313 | \r | |
314 | @retval EFI_SUCCESS The parameters for this request pass the\r | |
315 | checks.\r | |
316 | \r | |
317 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
318 | \r | |
319 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
320 | \r | |
666d05a0 RN |
321 | @retval EFI_INVALID_PARAMETER Address or Count is invalid.\r |
322 | \r | |
4a50cf4e RN |
323 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r |
324 | \r | |
325 | @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r | |
326 | and Count is not valid for this PI system.\r | |
327 | **/\r | |
328 | EFI_STATUS\r | |
329 | RootBridgeIoCheckParameter (\r | |
330 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
331 | IN OPERATION_TYPE OperationType,\r | |
332 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
333 | IN UINT64 Address,\r | |
334 | IN UINTN Count,\r | |
335 | IN VOID *Buffer\r | |
336 | )\r | |
337 | {\r | |
338 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
339 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r | |
340 | UINT64 Base;\r | |
341 | UINT64 Limit;\r | |
342 | UINT32 Size;\r | |
666d05a0 | 343 | UINT64 Length;\r |
4a50cf4e RN |
344 | \r |
345 | //\r | |
346 | // Check to see if Buffer is NULL\r | |
347 | //\r | |
348 | if (Buffer == NULL) {\r | |
349 | return EFI_INVALID_PARAMETER;\r | |
350 | }\r | |
351 | \r | |
352 | //\r | |
353 | // Check to see if Width is in the valid range\r | |
354 | //\r | |
1436aea4 | 355 | if ((UINT32)Width >= EfiPciWidthMaximum) {\r |
4a50cf4e RN |
356 | return EFI_INVALID_PARAMETER;\r |
357 | }\r | |
358 | \r | |
359 | //\r | |
666d05a0 | 360 | // For FIFO type, the device address won't increase during the access,\r |
4a50cf4e RN |
361 | // so treat Count as 1\r |
362 | //\r | |
1436aea4 | 363 | if ((Width >= EfiPciWidthFifoUint8) && (Width <= EfiPciWidthFifoUint64)) {\r |
4a50cf4e RN |
364 | Count = 1;\r |
365 | }\r | |
366 | \r | |
1436aea4 | 367 | Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);\r |
4a50cf4e RN |
368 | Size = 1 << Width;\r |
369 | \r | |
666d05a0 RN |
370 | //\r |
371 | // Make sure (Count * Size) doesn't exceed MAX_UINT64\r | |
372 | //\r | |
373 | if (Count > DivU64x32 (MAX_UINT64, Size)) {\r | |
374 | return EFI_INVALID_PARAMETER;\r | |
375 | }\r | |
376 | \r | |
4a50cf4e RN |
377 | //\r |
378 | // Check to see if Address is aligned\r | |
379 | //\r | |
380 | if ((Address & (Size - 1)) != 0) {\r | |
381 | return EFI_UNSUPPORTED;\r | |
382 | }\r | |
383 | \r | |
666d05a0 RN |
384 | //\r |
385 | // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64\r | |
386 | //\r | |
387 | Length = MultU64x32 (Count, Size);\r | |
388 | if (Address > MAX_UINT64 - Length) {\r | |
389 | return EFI_INVALID_PARAMETER;\r | |
390 | }\r | |
391 | \r | |
4a50cf4e RN |
392 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r |
393 | \r | |
394 | //\r | |
395 | // Check to see if any address associated with this transfer exceeds the\r | |
396 | // maximum allowed address. The maximum address implied by the parameters\r | |
397 | // passed in is Address + Size * Count. If the following condition is met,\r | |
398 | // then the transfer is not supported.\r | |
399 | //\r | |
400 | // Address + Size * Count > Limit + 1\r | |
401 | //\r | |
402 | // Since Limit can be the maximum integer value supported by the CPU and\r | |
403 | // Count can also be the maximum integer value supported by the CPU, this\r | |
404 | // range check must be adjusted to avoid all oveflow conditions.\r | |
405 | //\r | |
406 | if (OperationType == IoOperation) {\r | |
407 | //\r | |
408 | // Allow Legacy IO access\r | |
409 | //\r | |
666d05a0 | 410 | if (Address + Length <= 0x1000) {\r |
4a50cf4e | 411 | if ((RootBridge->Attributes & (\r |
1436aea4 MK |
412 | EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |\r |
413 | EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r | |
414 | EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0)\r | |
415 | {\r | |
4a50cf4e RN |
416 | return EFI_SUCCESS;\r |
417 | }\r | |
418 | }\r | |
1436aea4 MK |
419 | \r |
420 | Base = RootBridge->Io.Base;\r | |
4a50cf4e RN |
421 | Limit = RootBridge->Io.Limit;\r |
422 | } else if (OperationType == MemOperation) {\r | |
423 | //\r | |
424 | // Allow Legacy MMIO access\r | |
425 | //\r | |
1436aea4 | 426 | if ((Address >= 0xA0000) && ((Address + Length) <= 0xC0000)) {\r |
4a50cf4e RN |
427 | if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {\r |
428 | return EFI_SUCCESS;\r | |
429 | }\r | |
430 | }\r | |
1436aea4 | 431 | \r |
4a50cf4e RN |
432 | //\r |
433 | // By comparing the Address against Limit we know which range to be used\r | |
434 | // for checking\r | |
435 | //\r | |
bff6584d RN |
436 | if ((Address >= RootBridge->Mem.Base) && (Address + Length <= RootBridge->Mem.Limit + 1)) {\r |
437 | Base = RootBridge->Mem.Base;\r | |
4a50cf4e | 438 | Limit = RootBridge->Mem.Limit;\r |
bff6584d RN |
439 | } else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= RootBridge->PMem.Limit + 1)) {\r |
440 | Base = RootBridge->PMem.Base;\r | |
441 | Limit = RootBridge->PMem.Limit;\r | |
442 | } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= RootBridge->MemAbove4G.Limit + 1)) {\r | |
443 | Base = RootBridge->MemAbove4G.Base;\r | |
4a50cf4e | 444 | Limit = RootBridge->MemAbove4G.Limit;\r |
bff6584d RN |
445 | } else {\r |
446 | Base = RootBridge->PMemAbove4G.Base;\r | |
447 | Limit = RootBridge->PMemAbove4G.Limit;\r | |
4a50cf4e RN |
448 | }\r |
449 | } else {\r | |
1436aea4 MK |
450 | PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&Address;\r |
451 | if ((PciRbAddr->Bus < RootBridge->Bus.Base) ||\r | |
452 | (PciRbAddr->Bus > RootBridge->Bus.Limit))\r | |
453 | {\r | |
4a50cf4e RN |
454 | return EFI_INVALID_PARAMETER;\r |
455 | }\r | |
456 | \r | |
1436aea4 MK |
457 | if ((PciRbAddr->Device > PCI_MAX_DEVICE) ||\r |
458 | (PciRbAddr->Function > PCI_MAX_FUNC))\r | |
459 | {\r | |
4a50cf4e RN |
460 | return EFI_INVALID_PARAMETER;\r |
461 | }\r | |
462 | \r | |
463 | if (PciRbAddr->ExtendedRegister != 0) {\r | |
464 | Address = PciRbAddr->ExtendedRegister;\r | |
465 | } else {\r | |
466 | Address = PciRbAddr->Register;\r | |
467 | }\r | |
1436aea4 MK |
468 | \r |
469 | Base = 0;\r | |
014b4720 | 470 | Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;\r |
4a50cf4e RN |
471 | }\r |
472 | \r | |
473 | if (Address < Base) {\r | |
1436aea4 | 474 | return EFI_INVALID_PARAMETER;\r |
4a50cf4e RN |
475 | }\r |
476 | \r | |
666d05a0 | 477 | if (Address + Length > Limit + 1) {\r |
4a50cf4e RN |
478 | return EFI_INVALID_PARAMETER;\r |
479 | }\r | |
480 | \r | |
481 | return EFI_SUCCESS;\r | |
482 | }\r | |
483 | \r | |
74d0a339 HG |
484 | /**\r |
485 | Use address to match apertures of memory type and then get the corresponding\r | |
486 | translation.\r | |
487 | \r | |
488 | @param RootBridge The root bridge instance.\r | |
489 | @param Address The address used to match aperture.\r | |
490 | @param Translation Pointer containing the output translation.\r | |
491 | \r | |
492 | @return EFI_SUCCESS Get translation successfully.\r | |
493 | @return EFI_INVALID_PARAMETER No matched memory aperture; the input Address\r | |
494 | must be invalid.\r | |
495 | **/\r | |
496 | EFI_STATUS\r | |
497 | RootBridgeIoGetMemTranslationByAddress (\r | |
1436aea4 MK |
498 | IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,\r |
499 | IN UINT64 Address,\r | |
500 | IN OUT UINT64 *Translation\r | |
74d0a339 HG |
501 | )\r |
502 | {\r | |
1436aea4 | 503 | if ((Address >= RootBridge->Mem.Base) && (Address <= RootBridge->Mem.Limit)) {\r |
74d0a339 | 504 | *Translation = RootBridge->Mem.Translation;\r |
1436aea4 | 505 | } else if ((Address >= RootBridge->PMem.Base) && (Address <= RootBridge->PMem.Limit)) {\r |
74d0a339 | 506 | *Translation = RootBridge->PMem.Translation;\r |
1436aea4 | 507 | } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address <= RootBridge->MemAbove4G.Limit)) {\r |
74d0a339 | 508 | *Translation = RootBridge->MemAbove4G.Translation;\r |
1436aea4 | 509 | } else if ((Address >= RootBridge->PMemAbove4G.Base) && (Address <= RootBridge->PMemAbove4G.Limit)) {\r |
74d0a339 HG |
510 | *Translation = RootBridge->PMemAbove4G.Translation;\r |
511 | } else {\r | |
512 | return EFI_INVALID_PARAMETER;\r | |
513 | }\r | |
514 | \r | |
515 | return EFI_SUCCESS;\r | |
516 | }\r | |
517 | \r | |
0edb7ec5 RN |
518 | /**\r |
519 | Return the result of (Multiplicand * Multiplier / Divisor).\r | |
520 | \r | |
521 | @param Multiplicand A 64-bit unsigned value.\r | |
522 | @param Multiplier A 64-bit unsigned value.\r | |
523 | @param Divisor A 32-bit unsigned value.\r | |
524 | @param Remainder A pointer to a 32-bit unsigned value. This parameter is\r | |
525 | optional and may be NULL.\r | |
526 | \r | |
527 | @return Multiplicand * Multiplier / Divisor.\r | |
528 | **/\r | |
529 | UINT64\r | |
530 | MultThenDivU64x64x32 (\r | |
1436aea4 MK |
531 | IN UINT64 Multiplicand,\r |
532 | IN UINT64 Multiplier,\r | |
533 | IN UINT32 Divisor,\r | |
534 | OUT UINT32 *Remainder OPTIONAL\r | |
0edb7ec5 RN |
535 | )\r |
536 | {\r | |
1436aea4 MK |
537 | UINT64 Uint64;\r |
538 | UINT32 LocalRemainder;\r | |
539 | UINT32 Uint32;\r | |
540 | \r | |
0edb7ec5 RN |
541 | if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) {\r |
542 | //\r | |
543 | // Make sure Multiplicand is the bigger one.\r | |
544 | //\r | |
545 | if (Multiplicand < Multiplier) {\r | |
546 | Uint64 = Multiplicand;\r | |
547 | Multiplicand = Multiplier;\r | |
548 | Multiplier = Uint64;\r | |
549 | }\r | |
1436aea4 | 550 | \r |
0edb7ec5 RN |
551 | //\r |
552 | // Because Multiplicand * Multiplier overflows,\r | |
553 | // Multiplicand * Multiplier / Divisor\r | |
554 | // = (2 * Multiplicand' + 1) * Multiplier / Divisor\r | |
555 | // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor\r | |
556 | //\r | |
557 | Uint64 = MultThenDivU64x64x32 (RShiftU64 (Multiplicand, 1), Multiplier, Divisor, &LocalRemainder);\r | |
558 | Uint64 = LShiftU64 (Uint64, 1);\r | |
559 | Uint32 = 0;\r | |
560 | if ((Multiplicand & 0x1) == 1) {\r | |
561 | Uint64 += DivU64x32Remainder (Multiplier, Divisor, &Uint32);\r | |
562 | }\r | |
1436aea4 | 563 | \r |
0edb7ec5 RN |
564 | return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder, 1), Divisor, Remainder);\r |
565 | } else {\r | |
566 | return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divisor, Remainder);\r | |
567 | }\r | |
568 | }\r | |
569 | \r | |
570 | /**\r | |
571 | Return the elapsed tick count from CurrentTick.\r | |
572 | \r | |
573 | @param CurrentTick On input, the previous tick count.\r | |
574 | On output, the current tick count.\r | |
575 | @param StartTick The value the performance counter starts with when it\r | |
576 | rolls over.\r | |
577 | @param EndTick The value that the performance counter ends with before\r | |
578 | it rolls over.\r | |
579 | \r | |
580 | @return The elapsed tick count from CurrentTick.\r | |
581 | **/\r | |
582 | UINT64\r | |
583 | GetElapsedTick (\r | |
584 | UINT64 *CurrentTick,\r | |
585 | UINT64 StartTick,\r | |
586 | UINT64 EndTick\r | |
587 | )\r | |
588 | {\r | |
589 | UINT64 PreviousTick;\r | |
d1102dba | 590 | \r |
0edb7ec5 | 591 | PreviousTick = *CurrentTick;\r |
1436aea4 | 592 | *CurrentTick = GetPerformanceCounter ();\r |
0edb7ec5 RN |
593 | if (StartTick < EndTick) {\r |
594 | return *CurrentTick - PreviousTick;\r | |
595 | } else {\r | |
596 | return PreviousTick - *CurrentTick;\r | |
597 | }\r | |
598 | }\r | |
599 | \r | |
4a50cf4e RN |
600 | /**\r |
601 | Polls an address in memory mapped I/O space until an exit condition is met,\r | |
602 | or a timeout occurs.\r | |
603 | \r | |
604 | This function provides a standard way to poll a PCI memory location. A PCI\r | |
605 | memory read operation is performed at the PCI memory address specified by\r | |
606 | Address for the width specified by Width. The result of this PCI memory read\r | |
607 | operation is stored in Result. This PCI memory read operation is repeated\r | |
608 | until either a timeout of Delay 100 ns units has expired, or (Result & Mask)\r | |
609 | is equal to Value.\r | |
610 | \r | |
611 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
612 | @param[in] Width Signifies the width of the memory operations.\r | |
613 | @param[in] Address The base address of the memory operations. The caller\r | |
614 | is responsible for aligning Address if required.\r | |
615 | @param[in] Mask Mask used for the polling criteria. Bytes above Width\r | |
616 | in Mask are ignored. The bits in the bytes below Width\r | |
617 | which are zero in Mask are ignored when polling the\r | |
618 | memory address.\r | |
619 | @param[in] Value The comparison value used for the polling exit\r | |
620 | criteria.\r | |
621 | @param[in] Delay The number of 100 ns units to poll. Note that timer\r | |
622 | available may be of poorer granularity.\r | |
623 | @param[out] Result Pointer to the last value read from the memory\r | |
624 | location.\r | |
625 | \r | |
626 | @retval EFI_SUCCESS The last data returned from the access matched\r | |
627 | the poll exit criteria.\r | |
628 | @retval EFI_INVALID_PARAMETER Width is invalid.\r | |
629 | @retval EFI_INVALID_PARAMETER Result is NULL.\r | |
630 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
631 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
632 | lack of resources.\r | |
633 | **/\r | |
4a50cf4e RN |
634 | EFI_STATUS\r |
635 | EFIAPI\r | |
636 | RootBridgeIoPollMem (\r | |
637 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
638 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
639 | IN UINT64 Address,\r | |
640 | IN UINT64 Mask,\r | |
641 | IN UINT64 Value,\r | |
642 | IN UINT64 Delay,\r | |
643 | OUT UINT64 *Result\r | |
644 | )\r | |
645 | {\r | |
646 | EFI_STATUS Status;\r | |
647 | UINT64 NumberOfTicks;\r | |
648 | UINT32 Remainder;\r | |
0edb7ec5 RN |
649 | UINT64 StartTick;\r |
650 | UINT64 EndTick;\r | |
651 | UINT64 CurrentTick;\r | |
652 | UINT64 ElapsedTick;\r | |
653 | UINT64 Frequency;\r | |
4a50cf4e RN |
654 | \r |
655 | if (Result == NULL) {\r | |
656 | return EFI_INVALID_PARAMETER;\r | |
657 | }\r | |
658 | \r | |
659 | if ((UINT32)Width > EfiPciWidthUint64) {\r | |
660 | return EFI_INVALID_PARAMETER;\r | |
661 | }\r | |
662 | \r | |
663 | //\r | |
664 | // No matter what, always do a single poll.\r | |
665 | //\r | |
666 | Status = This->Mem.Read (This, Width, Address, 1, Result);\r | |
667 | if (EFI_ERROR (Status)) {\r | |
668 | return Status;\r | |
669 | }\r | |
670 | \r | |
671 | if ((*Result & Mask) == Value) {\r | |
672 | return EFI_SUCCESS;\r | |
673 | }\r | |
674 | \r | |
675 | if (Delay == 0) {\r | |
676 | return EFI_SUCCESS;\r | |
4a50cf4e | 677 | } else {\r |
4a50cf4e | 678 | //\r |
0edb7ec5 | 679 | // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)\r |
4a50cf4e | 680 | //\r |
0edb7ec5 | 681 | Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);\r |
1436aea4 MK |
682 | NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);\r |
683 | if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {\r | |
0edb7ec5 | 684 | NumberOfTicks++;\r |
4a50cf4e | 685 | }\r |
1436aea4 MK |
686 | \r |
687 | for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()\r | |
688 | ; ElapsedTick <= NumberOfTicks\r | |
689 | ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)\r | |
690 | )\r | |
691 | {\r | |
4a50cf4e RN |
692 | Status = This->Mem.Read (This, Width, Address, 1, Result);\r |
693 | if (EFI_ERROR (Status)) {\r | |
694 | return Status;\r | |
695 | }\r | |
696 | \r | |
697 | if ((*Result & Mask) == Value) {\r | |
698 | return EFI_SUCCESS;\r | |
699 | }\r | |
4a50cf4e RN |
700 | }\r |
701 | }\r | |
1436aea4 | 702 | \r |
4a50cf4e RN |
703 | return EFI_TIMEOUT;\r |
704 | }\r | |
705 | \r | |
706 | /**\r | |
707 | Reads from the I/O space of a PCI Root Bridge. Returns when either the\r | |
708 | polling exit criteria is satisfied or after a defined duration.\r | |
709 | \r | |
710 | This function provides a standard way to poll a PCI I/O location. A PCI I/O\r | |
711 | read operation is performed at the PCI I/O address specified by Address for\r | |
712 | the width specified by Width.\r | |
713 | The result of this PCI I/O read operation is stored in Result. This PCI I/O\r | |
714 | read operation is repeated until either a timeout of Delay 100 ns units has\r | |
715 | expired, or (Result & Mask) is equal to Value.\r | |
716 | \r | |
717 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
718 | @param[in] Width Signifies the width of the I/O operations.\r | |
719 | @param[in] Address The base address of the I/O operations. The caller is\r | |
720 | responsible for aligning Address if required.\r | |
721 | @param[in] Mask Mask used for the polling criteria. Bytes above Width in\r | |
722 | Mask are ignored. The bits in the bytes below Width\r | |
723 | which are zero in Mask are ignored when polling the I/O\r | |
724 | address.\r | |
725 | @param[in] Value The comparison value used for the polling exit criteria.\r | |
726 | @param[in] Delay The number of 100 ns units to poll. Note that timer\r | |
727 | available may be of poorer granularity.\r | |
728 | @param[out] Result Pointer to the last value read from the memory location.\r | |
729 | \r | |
730 | @retval EFI_SUCCESS The last data returned from the access matched\r | |
731 | the poll exit criteria.\r | |
732 | @retval EFI_INVALID_PARAMETER Width is invalid.\r | |
733 | @retval EFI_INVALID_PARAMETER Result is NULL.\r | |
734 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
735 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
736 | lack of resources.\r | |
737 | **/\r | |
738 | EFI_STATUS\r | |
739 | EFIAPI\r | |
740 | RootBridgeIoPollIo (\r | |
741 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
742 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
743 | IN UINT64 Address,\r | |
744 | IN UINT64 Mask,\r | |
745 | IN UINT64 Value,\r | |
746 | IN UINT64 Delay,\r | |
747 | OUT UINT64 *Result\r | |
748 | )\r | |
749 | {\r | |
750 | EFI_STATUS Status;\r | |
751 | UINT64 NumberOfTicks;\r | |
752 | UINT32 Remainder;\r | |
0edb7ec5 RN |
753 | UINT64 StartTick;\r |
754 | UINT64 EndTick;\r | |
755 | UINT64 CurrentTick;\r | |
756 | UINT64 ElapsedTick;\r | |
757 | UINT64 Frequency;\r | |
4a50cf4e RN |
758 | \r |
759 | //\r | |
760 | // No matter what, always do a single poll.\r | |
761 | //\r | |
762 | \r | |
763 | if (Result == NULL) {\r | |
764 | return EFI_INVALID_PARAMETER;\r | |
765 | }\r | |
766 | \r | |
767 | if ((UINT32)Width > EfiPciWidthUint64) {\r | |
768 | return EFI_INVALID_PARAMETER;\r | |
769 | }\r | |
770 | \r | |
771 | Status = This->Io.Read (This, Width, Address, 1, Result);\r | |
772 | if (EFI_ERROR (Status)) {\r | |
773 | return Status;\r | |
774 | }\r | |
1436aea4 | 775 | \r |
4a50cf4e RN |
776 | if ((*Result & Mask) == Value) {\r |
777 | return EFI_SUCCESS;\r | |
778 | }\r | |
779 | \r | |
780 | if (Delay == 0) {\r | |
781 | return EFI_SUCCESS;\r | |
4a50cf4e | 782 | } else {\r |
4a50cf4e | 783 | //\r |
0edb7ec5 | 784 | // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)\r |
4a50cf4e | 785 | //\r |
0edb7ec5 | 786 | Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);\r |
1436aea4 MK |
787 | NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);\r |
788 | if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {\r | |
0edb7ec5 | 789 | NumberOfTicks++;\r |
4a50cf4e | 790 | }\r |
1436aea4 MK |
791 | \r |
792 | for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()\r | |
793 | ; ElapsedTick <= NumberOfTicks\r | |
794 | ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)\r | |
795 | )\r | |
796 | {\r | |
4a50cf4e RN |
797 | Status = This->Io.Read (This, Width, Address, 1, Result);\r |
798 | if (EFI_ERROR (Status)) {\r | |
799 | return Status;\r | |
800 | }\r | |
801 | \r | |
802 | if ((*Result & Mask) == Value) {\r | |
803 | return EFI_SUCCESS;\r | |
804 | }\r | |
4a50cf4e RN |
805 | }\r |
806 | }\r | |
1436aea4 | 807 | \r |
4a50cf4e RN |
808 | return EFI_TIMEOUT;\r |
809 | }\r | |
810 | \r | |
811 | /**\r | |
812 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
813 | bridge memory space.\r | |
814 | \r | |
815 | The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r | |
816 | controller registers in the PCI root bridge memory space.\r | |
817 | The memory operations are carried out exactly as requested. The caller is\r | |
818 | responsible for satisfying any alignment and memory width restrictions that a\r | |
819 | PCI Root Bridge on a platform might require.\r | |
820 | \r | |
821 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
822 | @param[in] Width Signifies the width of the memory operation.\r | |
823 | @param[in] Address The base address of the memory operation. The caller\r | |
824 | is responsible for aligning the Address if required.\r | |
825 | @param[in] Count The number of memory operations to perform. Bytes\r | |
826 | moved is Width size * Count, starting at Address.\r | |
827 | @param[out] Buffer For read operations, the destination buffer to store\r | |
828 | the results. For write operations, the source buffer\r | |
829 | to write data from.\r | |
830 | \r | |
831 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
832 | root bridge.\r | |
833 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
834 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
835 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
836 | lack of resources.\r | |
837 | **/\r | |
838 | EFI_STATUS\r | |
839 | EFIAPI\r | |
840 | RootBridgeIoMemRead (\r | |
841 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
842 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
843 | IN UINT64 Address,\r | |
844 | IN UINTN Count,\r | |
845 | OUT VOID *Buffer\r | |
846 | )\r | |
847 | {\r | |
1436aea4 MK |
848 | EFI_STATUS Status;\r |
849 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
850 | UINT64 Translation;\r | |
4a50cf4e | 851 | \r |
1436aea4 MK |
852 | Status = RootBridgeIoCheckParameter (\r |
853 | This,\r | |
854 | MemOperation,\r | |
855 | Width,\r | |
856 | Address,\r | |
857 | Count,\r | |
858 | Buffer\r | |
859 | );\r | |
4a50cf4e RN |
860 | if (EFI_ERROR (Status)) {\r |
861 | return Status;\r | |
862 | }\r | |
74d0a339 HG |
863 | \r |
864 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1436aea4 | 865 | Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);\r |
74d0a339 HG |
866 | if (EFI_ERROR (Status)) {\r |
867 | return Status;\r | |
868 | }\r | |
869 | \r | |
870 | // Address passed to CpuIo->Mem.Read needs to be a host address instead of\r | |
871 | // device address.\r | |
1436aea4 MK |
872 | return mCpuIo->Mem.Read (\r |
873 | mCpuIo,\r | |
874 | (EFI_CPU_IO_PROTOCOL_WIDTH)Width,\r | |
875 | TO_HOST_ADDRESS (Address, Translation),\r | |
876 | Count,\r | |
877 | Buffer\r | |
878 | );\r | |
4a50cf4e RN |
879 | }\r |
880 | \r | |
881 | /**\r | |
882 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
883 | bridge memory space.\r | |
884 | \r | |
885 | The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r | |
886 | controller registers in the PCI root bridge memory space.\r | |
887 | The memory operations are carried out exactly as requested. The caller is\r | |
888 | responsible for satisfying any alignment and memory width restrictions that a\r | |
889 | PCI Root Bridge on a platform might require.\r | |
890 | \r | |
891 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
892 | @param[in] Width Signifies the width of the memory operation.\r | |
893 | @param[in] Address The base address of the memory operation. The caller\r | |
894 | is responsible for aligning the Address if required.\r | |
895 | @param[in] Count The number of memory operations to perform. Bytes\r | |
896 | moved is Width size * Count, starting at Address.\r | |
897 | @param[in] Buffer For read operations, the destination buffer to store\r | |
898 | the results. For write operations, the source buffer\r | |
899 | to write data from.\r | |
900 | \r | |
901 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
902 | root bridge.\r | |
903 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
904 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
905 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
906 | lack of resources.\r | |
907 | **/\r | |
908 | EFI_STATUS\r | |
909 | EFIAPI\r | |
910 | RootBridgeIoMemWrite (\r | |
911 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
912 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
913 | IN UINT64 Address,\r | |
914 | IN UINTN Count,\r | |
915 | IN VOID *Buffer\r | |
916 | )\r | |
917 | {\r | |
1436aea4 MK |
918 | EFI_STATUS Status;\r |
919 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
920 | UINT64 Translation;\r | |
4a50cf4e | 921 | \r |
1436aea4 MK |
922 | Status = RootBridgeIoCheckParameter (\r |
923 | This,\r | |
924 | MemOperation,\r | |
925 | Width,\r | |
926 | Address,\r | |
927 | Count,\r | |
928 | Buffer\r | |
929 | );\r | |
4a50cf4e RN |
930 | if (EFI_ERROR (Status)) {\r |
931 | return Status;\r | |
932 | }\r | |
74d0a339 HG |
933 | \r |
934 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1436aea4 | 935 | Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);\r |
74d0a339 HG |
936 | if (EFI_ERROR (Status)) {\r |
937 | return Status;\r | |
938 | }\r | |
939 | \r | |
940 | // Address passed to CpuIo->Mem.Write needs to be a host address instead of\r | |
941 | // device address.\r | |
1436aea4 MK |
942 | return mCpuIo->Mem.Write (\r |
943 | mCpuIo,\r | |
944 | (EFI_CPU_IO_PROTOCOL_WIDTH)Width,\r | |
945 | TO_HOST_ADDRESS (Address, Translation),\r | |
946 | Count,\r | |
947 | Buffer\r | |
948 | );\r | |
4a50cf4e RN |
949 | }\r |
950 | \r | |
951 | /**\r | |
952 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
953 | bridge I/O space.\r | |
954 | \r | |
955 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
956 | @param[in] Width Signifies the width of the memory operations.\r | |
957 | @param[in] Address The base address of the I/O operation. The caller is\r | |
958 | responsible for aligning the Address if required.\r | |
959 | @param[in] Count The number of I/O operations to perform. Bytes moved\r | |
960 | is Width size * Count, starting at Address.\r | |
961 | @param[out] Buffer For read operations, the destination buffer to store\r | |
962 | the results. For write operations, the source buffer\r | |
963 | to write data from.\r | |
964 | \r | |
965 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
966 | root bridge.\r | |
967 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
968 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
969 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
970 | lack of resources.\r | |
971 | **/\r | |
972 | EFI_STATUS\r | |
973 | EFIAPI\r | |
974 | RootBridgeIoIoRead (\r | |
975 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
976 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
977 | IN UINT64 Address,\r | |
978 | IN UINTN Count,\r | |
979 | OUT VOID *Buffer\r | |
980 | )\r | |
981 | {\r | |
1436aea4 MK |
982 | EFI_STATUS Status;\r |
983 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
74d0a339 | 984 | \r |
4a50cf4e | 985 | Status = RootBridgeIoCheckParameter (\r |
1436aea4 MK |
986 | This,\r |
987 | IoOperation,\r | |
988 | Width,\r | |
989 | Address,\r | |
990 | Count,\r | |
991 | Buffer\r | |
4a50cf4e RN |
992 | );\r |
993 | if (EFI_ERROR (Status)) {\r | |
994 | return Status;\r | |
995 | }\r | |
74d0a339 HG |
996 | \r |
997 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
998 | \r | |
999 | // Address passed to CpuIo->Io.Read needs to be a host address instead of\r | |
1000 | // device address.\r | |
1436aea4 MK |
1001 | return mCpuIo->Io.Read (\r |
1002 | mCpuIo,\r | |
1003 | (EFI_CPU_IO_PROTOCOL_WIDTH)Width,\r | |
1004 | TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),\r | |
1005 | Count,\r | |
1006 | Buffer\r | |
1007 | );\r | |
4a50cf4e RN |
1008 | }\r |
1009 | \r | |
1010 | /**\r | |
1011 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
1012 | bridge I/O space.\r | |
1013 | \r | |
1014 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1015 | @param[in] Width Signifies the width of the memory operations.\r | |
1016 | @param[in] Address The base address of the I/O operation. The caller is\r | |
1017 | responsible for aligning the Address if required.\r | |
1018 | @param[in] Count The number of I/O operations to perform. Bytes moved\r | |
1019 | is Width size * Count, starting at Address.\r | |
1020 | @param[in] Buffer For read operations, the destination buffer to store\r | |
1021 | the results. For write operations, the source buffer\r | |
1022 | to write data from.\r | |
1023 | \r | |
1024 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
1025 | root bridge.\r | |
1026 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
1027 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
1028 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
1029 | lack of resources.\r | |
1030 | **/\r | |
1031 | EFI_STATUS\r | |
1032 | EFIAPI\r | |
1033 | RootBridgeIoIoWrite (\r | |
1436aea4 MK |
1034 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r |
1035 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1036 | IN UINT64 Address,\r | |
1037 | IN UINTN Count,\r | |
1038 | IN VOID *Buffer\r | |
4a50cf4e RN |
1039 | )\r |
1040 | {\r | |
1436aea4 MK |
1041 | EFI_STATUS Status;\r |
1042 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
74d0a339 | 1043 | \r |
4a50cf4e | 1044 | Status = RootBridgeIoCheckParameter (\r |
1436aea4 MK |
1045 | This,\r |
1046 | IoOperation,\r | |
1047 | Width,\r | |
1048 | Address,\r | |
1049 | Count,\r | |
1050 | Buffer\r | |
4a50cf4e RN |
1051 | );\r |
1052 | if (EFI_ERROR (Status)) {\r | |
1053 | return Status;\r | |
1054 | }\r | |
74d0a339 HG |
1055 | \r |
1056 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1057 | \r | |
1058 | // Address passed to CpuIo->Io.Write needs to be a host address instead of\r | |
1059 | // device address.\r | |
1436aea4 MK |
1060 | return mCpuIo->Io.Write (\r |
1061 | mCpuIo,\r | |
1062 | (EFI_CPU_IO_PROTOCOL_WIDTH)Width,\r | |
1063 | TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),\r | |
1064 | Count,\r | |
1065 | Buffer\r | |
1066 | );\r | |
4a50cf4e RN |
1067 | }\r |
1068 | \r | |
1069 | /**\r | |
1070 | Enables a PCI driver to copy one region of PCI root bridge memory space to\r | |
1071 | another region of PCI root bridge memory space.\r | |
1072 | \r | |
1073 | The CopyMem() function enables a PCI driver to copy one region of PCI root\r | |
1074 | bridge memory space to another region of PCI root bridge memory space. This\r | |
1075 | is especially useful for video scroll operation on a memory mapped video\r | |
1076 | buffer.\r | |
1077 | The memory operations are carried out exactly as requested. The caller is\r | |
1078 | responsible for satisfying any alignment and memory width restrictions that a\r | |
1079 | PCI root bridge on a platform might require.\r | |
1080 | \r | |
1081 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
1082 | instance.\r | |
1083 | @param[in] Width Signifies the width of the memory operations.\r | |
1084 | @param[in] DestAddress The destination address of the memory operation. The\r | |
1085 | caller is responsible for aligning the DestAddress if\r | |
1086 | required.\r | |
1087 | @param[in] SrcAddress The source address of the memory operation. The caller\r | |
1088 | is responsible for aligning the SrcAddress if\r | |
1089 | required.\r | |
1090 | @param[in] Count The number of memory operations to perform. Bytes\r | |
1091 | moved is Width size * Count, starting at DestAddress\r | |
1092 | and SrcAddress.\r | |
1093 | \r | |
1094 | @retval EFI_SUCCESS The data was copied from one memory region\r | |
1095 | to another memory region.\r | |
1096 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
1097 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
1098 | lack of resources.\r | |
1099 | **/\r | |
1100 | EFI_STATUS\r | |
1101 | EFIAPI\r | |
1102 | RootBridgeIoCopyMem (\r | |
1436aea4 MK |
1103 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r |
1104 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1105 | IN UINT64 DestAddress,\r | |
1106 | IN UINT64 SrcAddress,\r | |
1107 | IN UINTN Count\r | |
4a50cf4e RN |
1108 | )\r |
1109 | {\r | |
1110 | EFI_STATUS Status;\r | |
1111 | BOOLEAN Forward;\r | |
1112 | UINTN Stride;\r | |
1113 | UINTN Index;\r | |
1114 | UINT64 Result;\r | |
1115 | \r | |
1436aea4 | 1116 | if ((UINT32)Width > EfiPciWidthUint64) {\r |
4a50cf4e RN |
1117 | return EFI_INVALID_PARAMETER;\r |
1118 | }\r | |
1119 | \r | |
1120 | if (DestAddress == SrcAddress) {\r | |
1121 | return EFI_SUCCESS;\r | |
1122 | }\r | |
1123 | \r | |
1436aea4 | 1124 | Stride = (UINTN)(1 << Width);\r |
4a50cf4e RN |
1125 | \r |
1126 | Forward = TRUE;\r | |
1127 | if ((DestAddress > SrcAddress) &&\r | |
1436aea4 MK |
1128 | (DestAddress < (SrcAddress + Count * Stride)))\r |
1129 | {\r | |
1130 | Forward = FALSE;\r | |
1131 | SrcAddress = SrcAddress + (Count - 1) * Stride;\r | |
4a50cf4e RN |
1132 | DestAddress = DestAddress + (Count - 1) * Stride;\r |
1133 | }\r | |
1134 | \r | |
1135 | for (Index = 0; Index < Count; Index++) {\r | |
1136 | Status = RootBridgeIoMemRead (\r | |
1137 | This,\r | |
1138 | Width,\r | |
1139 | SrcAddress,\r | |
1140 | 1,\r | |
1141 | &Result\r | |
1142 | );\r | |
1143 | if (EFI_ERROR (Status)) {\r | |
1144 | return Status;\r | |
1145 | }\r | |
1436aea4 | 1146 | \r |
4a50cf4e RN |
1147 | Status = RootBridgeIoMemWrite (\r |
1148 | This,\r | |
1149 | Width,\r | |
1150 | DestAddress,\r | |
1151 | 1,\r | |
1152 | &Result\r | |
1153 | );\r | |
1154 | if (EFI_ERROR (Status)) {\r | |
1155 | return Status;\r | |
1156 | }\r | |
1436aea4 | 1157 | \r |
4a50cf4e | 1158 | if (Forward) {\r |
1436aea4 | 1159 | SrcAddress += Stride;\r |
4a50cf4e RN |
1160 | DestAddress += Stride;\r |
1161 | } else {\r | |
1436aea4 | 1162 | SrcAddress -= Stride;\r |
4a50cf4e RN |
1163 | DestAddress -= Stride;\r |
1164 | }\r | |
1165 | }\r | |
1436aea4 | 1166 | \r |
4a50cf4e RN |
1167 | return EFI_SUCCESS;\r |
1168 | }\r | |
1169 | \r | |
4a50cf4e RN |
1170 | /**\r |
1171 | PCI configuration space access.\r | |
1172 | \r | |
1173 | @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
1174 | @param Read TRUE indicating it's a read operation.\r | |
1175 | @param Width Signifies the width of the memory operation.\r | |
1176 | @param Address The address within the PCI configuration space\r | |
1177 | for the PCI controller.\r | |
1178 | @param Count The number of PCI configuration operations\r | |
1179 | to perform.\r | |
1180 | @param Buffer The destination buffer to store the results.\r | |
1181 | \r | |
1182 | @retval EFI_SUCCESS The data was read/written from/to the PCI root bridge.\r | |
1183 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1184 | **/\r | |
1185 | EFI_STATUS\r | |
1186 | EFIAPI\r | |
1187 | RootBridgeIoPciAccess (\r | |
1436aea4 MK |
1188 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r |
1189 | IN BOOLEAN Read,\r | |
1190 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1191 | IN UINT64 Address,\r | |
1192 | IN UINTN Count,\r | |
1193 | IN OUT VOID *Buffer\r | |
4a50cf4e RN |
1194 | )\r |
1195 | {\r | |
1196 | EFI_STATUS Status;\r | |
1197 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1198 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;\r | |
1199 | UINT8 *Uint8Buffer;\r | |
1200 | UINT8 InStride;\r | |
1201 | UINT8 OutStride;\r | |
1202 | UINTN Size;\r | |
1203 | \r | |
1204 | Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r | |
1205 | if (EFI_ERROR (Status)) {\r | |
1206 | return Status;\r | |
1207 | }\r | |
1208 | \r | |
1209 | //\r | |
1210 | // Read Pci configuration space\r | |
1211 | //\r | |
1212 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1213 | CopyMem (&PciAddress, &Address, sizeof (PciAddress));\r | |
1214 | \r | |
1215 | if (PciAddress.ExtendedRegister == 0) {\r | |
1216 | PciAddress.ExtendedRegister = PciAddress.Register;\r | |
1217 | }\r | |
1218 | \r | |
1219 | Address = PCI_SEGMENT_LIB_ADDRESS (\r | |
1220 | RootBridge->RootBridgeIo.SegmentNumber,\r | |
1221 | PciAddress.Bus,\r | |
1222 | PciAddress.Device,\r | |
1223 | PciAddress.Function,\r | |
1224 | PciAddress.ExtendedRegister\r | |
1225 | );\r | |
1226 | \r | |
1227 | //\r | |
1228 | // Select loop based on the width of the transfer\r | |
1229 | //\r | |
1230 | InStride = mInStride[Width];\r | |
1231 | OutStride = mOutStride[Width];\r | |
1436aea4 | 1232 | Size = (UINTN)(1 << (Width & 0x03));\r |
4a50cf4e RN |
1233 | for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r |
1234 | if (Read) {\r | |
1235 | PciSegmentReadBuffer (Address, Size, Uint8Buffer);\r | |
1236 | } else {\r | |
1237 | PciSegmentWriteBuffer (Address, Size, Uint8Buffer);\r | |
1238 | }\r | |
1239 | }\r | |
1436aea4 | 1240 | \r |
4a50cf4e RN |
1241 | return EFI_SUCCESS;\r |
1242 | }\r | |
1243 | \r | |
1244 | /**\r | |
1245 | Allows read from PCI configuration space.\r | |
1246 | \r | |
1247 | @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
1248 | @param Width Signifies the width of the memory operation.\r | |
1249 | @param Address The address within the PCI configuration space\r | |
1250 | for the PCI controller.\r | |
1251 | @param Count The number of PCI configuration operations\r | |
1252 | to perform.\r | |
1253 | @param Buffer The destination buffer to store the results.\r | |
1254 | \r | |
1255 | @retval EFI_SUCCESS The data was read from the PCI root bridge.\r | |
1256 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1257 | **/\r | |
1258 | EFI_STATUS\r | |
1259 | EFIAPI\r | |
1260 | RootBridgeIoPciRead (\r | |
1436aea4 MK |
1261 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r |
1262 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1263 | IN UINT64 Address,\r | |
1264 | IN UINTN Count,\r | |
1265 | IN OUT VOID *Buffer\r | |
4a50cf4e RN |
1266 | )\r |
1267 | {\r | |
1268 | return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);\r | |
1269 | }\r | |
1270 | \r | |
1271 | /**\r | |
1272 | Allows write to PCI configuration space.\r | |
1273 | \r | |
1274 | @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
1275 | @param Width Signifies the width of the memory operation.\r | |
1276 | @param Address The address within the PCI configuration space\r | |
1277 | for the PCI controller.\r | |
1278 | @param Count The number of PCI configuration operations\r | |
1279 | to perform.\r | |
1280 | @param Buffer The source buffer to get the results.\r | |
1281 | \r | |
1282 | @retval EFI_SUCCESS The data was written to the PCI root bridge.\r | |
1283 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1284 | **/\r | |
1285 | EFI_STATUS\r | |
1286 | EFIAPI\r | |
1287 | RootBridgeIoPciWrite (\r | |
1436aea4 MK |
1288 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r |
1289 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1290 | IN UINT64 Address,\r | |
1291 | IN UINTN Count,\r | |
1292 | IN OUT VOID *Buffer\r | |
4a50cf4e RN |
1293 | )\r |
1294 | {\r | |
1295 | return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);\r | |
1296 | }\r | |
1297 | \r | |
1298 | /**\r | |
4a50cf4e RN |
1299 | Provides the PCI controller-specific address needed to access\r |
1300 | system memory for DMA.\r | |
1301 | \r | |
1302 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1303 | @param Operation Indicate if the bus master is going to read or write\r | |
1304 | to system memory.\r | |
1305 | @param HostAddress The system memory address to map on the PCI controller.\r | |
1306 | @param NumberOfBytes On input the number of bytes to map.\r | |
1307 | On output the number of bytes that were mapped.\r | |
1308 | @param DeviceAddress The resulting map address for the bus master PCI\r | |
1309 | controller to use to access the system memory's HostAddress.\r | |
1310 | @param Mapping The value to pass to Unmap() when the bus master DMA\r | |
1311 | operation is complete.\r | |
1312 | \r | |
1313 | @retval EFI_SUCCESS Success.\r | |
1314 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1315 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
1316 | @retval EFI_DEVICE_ERROR The System hardware could not map the requested address.\r | |
1317 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.\r | |
4a50cf4e RN |
1318 | **/\r |
1319 | EFI_STATUS\r | |
1320 | EFIAPI\r | |
1321 | RootBridgeIoMap (\r | |
1322 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1323 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r | |
1324 | IN VOID *HostAddress,\r | |
1325 | IN OUT UINTN *NumberOfBytes,\r | |
1326 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
1327 | OUT VOID **Mapping\r | |
1328 | )\r | |
1329 | {\r | |
1436aea4 MK |
1330 | EFI_STATUS Status;\r |
1331 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1332 | EFI_PHYSICAL_ADDRESS PhysicalAddress;\r | |
1333 | MAP_INFO *MapInfo;\r | |
4a50cf4e | 1334 | \r |
1436aea4 MK |
1335 | if ((HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) ||\r |
1336 | (Mapping == NULL))\r | |
1337 | {\r | |
4a50cf4e RN |
1338 | return EFI_INVALID_PARAMETER;\r |
1339 | }\r | |
1340 | \r | |
1341 | //\r | |
1342 | // Make sure that Operation is valid\r | |
1343 | //\r | |
1436aea4 | 1344 | if ((UINT32)Operation >= EfiPciOperationMaximum) {\r |
4a50cf4e RN |
1345 | return EFI_INVALID_PARAMETER;\r |
1346 | }\r | |
1347 | \r | |
1348 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1349 | \r | |
69b40465 | 1350 | if (mIoMmu != NULL) {\r |
c15da8eb JY |
1351 | if (!RootBridge->DmaAbove4G) {\r |
1352 | //\r | |
1353 | // Clear 64bit support\r | |
1354 | //\r | |
1355 | if (Operation > EfiPciOperationBusMasterCommonBuffer) {\r | |
1436aea4 | 1356 | Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation - EfiPciOperationBusMasterRead64);\r |
c15da8eb JY |
1357 | }\r |
1358 | }\r | |
1436aea4 | 1359 | \r |
69b40465 RN |
1360 | Status = mIoMmu->Map (\r |
1361 | mIoMmu,\r | |
1436aea4 | 1362 | (EDKII_IOMMU_OPERATION)Operation,\r |
69b40465 RN |
1363 | HostAddress,\r |
1364 | NumberOfBytes,\r | |
1365 | DeviceAddress,\r | |
1366 | Mapping\r | |
1367 | );\r | |
c15da8eb JY |
1368 | return Status;\r |
1369 | }\r | |
1370 | \r | |
1436aea4 | 1371 | PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;\r |
e58a71d9 | 1372 | if ((!RootBridge->DmaAbove4G ||\r |
1436aea4 MK |
1373 | ((Operation != EfiPciOperationBusMasterRead64) &&\r |
1374 | (Operation != EfiPciOperationBusMasterWrite64) &&\r | |
1375 | (Operation != EfiPciOperationBusMasterCommonBuffer64))) &&\r | |
1376 | ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB))\r | |
1377 | {\r | |
4a50cf4e | 1378 | //\r |
e58a71d9 AB |
1379 | // If the root bridge or the device cannot handle performing DMA above\r |
1380 | // 4GB but any part of the DMA transfer being mapped is above 4GB, then\r | |
4a50cf4e RN |
1381 | // map the DMA transfer to a buffer below 4GB.\r |
1382 | //\r | |
1383 | \r | |
1436aea4 MK |
1384 | if ((Operation == EfiPciOperationBusMasterCommonBuffer) ||\r |
1385 | (Operation == EfiPciOperationBusMasterCommonBuffer64))\r | |
1386 | {\r | |
4a50cf4e RN |
1387 | //\r |
1388 | // Common Buffer operations can not be remapped. If the common buffer\r | |
1389 | // if above 4GB, then it is not possible to generate a mapping, so return\r | |
1390 | // an error.\r | |
1391 | //\r | |
1392 | return EFI_UNSUPPORTED;\r | |
1393 | }\r | |
1394 | \r | |
1395 | //\r | |
1396 | // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r | |
1397 | // called later.\r | |
1398 | //\r | |
1399 | MapInfo = AllocatePool (sizeof (MAP_INFO));\r | |
1400 | if (MapInfo == NULL) {\r | |
1401 | *NumberOfBytes = 0;\r | |
1402 | return EFI_OUT_OF_RESOURCES;\r | |
1403 | }\r | |
1404 | \r | |
1405 | //\r | |
1406 | // Initialize the MAP_INFO structure\r | |
1407 | //\r | |
1408 | MapInfo->Signature = MAP_INFO_SIGNATURE;\r | |
1409 | MapInfo->Operation = Operation;\r | |
1410 | MapInfo->NumberOfBytes = *NumberOfBytes;\r | |
1411 | MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes);\r | |
1412 | MapInfo->HostAddress = PhysicalAddress;\r | |
1413 | MapInfo->MappedHostAddress = SIZE_4GB - 1;\r | |
1414 | \r | |
1415 | //\r | |
1416 | // Allocate a buffer below 4GB to map the transfer to.\r | |
1417 | //\r | |
1418 | Status = gBS->AllocatePages (\r | |
1419 | AllocateMaxAddress,\r | |
1420 | EfiBootServicesData,\r | |
1421 | MapInfo->NumberOfPages,\r | |
1422 | &MapInfo->MappedHostAddress\r | |
1423 | );\r | |
1424 | if (EFI_ERROR (Status)) {\r | |
1425 | FreePool (MapInfo);\r | |
1426 | *NumberOfBytes = 0;\r | |
1427 | return Status;\r | |
1428 | }\r | |
1429 | \r | |
1430 | //\r | |
1431 | // If this is a read operation from the Bus Master's point of view,\r | |
1432 | // then copy the contents of the real buffer into the mapped buffer\r | |
1433 | // so the Bus Master can read the contents of the real buffer.\r | |
1434 | //\r | |
1436aea4 MK |
1435 | if ((Operation == EfiPciOperationBusMasterRead) ||\r |
1436 | (Operation == EfiPciOperationBusMasterRead64))\r | |
1437 | {\r | |
4a50cf4e | 1438 | CopyMem (\r |
1436aea4 MK |
1439 | (VOID *)(UINTN)MapInfo->MappedHostAddress,\r |
1440 | (VOID *)(UINTN)MapInfo->HostAddress,\r | |
4a50cf4e RN |
1441 | MapInfo->NumberOfBytes\r |
1442 | );\r | |
1443 | }\r | |
1444 | \r | |
1445 | InsertTailList (&RootBridge->Maps, &MapInfo->Link);\r | |
1446 | \r | |
1447 | //\r | |
1448 | // The DeviceAddress is the address of the maped buffer below 4GB\r | |
1449 | //\r | |
1450 | *DeviceAddress = MapInfo->MappedHostAddress;\r | |
1451 | //\r | |
1452 | // Return a pointer to the MAP_INFO structure in Mapping\r | |
1453 | //\r | |
1436aea4 | 1454 | *Mapping = MapInfo;\r |
4a50cf4e RN |
1455 | } else {\r |
1456 | //\r | |
1457 | // If the root bridge CAN handle performing DMA above 4GB or\r | |
1458 | // the transfer is below 4GB, so the DeviceAddress is simply the\r | |
1459 | // HostAddress\r | |
1460 | //\r | |
1461 | *DeviceAddress = PhysicalAddress;\r | |
1462 | *Mapping = NO_MAPPING;\r | |
1463 | }\r | |
1464 | \r | |
1465 | return EFI_SUCCESS;\r | |
1466 | }\r | |
1467 | \r | |
1468 | /**\r | |
1469 | Completes the Map() operation and releases any corresponding resources.\r | |
1470 | \r | |
1471 | The Unmap() function completes the Map() operation and releases any\r | |
1472 | corresponding resources.\r | |
1473 | If the operation was an EfiPciOperationBusMasterWrite or\r | |
1474 | EfiPciOperationBusMasterWrite64, the data is committed to the target system\r | |
1475 | memory.\r | |
1476 | Any resources used for the mapping are freed.\r | |
1477 | \r | |
1478 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1479 | @param[in] Mapping The mapping value returned from Map().\r | |
1480 | \r | |
1481 | @retval EFI_SUCCESS The range was unmapped.\r | |
1482 | @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r | |
1483 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r | |
1484 | **/\r | |
1485 | EFI_STATUS\r | |
1486 | EFIAPI\r | |
1487 | RootBridgeIoUnmap (\r | |
1488 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1489 | IN VOID *Mapping\r | |
1490 | )\r | |
1491 | {\r | |
1436aea4 MK |
1492 | MAP_INFO *MapInfo;\r |
1493 | LIST_ENTRY *Link;\r | |
1494 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
c15da8eb JY |
1495 | EFI_STATUS Status;\r |
1496 | \r | |
69b40465 RN |
1497 | if (mIoMmu != NULL) {\r |
1498 | Status = mIoMmu->Unmap (\r | |
1499 | mIoMmu,\r | |
1500 | Mapping\r | |
1501 | );\r | |
c15da8eb JY |
1502 | return Status;\r |
1503 | }\r | |
4a50cf4e RN |
1504 | \r |
1505 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
c15da8eb | 1506 | \r |
4a50cf4e RN |
1507 | //\r |
1508 | // See if the Map() operation associated with this Unmap() required a mapping\r | |
1509 | // buffer. If a mapping buffer was not required, then this function simply\r | |
1510 | // returns EFI_SUCCESS.\r | |
1511 | //\r | |
1512 | if (Mapping == NO_MAPPING) {\r | |
1513 | return EFI_SUCCESS;\r | |
1514 | }\r | |
1515 | \r | |
1516 | MapInfo = NO_MAPPING;\r | |
1517 | for (Link = GetFirstNode (&RootBridge->Maps)\r | |
1518 | ; !IsNull (&RootBridge->Maps, Link)\r | |
1519 | ; Link = GetNextNode (&RootBridge->Maps, Link)\r | |
1436aea4 MK |
1520 | )\r |
1521 | {\r | |
4a50cf4e RN |
1522 | MapInfo = MAP_INFO_FROM_LINK (Link);\r |
1523 | if (MapInfo == Mapping) {\r | |
1524 | break;\r | |
1525 | }\r | |
1526 | }\r | |
1436aea4 | 1527 | \r |
4a50cf4e RN |
1528 | //\r |
1529 | // Mapping is not a valid value returned by Map()\r | |
1530 | //\r | |
1531 | if (MapInfo != Mapping) {\r | |
1532 | return EFI_INVALID_PARAMETER;\r | |
1533 | }\r | |
1436aea4 | 1534 | \r |
4a50cf4e RN |
1535 | RemoveEntryList (&MapInfo->Link);\r |
1536 | \r | |
1537 | //\r | |
1538 | // If this is a write operation from the Bus Master's point of view,\r | |
1539 | // then copy the contents of the mapped buffer into the real buffer\r | |
1540 | // so the processor can read the contents of the real buffer.\r | |
1541 | //\r | |
1436aea4 MK |
1542 | if ((MapInfo->Operation == EfiPciOperationBusMasterWrite) ||\r |
1543 | (MapInfo->Operation == EfiPciOperationBusMasterWrite64))\r | |
1544 | {\r | |
4a50cf4e | 1545 | CopyMem (\r |
1436aea4 MK |
1546 | (VOID *)(UINTN)MapInfo->HostAddress,\r |
1547 | (VOID *)(UINTN)MapInfo->MappedHostAddress,\r | |
4a50cf4e RN |
1548 | MapInfo->NumberOfBytes\r |
1549 | );\r | |
1550 | }\r | |
1551 | \r | |
1552 | //\r | |
1553 | // Free the mapped buffer and the MAP_INFO structure.\r | |
1554 | //\r | |
1555 | gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r | |
1556 | FreePool (Mapping);\r | |
1557 | return EFI_SUCCESS;\r | |
1558 | }\r | |
1559 | \r | |
1560 | /**\r | |
1561 | Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer\r | |
1562 | or EfiPciOperationBusMasterCommonBuffer64 mapping.\r | |
1563 | \r | |
1564 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1565 | @param Type This parameter is not used and must be ignored.\r | |
1566 | @param MemoryType The type of memory to allocate, EfiBootServicesData or\r | |
1567 | EfiRuntimeServicesData.\r | |
1568 | @param Pages The number of pages to allocate.\r | |
1569 | @param HostAddress A pointer to store the base system memory address of the\r | |
1570 | allocated range.\r | |
1571 | @param Attributes The requested bit mask of attributes for the allocated\r | |
1572 | range. Only the attributes\r | |
1573 | EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,\r | |
1574 | EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and\r | |
1575 | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this\r | |
1576 | function.\r | |
1577 | \r | |
1578 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
1579 | @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r | |
1580 | @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r | |
1581 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal\r | |
1582 | attribute bits are MEMORY_WRITE_COMBINE,\r | |
1583 | MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r | |
1584 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
1585 | **/\r | |
1586 | EFI_STATUS\r | |
1587 | EFIAPI\r | |
1588 | RootBridgeIoAllocateBuffer (\r | |
1589 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1590 | IN EFI_ALLOCATE_TYPE Type,\r | |
1591 | IN EFI_MEMORY_TYPE MemoryType,\r | |
1592 | IN UINTN Pages,\r | |
1593 | OUT VOID **HostAddress,\r | |
1594 | IN UINT64 Attributes\r | |
1595 | )\r | |
1596 | {\r | |
1597 | EFI_STATUS Status;\r | |
1598 | EFI_PHYSICAL_ADDRESS PhysicalAddress;\r | |
1599 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1600 | EFI_ALLOCATE_TYPE AllocateType;\r | |
1601 | \r | |
1602 | //\r | |
1603 | // Validate Attributes\r | |
1604 | //\r | |
1605 | if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r | |
1606 | return EFI_UNSUPPORTED;\r | |
1607 | }\r | |
1608 | \r | |
1609 | //\r | |
1610 | // Check for invalid inputs\r | |
1611 | //\r | |
1612 | if (HostAddress == NULL) {\r | |
1613 | return EFI_INVALID_PARAMETER;\r | |
1614 | }\r | |
1615 | \r | |
1616 | //\r | |
1617 | // The only valid memory types are EfiBootServicesData and\r | |
1618 | // EfiRuntimeServicesData\r | |
1619 | //\r | |
1436aea4 MK |
1620 | if ((MemoryType != EfiBootServicesData) &&\r |
1621 | (MemoryType != EfiRuntimeServicesData))\r | |
1622 | {\r | |
4a50cf4e RN |
1623 | return EFI_INVALID_PARAMETER;\r |
1624 | }\r | |
1625 | \r | |
1626 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1627 | \r | |
69b40465 | 1628 | if (mIoMmu != NULL) {\r |
c15da8eb JY |
1629 | if (!RootBridge->DmaAbove4G) {\r |
1630 | //\r | |
1631 | // Clear DUAL_ADDRESS_CYCLE\r | |
1632 | //\r | |
1436aea4 | 1633 | Attributes &= ~((UINT64)EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r |
c15da8eb | 1634 | }\r |
1436aea4 | 1635 | \r |
69b40465 RN |
1636 | Status = mIoMmu->AllocateBuffer (\r |
1637 | mIoMmu,\r | |
1638 | Type,\r | |
1639 | MemoryType,\r | |
1640 | Pages,\r | |
1641 | HostAddress,\r | |
1642 | Attributes\r | |
1643 | );\r | |
c15da8eb JY |
1644 | return Status;\r |
1645 | }\r | |
1646 | \r | |
4a50cf4e | 1647 | AllocateType = AllocateAnyPages;\r |
e58a71d9 | 1648 | if (!RootBridge->DmaAbove4G ||\r |
1436aea4 MK |
1649 | ((Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0))\r |
1650 | {\r | |
4a50cf4e RN |
1651 | //\r |
1652 | // Limit allocations to memory below 4GB\r | |
1653 | //\r | |
1654 | AllocateType = AllocateMaxAddress;\r | |
1436aea4 | 1655 | PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(SIZE_4GB - 1);\r |
4a50cf4e | 1656 | }\r |
1436aea4 | 1657 | \r |
4a50cf4e RN |
1658 | Status = gBS->AllocatePages (\r |
1659 | AllocateType,\r | |
1660 | MemoryType,\r | |
1661 | Pages,\r | |
1662 | &PhysicalAddress\r | |
1663 | );\r | |
1664 | if (!EFI_ERROR (Status)) {\r | |
1436aea4 | 1665 | *HostAddress = (VOID *)(UINTN)PhysicalAddress;\r |
4a50cf4e RN |
1666 | }\r |
1667 | \r | |
1668 | return Status;\r | |
1669 | }\r | |
1670 | \r | |
1671 | /**\r | |
1672 | Frees memory that was allocated with AllocateBuffer().\r | |
1673 | \r | |
1674 | The FreeBuffer() function frees memory that was allocated with\r | |
1675 | AllocateBuffer().\r | |
1676 | \r | |
1677 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1678 | @param Pages The number of pages to free.\r | |
1679 | @param HostAddress The base system memory address of the allocated range.\r | |
1680 | \r | |
1681 | @retval EFI_SUCCESS The requested memory pages were freed.\r | |
1682 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and\r | |
1683 | Pages was not allocated with AllocateBuffer().\r | |
1684 | **/\r | |
1685 | EFI_STATUS\r | |
1686 | EFIAPI\r | |
1687 | RootBridgeIoFreeBuffer (\r | |
1688 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1689 | IN UINTN Pages,\r | |
1690 | OUT VOID *HostAddress\r | |
1691 | )\r | |
1692 | {\r | |
1436aea4 | 1693 | EFI_STATUS Status;\r |
c15da8eb | 1694 | \r |
69b40465 RN |
1695 | if (mIoMmu != NULL) {\r |
1696 | Status = mIoMmu->FreeBuffer (\r | |
1697 | mIoMmu,\r | |
1698 | Pages,\r | |
1699 | HostAddress\r | |
1700 | );\r | |
c15da8eb JY |
1701 | return Status;\r |
1702 | }\r | |
1703 | \r | |
1436aea4 | 1704 | return gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, Pages);\r |
4a50cf4e RN |
1705 | }\r |
1706 | \r | |
1707 | /**\r | |
1708 | Flushes all PCI posted write transactions from a PCI host bridge to system\r | |
1709 | memory.\r | |
1710 | \r | |
1711 | The Flush() function flushes any PCI posted write transactions from a PCI\r | |
1712 | host bridge to system memory. Posted write transactions are generated by PCI\r | |
1713 | bus masters when they perform write transactions to target addresses in\r | |
1714 | system memory.\r | |
1715 | This function does not flush posted write transactions from any PCI bridges.\r | |
1716 | A PCI controller specific action must be taken to guarantee that the posted\r | |
1717 | write transactions have been flushed from the PCI controller and from all the\r | |
1718 | PCI bridges into the PCI host bridge. This is typically done with a PCI read\r | |
1719 | transaction from the PCI controller prior to calling Flush().\r | |
1720 | \r | |
1721 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1722 | \r | |
1723 | @retval EFI_SUCCESS The PCI posted write transactions were flushed\r | |
1724 | from the PCI host bridge to system memory.\r | |
1725 | @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed\r | |
1726 | from the PCI host bridge due to a hardware error.\r | |
1727 | **/\r | |
1728 | EFI_STATUS\r | |
1729 | EFIAPI\r | |
1730 | RootBridgeIoFlush (\r | |
1436aea4 | 1731 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r |
4a50cf4e RN |
1732 | )\r |
1733 | {\r | |
1734 | return EFI_SUCCESS;\r | |
1735 | }\r | |
1736 | \r | |
1737 | /**\r | |
1738 | Gets the attributes that a PCI root bridge supports setting with\r | |
1739 | SetAttributes(), and the attributes that a PCI root bridge is currently\r | |
1740 | using.\r | |
1741 | \r | |
1742 | The GetAttributes() function returns the mask of attributes that this PCI\r | |
1743 | root bridge supports and the mask of attributes that the PCI root bridge is\r | |
1744 | currently using.\r | |
1745 | \r | |
1746 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1747 | @param Supported A pointer to the mask of attributes that this PCI root\r | |
1748 | bridge supports setting with SetAttributes().\r | |
1749 | @param Attributes A pointer to the mask of attributes that this PCI root\r | |
1750 | bridge is currently using.\r | |
1751 | \r | |
1752 | @retval EFI_SUCCESS If Supports is not NULL, then the attributes\r | |
1753 | that the PCI root bridge supports is returned\r | |
1754 | in Supports. If Attributes is not NULL, then\r | |
1755 | the attributes that the PCI root bridge is\r | |
1756 | currently using is returned in Attributes.\r | |
1757 | @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r | |
1758 | **/\r | |
1759 | EFI_STATUS\r | |
1760 | EFIAPI\r | |
1761 | RootBridgeIoGetAttributes (\r | |
1762 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1763 | OUT UINT64 *Supported,\r | |
1764 | OUT UINT64 *Attributes\r | |
1765 | )\r | |
1766 | {\r | |
1436aea4 | 1767 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r |
4a50cf4e | 1768 | \r |
1436aea4 | 1769 | if ((Attributes == NULL) && (Supported == NULL)) {\r |
4a50cf4e RN |
1770 | return EFI_INVALID_PARAMETER;\r |
1771 | }\r | |
1772 | \r | |
1773 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1774 | //\r | |
1775 | // Set the return value for Supported and Attributes\r | |
1776 | //\r | |
1777 | if (Supported != NULL) {\r | |
1436aea4 | 1778 | *Supported = RootBridge->Supports;\r |
4a50cf4e RN |
1779 | }\r |
1780 | \r | |
1781 | if (Attributes != NULL) {\r | |
1782 | *Attributes = RootBridge->Attributes;\r | |
1783 | }\r | |
1784 | \r | |
1785 | return EFI_SUCCESS;\r | |
1786 | }\r | |
1787 | \r | |
1788 | /**\r | |
1789 | Sets attributes for a resource range on a PCI root bridge.\r | |
1790 | \r | |
1791 | The SetAttributes() function sets the attributes specified in Attributes for\r | |
1792 | the PCI root bridge on the resource range specified by ResourceBase and\r | |
1793 | ResourceLength. Since the granularity of setting these attributes may vary\r | |
1794 | from resource type to resource type, and from platform to platform, the\r | |
1795 | actual resource range and the one passed in by the caller may differ. As a\r | |
1796 | result, this function may set the attributes specified by Attributes on a\r | |
1797 | larger resource range than the caller requested. The actual range is returned\r | |
1798 | in ResourceBase and ResourceLength. The caller is responsible for verifying\r | |
1799 | that the actual range for which the attributes were set is acceptable.\r | |
1800 | \r | |
1801 | @param This A pointer to the\r | |
1802 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1803 | @param Attributes The mask of attributes to set. If the\r | |
1804 | attribute bit MEMORY_WRITE_COMBINE,\r | |
1805 | MEMORY_CACHED, or MEMORY_DISABLE is set,\r | |
1806 | then the resource range is specified by\r | |
1807 | ResourceBase and ResourceLength. If\r | |
1808 | MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r | |
1809 | MEMORY_DISABLE are not set, then\r | |
1810 | ResourceBase and ResourceLength are ignored,\r | |
1811 | and may be NULL.\r | |
1812 | @param ResourceBase A pointer to the base address of the\r | |
1813 | resource range to be modified by the\r | |
1814 | attributes specified by Attributes.\r | |
1815 | @param ResourceLength A pointer to the length of the resource\r | |
1816 | range to be modified by the attributes\r | |
1817 | specified by Attributes.\r | |
1818 | \r | |
1819 | @retval EFI_SUCCESS The current configuration of this PCI root bridge\r | |
1820 | was returned in Resources.\r | |
1821 | @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r | |
1822 | could not be retrieved.\r | |
1823 | **/\r | |
1824 | EFI_STATUS\r | |
1825 | EFIAPI\r | |
1826 | RootBridgeIoSetAttributes (\r | |
1827 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1828 | IN UINT64 Attributes,\r | |
1829 | IN OUT UINT64 *ResourceBase,\r | |
1830 | IN OUT UINT64 *ResourceLength\r | |
1831 | )\r | |
1832 | {\r | |
1436aea4 | 1833 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r |
4a50cf4e RN |
1834 | \r |
1835 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1836 | \r | |
1837 | if ((Attributes & (~RootBridge->Supports)) != 0) {\r | |
1838 | return EFI_UNSUPPORTED;\r | |
1839 | }\r | |
1840 | \r | |
1841 | RootBridge->Attributes = Attributes;\r | |
1842 | return EFI_SUCCESS;\r | |
1843 | }\r | |
1844 | \r | |
1845 | /**\r | |
1846 | Retrieves the current resource settings of this PCI root bridge in the form\r | |
6fbaed1f | 1847 | of a set of ACPI resource descriptors.\r |
4a50cf4e RN |
1848 | \r |
1849 | There are only two resource descriptor types from the ACPI Specification that\r | |
1850 | may be used to describe the current resources allocated to a PCI root bridge.\r | |
6fbaed1f DB |
1851 | These are the QWORD Address Space Descriptor, and the End Tag. The QWORD\r |
1852 | Address Space Descriptor can describe memory, I/O, and bus number ranges for\r | |
1853 | dynamic or fixed resources. The configuration of a PCI root bridge is described\r | |
1854 | with one or more QWORD Address Space Descriptors followed by an End Tag.\r | |
4a50cf4e RN |
1855 | \r |
1856 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
6fbaed1f | 1857 | @param[out] Resources A pointer to the resource descriptors that\r |
4a50cf4e | 1858 | describe the current configuration of this PCI root\r |
6fbaed1f | 1859 | bridge. The storage for the resource\r |
4a50cf4e RN |
1860 | descriptors is allocated by this function. The\r |
1861 | caller must treat the return buffer as read-only\r | |
1862 | data, and the buffer must not be freed by the\r | |
1863 | caller.\r | |
1864 | \r | |
1865 | @retval EFI_SUCCESS The current configuration of this PCI root bridge\r | |
1866 | was returned in Resources.\r | |
1867 | @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r | |
1868 | could not be retrieved.\r | |
1869 | **/\r | |
1870 | EFI_STATUS\r | |
1871 | EFIAPI\r | |
1872 | RootBridgeIoConfiguration (\r | |
1436aea4 MK |
1873 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r |
1874 | OUT VOID **Resources\r | |
4a50cf4e RN |
1875 | )\r |
1876 | {\r | |
1436aea4 MK |
1877 | PCI_RESOURCE_TYPE Index;\r |
1878 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1879 | PCI_RES_NODE *ResAllocNode;\r | |
1880 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r | |
1881 | EFI_ACPI_END_TAG_DESCRIPTOR *End;\r | |
4a50cf4e RN |
1882 | \r |
1883 | //\r | |
1884 | // Get this instance of the Root Bridge.\r | |
1885 | //\r | |
1886 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1887 | ZeroMem (\r | |
1888 | RootBridge->ConfigBuffer,\r | |
1889 | TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r | |
1890 | );\r | |
1891 | Descriptor = RootBridge->ConfigBuffer;\r | |
1892 | for (Index = TypeIo; Index < TypeMax; Index++) {\r | |
4a50cf4e RN |
1893 | ResAllocNode = &RootBridge->ResAllocNode[Index];\r |
1894 | \r | |
1895 | if (ResAllocNode->Status != ResAllocated) {\r | |
1896 | continue;\r | |
1897 | }\r | |
1898 | \r | |
1899 | Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r | |
1900 | Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r | |
74d0a339 HG |
1901 | // According to UEFI 2.7, RootBridgeIo->Configuration should return address\r |
1902 | // range in CPU view (host address), and ResAllocNode->Base is already a CPU\r | |
1903 | // view address (host address).\r | |
1436aea4 MK |
1904 | Descriptor->AddrRangeMin = ResAllocNode->Base;\r |
1905 | Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r | |
1906 | Descriptor->AddrLen = ResAllocNode->Length;\r | |
74d0a339 | 1907 | Descriptor->AddrTranslationOffset = GetTranslationByResourceType (\r |
1436aea4 MK |
1908 | RootBridge,\r |
1909 | ResAllocNode->Type\r | |
1910 | );\r | |
74d0a339 | 1911 | \r |
4a50cf4e | 1912 | switch (ResAllocNode->Type) {\r |
1436aea4 MK |
1913 | case TypeIo:\r |
1914 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r | |
1915 | break;\r | |
1916 | \r | |
1917 | case TypePMem32:\r | |
1918 | Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r | |
1919 | case TypeMem32:\r | |
1920 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1921 | Descriptor->AddrSpaceGranularity = 32;\r | |
1922 | break;\r | |
1923 | \r | |
1924 | case TypePMem64:\r | |
1925 | Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r | |
1926 | case TypeMem64:\r | |
1927 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1928 | Descriptor->AddrSpaceGranularity = 64;\r | |
1929 | break;\r | |
1930 | \r | |
1931 | case TypeBus:\r | |
1932 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r | |
1933 | break;\r | |
1934 | \r | |
1935 | default:\r | |
1936 | break;\r | |
4a50cf4e RN |
1937 | }\r |
1938 | \r | |
1939 | Descriptor++;\r | |
1940 | }\r | |
1436aea4 | 1941 | \r |
4a50cf4e RN |
1942 | //\r |
1943 | // Terminate the entries.\r | |
1944 | //\r | |
1436aea4 | 1945 | End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;\r |
4a50cf4e RN |
1946 | End->Desc = ACPI_END_TAG_DESCRIPTOR;\r |
1947 | End->Checksum = 0x0;\r | |
1948 | \r | |
1949 | *Resources = RootBridge->ConfigBuffer;\r | |
1950 | return EFI_SUCCESS;\r | |
1951 | }\r |