[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciHostBridgeDxe / PciRootBridgeIo.c

/** @file\r
\r
  PCI Root Bridge Io Protocol code.\r
\r
Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PciHostBridge.h"\r
#include "PciRootBridge.h"\r
#include "PciHostResource.h"\r
\r
extern EDKII_IOMMU_PROTOCOL        *mIoMmuProtocol;\r
\r
#define NO_MAPPING  (VOID *) (UINTN) -1\r
\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
UINT8 mInStride[] = {\r
  1, // EfiPciWidthUint8\r
  2, // EfiPciWidthUint16\r
  4, // EfiPciWidthUint32\r
  8, // EfiPciWidthUint64\r
  0, // EfiPciWidthFifoUint8\r
  0, // EfiPciWidthFifoUint16\r
  0, // EfiPciWidthFifoUint32\r
  0, // EfiPciWidthFifoUint64\r
  1, // EfiPciWidthFillUint8\r
  2, // EfiPciWidthFillUint16\r
  4, // EfiPciWidthFillUint32\r
  8  // EfiPciWidthFillUint64\r
};\r
\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
UINT8 mOutStride[] = {\r
  1, // EfiPciWidthUint8\r
  2, // EfiPciWidthUint16\r
  4, // EfiPciWidthUint32\r
  8, // EfiPciWidthUint64\r
  1, // EfiPciWidthFifoUint8\r
  2, // EfiPciWidthFifoUint16\r
  4, // EfiPciWidthFifoUint32\r
  8, // EfiPciWidthFifoUint64\r
  0, // EfiPciWidthFillUint8\r
  0, // EfiPciWidthFillUint16\r
  0, // EfiPciWidthFillUint32\r
  0  // EfiPciWidthFillUint64\r
};\r
\r
/**\r
  Construct the Pci Root Bridge instance.\r
\r
  @param Bridge            The root bridge instance.\r
\r
  @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created\r
          or NULL if creation fails.\r
**/\r
PCI_ROOT_BRIDGE_INSTANCE *\r
CreateRootBridge (\r
  IN PCI_ROOT_BRIDGE       *Bridge\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
  PCI_RESOURCE_TYPE        Index;\r
  CHAR16                   *DevicePathStr;\r
  PCI_ROOT_BRIDGE_APERTURE *Aperture;\r
\r
  DevicePathStr = NULL;\r
\r
  DEBUG ((EFI_D_INFO, "RootBridge: "));\r
  DEBUG ((EFI_D_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));\r
  DEBUG ((EFI_D_INFO, "  Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));\r
  DEBUG ((EFI_D_INFO, "    DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));\r
  DEBUG ((EFI_D_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));\r
  DEBUG ((EFI_D_INFO, "     AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,\r
          (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",\r
          (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""\r
          ));\r
  DEBUG ((\r
    EFI_D_INFO, "           Bus: %lx - %lx Translation=%lx\n",\r
    Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation\r
    ));\r
  //\r
  // Translation for bus is not supported.\r
  //\r
  ASSERT (Bridge->Bus.Translation == 0);\r
  if (Bridge->Bus.Translation != 0) {\r
    return NULL;\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO, "            Io: %lx - %lx Translation=%lx\n",\r
    Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation\r
    ));\r
  DEBUG ((\r
    DEBUG_INFO, "           Mem: %lx - %lx Translation=%lx\n",\r
    Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation\r
    ));\r
  DEBUG ((\r
    DEBUG_INFO, "    MemAbove4G: %lx - %lx Translation=%lx\n",\r
    Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation\r
    ));\r
  DEBUG ((\r
    DEBUG_INFO, "          PMem: %lx - %lx Translation=%lx\n",\r
    Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation\r
    ));\r
  DEBUG ((\r
    DEBUG_INFO, "   PMemAbove4G: %lx - %lx Translation=%lx\n",\r
    Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation\r
    ));\r
\r
  //\r
  // Make sure Mem and MemAbove4G apertures are valid\r
  //\r
  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {\r
    ASSERT (Bridge->Mem.Limit < SIZE_4GB);\r
    if (Bridge->Mem.Limit >= SIZE_4GB) {\r
      return NULL;\r
    }\r
  }\r
  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {\r
    ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);\r
    if (Bridge->MemAbove4G.Base < SIZE_4GB) {\r
      return NULL;\r
    }\r
  }\r
  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {\r
    ASSERT (Bridge->PMem.Limit < SIZE_4GB);\r
    if (Bridge->PMem.Limit >= SIZE_4GB) {\r
      return NULL;\r
    }\r
  }\r
  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {\r
    ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);\r
    if (Bridge->PMemAbove4G.Base < SIZE_4GB) {\r
      return NULL;\r
    }\r
  }\r
\r
  //\r
  // Ignore AllocationAttributes when resources were already assigned.\r
  //\r
  if (!Bridge->ResourceAssigned) {\r
    if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
      //\r
      // If this bit is set, then the PCI Root Bridge does not\r
      // support separate windows for Non-prefetchable and Prefetchable\r
      // memory.\r
      //\r
      ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r
      ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
      if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r
          (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
          ) {\r
        return NULL;\r
      }\r
    }\r
\r
    if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {\r
      //\r
      // If this bit is not set, then the PCI Root Bridge does not support\r
      // 64 bit memory windows.\r
      //\r
      ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r
      ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
      if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r
          (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
          ) {\r
        return NULL;\r
      }\r
    }\r
  }\r
\r
  RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));\r
  ASSERT (RootBridge != NULL);\r
\r
  RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r
  RootBridge->Supports = Bridge->Supports;\r
  RootBridge->Attributes = Bridge->Attributes;\r
  RootBridge->DmaAbove4G = Bridge->DmaAbove4G;\r
  RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;\r
  RootBridge->AllocationAttributes = Bridge->AllocationAttributes;\r
  RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);\r
  RootBridge->DevicePathStr = DevicePathStr;\r
  RootBridge->ConfigBuffer = AllocatePool (\r
    TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
    );\r
  ASSERT (RootBridge->ConfigBuffer != NULL);\r
  InitializeListHead (&RootBridge->Maps);\r
\r
  CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
  CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
  CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
  CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
  CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
  CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
\r
  for (Index = TypeIo; Index < TypeMax; Index++) {\r
    switch (Index) {\r
    case TypeBus:\r
      Aperture = &RootBridge->Bus;\r
      break;\r
    case TypeIo:\r
      Aperture = &RootBridge->Io;\r
      break;\r
    case TypeMem32:\r
      Aperture = &RootBridge->Mem;\r
      break;\r
    case TypeMem64:\r
      Aperture = &RootBridge->MemAbove4G;\r
      break;\r
    case TypePMem32:\r
      Aperture = &RootBridge->PMem;\r
      break;\r
    case TypePMem64:\r
      Aperture = &RootBridge->PMemAbove4G;\r
      break;\r
    default:\r
      ASSERT (FALSE);\r
      Aperture = NULL;\r
      break;\r
    }\r
    RootBridge->ResAllocNode[Index].Type     = Index;\r
    if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {\r
      //\r
      // Base in ResAllocNode is a host address, while Base in Aperture is a\r
      // device address.\r
      //\r
      RootBridge->ResAllocNode[Index].Base   = TO_HOST_ADDRESS (Aperture->Base,\r
        Aperture->Translation);\r
      RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;\r
      RootBridge->ResAllocNode[Index].Status = ResAllocated;\r
    } else {\r
      RootBridge->ResAllocNode[Index].Base   = 0;\r
      RootBridge->ResAllocNode[Index].Length = 0;\r
      RootBridge->ResAllocNode[Index].Status = ResNone;\r
    }\r
  }\r
\r
  RootBridge->RootBridgeIo.SegmentNumber  = Bridge->Segment;\r
  RootBridge->RootBridgeIo.PollMem        = RootBridgeIoPollMem;\r
  RootBridge->RootBridgeIo.PollIo         = RootBridgeIoPollIo;\r
  RootBridge->RootBridgeIo.Mem.Read       = RootBridgeIoMemRead;\r
  RootBridge->RootBridgeIo.Mem.Write      = RootBridgeIoMemWrite;\r
  RootBridge->RootBridgeIo.Io.Read        = RootBridgeIoIoRead;\r
  RootBridge->RootBridgeIo.Io.Write       = RootBridgeIoIoWrite;\r
  RootBridge->RootBridgeIo.CopyMem        = RootBridgeIoCopyMem;\r
  RootBridge->RootBridgeIo.Pci.Read       = RootBridgeIoPciRead;\r
  RootBridge->RootBridgeIo.Pci.Write      = RootBridgeIoPciWrite;\r
  RootBridge->RootBridgeIo.Map            = RootBridgeIoMap;\r
  RootBridge->RootBridgeIo.Unmap          = RootBridgeIoUnmap;\r
  RootBridge->RootBridgeIo.AllocateBuffer = RootBridgeIoAllocateBuffer;\r
  RootBridge->RootBridgeIo.FreeBuffer     = RootBridgeIoFreeBuffer;\r
  RootBridge->RootBridgeIo.Flush          = RootBridgeIoFlush;\r
  RootBridge->RootBridgeIo.GetAttributes  = RootBridgeIoGetAttributes;\r
  RootBridge->RootBridgeIo.SetAttributes  = RootBridgeIoSetAttributes;\r
  RootBridge->RootBridgeIo.Configuration  = RootBridgeIoConfiguration;\r
\r
  return RootBridge;\r
}\r
\r
/**\r
  Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r
\r
  The I/O operations are carried out exactly as requested. The caller is\r
  responsible for satisfying any alignment and I/O width restrictions that a PI\r
  System on a platform might require. For example on some platforms, width\r
  requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other\r
  hand, will be handled by the driver.\r
\r
  @param[in] This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
\r
  @param[in] OperationType  I/O operation type: IO/MMIO/PCI.\r
\r
  @param[in] Width          Signifies the width of the I/O or Memory operation.\r
\r
  @param[in] Address        The base address of the I/O operation.\r
\r
  @param[in] Count          The number of I/O operations to perform. The number\r
                            of bytes moved is Width size * Count, starting at\r
                            Address.\r
\r
  @param[in] Buffer         For read operations, the destination buffer to\r
                            store the results. For write operations, the source\r
                            buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The parameters for this request pass the\r
                                 checks.\r
\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
**/\r
EFI_STATUS\r
RootBridgeIoCheckParameter (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN OPERATION_TYPE                         OperationType,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                                 Address,\r
  IN UINTN                                  Count,\r
  IN VOID                                   *Buffer\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;\r
  UINT64                                       Base;\r
  UINT64                                       Limit;\r
  UINT32                                       Size;\r
\r
  //\r
  // Check to see if Buffer is NULL\r
  //\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Check to see if Width is in the valid range\r
  //\r
  if ((UINT32) Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // For FIFO type, the target address won't increase during the access,\r
  // so treat Count as 1\r
  //\r
  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
    Count = 1;\r
  }\r
\r
  Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
  Size  = 1 << Width;\r
\r
  //\r
  // Check to see if Address is aligned\r
  //\r
  if ((Address & (Size - 1)) != 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
\r
  //\r
  // Check to see if any address associated with this transfer exceeds the\r
  // maximum allowed address.  The maximum address implied by the parameters\r
  // passed in is Address + Size * Count.  If the following condition is met,\r
  // then the transfer is not supported.\r
  //\r
  //    Address + Size * Count > Limit + 1\r
  //\r
  // Since Limit can be the maximum integer value supported by the CPU and\r
  // Count can also be the maximum integer value supported by the CPU, this\r
  // range check must be adjusted to avoid all oveflow conditions.\r
  //\r
  if (OperationType == IoOperation) {\r
    //\r
    // Allow Legacy IO access\r
    //\r
    if (Address + MultU64x32 (Count, Size) <= 0x1000) {\r
      if ((RootBridge->Attributes & (\r
           EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |\r
           EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
           EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0) {\r
        return EFI_SUCCESS;\r
      }\r
    }\r
    Base = RootBridge->Io.Base;\r
    Limit = RootBridge->Io.Limit;\r
  } else if (OperationType == MemOperation) {\r
    //\r
    // Allow Legacy MMIO access\r
    //\r
    if ((Address >= 0xA0000) && (Address + MultU64x32 (Count, Size)) <= 0xC0000) {\r
      if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {\r
        return EFI_SUCCESS;\r
      }\r
    }\r
    //\r
    // By comparing the Address against Limit we know which range to be used\r
    // for checking\r
    //\r
    if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit + 1) {\r
      Base = RootBridge->Mem.Base;\r
      Limit = RootBridge->Mem.Limit;\r
    } else {\r
      Base = RootBridge->MemAbove4G.Base;\r
      Limit = RootBridge->MemAbove4G.Limit;\r
    }\r
  } else {\r
    PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
    if (PciRbAddr->Bus < RootBridge->Bus.Base ||\r
        PciRbAddr->Bus > RootBridge->Bus.Limit) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    if (PciRbAddr->Device > PCI_MAX_DEVICE ||\r
        PciRbAddr->Function > PCI_MAX_FUNC) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    if (PciRbAddr->ExtendedRegister != 0) {\r
      Address = PciRbAddr->ExtendedRegister;\r
    } else {\r
      Address = PciRbAddr->Register;\r
    }\r
    Base = 0;\r
    Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;\r
  }\r
\r
  if (Address < Base) {\r
      return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Address + MultU64x32 (Count, Size) > Limit + 1) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Use address to match apertures of memory type and then get the corresponding\r
  translation.\r
\r
  @param RootBridge              The root bridge instance.\r
  @param Address                 The address used to match aperture.\r
  @param Translation             Pointer containing the output translation.\r
\r
  @return EFI_SUCCESS            Get translation successfully.\r
  @return EFI_INVALID_PARAMETER  No matched memory aperture; the input Address\r
                                 must be invalid.\r
**/\r
EFI_STATUS\r
RootBridgeIoGetMemTranslationByAddress (\r
  IN PCI_ROOT_BRIDGE_INSTANCE               *RootBridge,\r
  IN UINT64                                 Address,\r
  IN OUT UINT64                             *Translation\r
  )\r
{\r
  if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) {\r
    *Translation = RootBridge->Mem.Translation;\r
  } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) {\r
    *Translation = RootBridge->PMem.Translation;\r
  } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) {\r
    *Translation = RootBridge->MemAbove4G.Translation;\r
  } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) {\r
    *Translation = RootBridge->PMemAbove4G.Translation;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Polls an address in memory mapped I/O space until an exit condition is met,\r
  or a timeout occurs.\r
\r
  This function provides a standard way to poll a PCI memory location. A PCI\r
  memory read operation is performed at the PCI memory address specified by\r
  Address for the width specified by Width. The result of this PCI memory read\r
  operation is stored in Result. This PCI memory read operation is repeated\r
  until either a timeout of Delay 100 ns units has expired, or (Result & Mask)\r
  is equal to Value.\r
\r
  @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in]   Width     Signifies the width of the memory operations.\r
  @param[in]   Address   The base address of the memory operations. The caller\r
                         is responsible for aligning Address if required.\r
  @param[in]   Mask      Mask used for the polling criteria. Bytes above Width\r
                         in Mask are ignored. The bits in the bytes below Width\r
                         which are zero in Mask are ignored when polling the\r
                         memory address.\r
  @param[in]   Value     The comparison value used for the polling exit\r
                         criteria.\r
  @param[in]   Delay     The number of 100 ns units to poll. Note that timer\r
                         available may be of poorer granularity.\r
  @param[out]  Result    Pointer to the last value read from the memory\r
                         location.\r
\r
  @retval EFI_SUCCESS            The last data returned from the access matched\r
                                 the poll exit criteria.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid.\r
  @retval EFI_INVALID_PARAMETER  Result is NULL.\r
  @retval EFI_TIMEOUT            Delay expired before a match occurred.\r
  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a\r
                                 lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollMem (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT64      NumberOfTicks;\r
  UINT32      Remainder;\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((UINT32)Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // No matter what, always do a single poll.\r
  //\r
  Status = This->Mem.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
\r
  } else {\r
\r
    //\r
    // Determine the proper # of metronome ticks to wait for polling the\r
    // location.  The nuber of ticks is Roundup (Delay /\r
    // mMetronome->TickPeriod)+1\r
    // The "+1" to account for the possibility of the first tick being short\r
    // because we started in the middle of a tick.\r
    //\r
    // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
    // protocol definition is updated.\r
    //\r
    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,\r
                      &Remainder);\r
    if (Remainder != 0) {\r
      NumberOfTicks += 1;\r
    }\r
    NumberOfTicks += 1;\r
\r
    while (NumberOfTicks != 0) {\r
\r
      mMetronome->WaitForTick (mMetronome, 1);\r
\r
      Status = This->Mem.Read (This, Width, Address, 1, Result);\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
\r
      if ((*Result & Mask) == Value) {\r
        return EFI_SUCCESS;\r
      }\r
\r
      NumberOfTicks -= 1;\r
    }\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Reads from the I/O space of a PCI Root Bridge. Returns when either the\r
  polling exit criteria is satisfied or after a defined duration.\r
\r
  This function provides a standard way to poll a PCI I/O location. A PCI I/O\r
  read operation is performed at the PCI I/O address specified by Address for\r
  the width specified by Width.\r
  The result of this PCI I/O read operation is stored in Result. This PCI I/O\r
  read operation is repeated until either a timeout of Delay 100 ns units has\r
  expired, or (Result & Mask) is equal to Value.\r
\r
  @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in] Width     Signifies the width of the I/O operations.\r
  @param[in] Address   The base address of the I/O operations. The caller is\r
                       responsible for aligning Address if required.\r
  @param[in] Mask      Mask used for the polling criteria. Bytes above Width in\r
                       Mask are ignored. The bits in the bytes below Width\r
                       which are zero in Mask are ignored when polling the I/O\r
                       address.\r
  @param[in] Value     The comparison value used for the polling exit criteria.\r
  @param[in] Delay     The number of 100 ns units to poll. Note that timer\r
                       available may be of poorer granularity.\r
  @param[out] Result   Pointer to the last value read from the memory location.\r
\r
  @retval EFI_SUCCESS            The last data returned from the access matched\r
                                 the poll exit criteria.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid.\r
  @retval EFI_INVALID_PARAMETER  Result is NULL.\r
  @retval EFI_TIMEOUT            Delay expired before a match occurred.\r
  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a\r
                                 lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollIo (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT64      NumberOfTicks;\r
  UINT32      Remainder;\r
\r
  //\r
  // No matter what, always do a single poll.\r
  //\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((UINT32)Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = This->Io.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
\r
  } else {\r
\r
    //\r
    // Determine the proper # of metronome ticks to wait for polling the\r
    // location.  The number of ticks is Roundup (Delay /\r
    // mMetronome->TickPeriod)+1\r
    // The "+1" to account for the possibility of the first tick being short\r
    // because we started in the middle of a tick.\r
    //\r
    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,\r
                      &Remainder);\r
    if (Remainder != 0) {\r
      NumberOfTicks += 1;\r
    }\r
    NumberOfTicks += 1;\r
\r
    while (NumberOfTicks != 0) {\r
\r
      mMetronome->WaitForTick (mMetronome, 1);\r
\r
      Status = This->Io.Read (This, Width, Address, 1, Result);\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
\r
      if ((*Result & Mask) == Value) {\r
        return EFI_SUCCESS;\r
      }\r
\r
      NumberOfTicks -= 1;\r
    }\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Enables a PCI driver to access PCI controller registers in the PCI root\r
  bridge memory space.\r
\r
  The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r
  controller registers in the PCI root bridge memory space.\r
  The memory operations are carried out exactly as requested. The caller is\r
  responsible for satisfying any alignment and memory width restrictions that a\r
  PCI Root Bridge on a platform might require.\r
\r
  @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in]   Width     Signifies the width of the memory operation.\r
  @param[in]   Address   The base address of the memory operation. The caller\r
                         is responsible for aligning the Address if required.\r
  @param[in]   Count     The number of memory operations to perform. Bytes\r
                         moved is Width size * Count, starting at Address.\r
  @param[out]  Buffer    For read operations, the destination buffer to store\r
                         the results. For write operations, the source buffer\r
                         to write data from.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PCI\r
                                 root bridge.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a\r
                                 lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  OUT    VOID                                   *Buffer\r
  )\r
{\r
  EFI_STATUS                             Status;\r
  PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;\r
  UINT64                                 Translation;\r
\r
  Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,\r
                                       Count, Buffer);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
  Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  // Address passed to CpuIo->Mem.Read needs to be a host address instead of\r
  // device address.\r
  return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
      TO_HOST_ADDRESS (Address, Translation), Count, Buffer);\r
}\r
\r
/**\r
  Enables a PCI driver to access PCI controller registers in the PCI root\r
  bridge memory space.\r
\r
  The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r
  controller registers in the PCI root bridge memory space.\r
  The memory operations are carried out exactly as requested. The caller is\r
  responsible for satisfying any alignment and memory width restrictions that a\r
  PCI Root Bridge on a platform might require.\r
\r
  @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in]   Width     Signifies the width of the memory operation.\r
  @param[in]   Address   The base address of the memory operation. The caller\r
                         is responsible for aligning the Address if required.\r
  @param[in]   Count     The number of memory operations to perform. Bytes\r
                         moved is Width size * Count, starting at Address.\r
  @param[in]   Buffer    For read operations, the destination buffer to store\r
                         the results. For write operations, the source buffer\r
                         to write data from.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PCI\r
                                 root bridge.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a\r
                                 lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN     VOID                                   *Buffer\r
  )\r
{\r
  EFI_STATUS                             Status;\r
  PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;\r
  UINT64                                 Translation;\r
\r
  Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,\r
                                       Count, Buffer);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
  Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  // Address passed to CpuIo->Mem.Write needs to be a host address instead of\r
  // device address.\r
  return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
      TO_HOST_ADDRESS (Address, Translation), Count, Buffer);\r
}\r
\r
/**\r
  Enables a PCI driver to access PCI controller registers in the PCI root\r
  bridge I/O space.\r
\r
  @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in]   Width       Signifies the width of the memory operations.\r
  @param[in]   Address     The base address of the I/O operation. The caller is\r
                           responsible for aligning the Address if required.\r
  @param[in]   Count       The number of I/O operations to perform. Bytes moved\r
                           is Width size * Count, starting at Address.\r
  @param[out]  Buffer      For read operations, the destination buffer to store\r
                           the results. For write operations, the source buffer\r
                           to write data from.\r
\r
  @retval EFI_SUCCESS              The data was read from or written to the PCI\r
                                   root bridge.\r
  @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.\r
  @retval EFI_INVALID_PARAMETER    Buffer is NULL.\r
  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a\r
                                   lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  OUT    VOID                                   *Buffer\r
  )\r
{\r
  EFI_STATUS                                    Status;\r
  PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;\r
\r
  Status = RootBridgeIoCheckParameter (\r
             This, IoOperation, Width,\r
             Address, Count, Buffer\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
\r
  // Address passed to CpuIo->Io.Read needs to be a host address instead of\r
  // device address.\r
  return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
      TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);\r
}\r
\r
/**\r
  Enables a PCI driver to access PCI controller registers in the PCI root\r
  bridge I/O space.\r
\r
  @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in]   Width       Signifies the width of the memory operations.\r
  @param[in]   Address     The base address of the I/O operation. The caller is\r
                           responsible for aligning the Address if required.\r
  @param[in]   Count       The number of I/O operations to perform. Bytes moved\r
                           is Width size * Count, starting at Address.\r
  @param[in]   Buffer      For read operations, the destination buffer to store\r
                           the results. For write operations, the source buffer\r
                           to write data from.\r
\r
  @retval EFI_SUCCESS              The data was read from or written to the PCI\r
                                   root bridge.\r
  @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.\r
  @retval EFI_INVALID_PARAMETER    Buffer is NULL.\r
  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a\r
                                   lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoWrite (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,\r
  IN       UINT64                                  Address,\r
  IN       UINTN                                   Count,\r
  IN       VOID                                    *Buffer\r
  )\r
{\r
  EFI_STATUS                                    Status;\r
  PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;\r
\r
  Status = RootBridgeIoCheckParameter (\r
             This, IoOperation, Width,\r
             Address, Count, Buffer\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
\r
  // Address passed to CpuIo->Io.Write needs to be a host address instead of\r
  // device address.\r
  return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
      TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);\r
}\r
\r
/**\r
  Enables a PCI driver to copy one region of PCI root bridge memory space to\r
  another region of PCI root bridge memory space.\r
\r
  The CopyMem() function enables a PCI driver to copy one region of PCI root\r
  bridge memory space to another region of PCI root bridge memory space. This\r
  is especially useful for video scroll operation on a memory mapped video\r
  buffer.\r
  The memory operations are carried out exactly as requested. The caller is\r
  responsible for satisfying any alignment and memory width restrictions that a\r
  PCI root bridge on a platform might require.\r
\r
  @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
                         instance.\r
  @param[in] Width       Signifies the width of the memory operations.\r
  @param[in] DestAddress The destination address of the memory operation. The\r
                         caller is responsible for aligning the DestAddress if\r
                         required.\r
  @param[in] SrcAddress  The source address of the memory operation. The caller\r
                         is responsible for aligning the SrcAddress if\r
                         required.\r
  @param[in] Count       The number of memory operations to perform. Bytes\r
                         moved is Width size * Count, starting at DestAddress\r
                         and SrcAddress.\r
\r
  @retval  EFI_SUCCESS             The data was copied from one memory region\r
                                   to another memory region.\r
  @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.\r
  @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a\r
                                   lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoCopyMem (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,\r
  IN UINT64                                       DestAddress,\r
  IN UINT64                                       SrcAddress,\r
  IN UINTN                                        Count\r
  )\r
{\r
  EFI_STATUS  Status;\r
  BOOLEAN     Forward;\r
  UINTN       Stride;\r
  UINTN       Index;\r
  UINT64      Result;\r
\r
  if ((UINT32) Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (DestAddress == SrcAddress) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  Stride = (UINTN) (1 << Width);\r
\r
  Forward = TRUE;\r
  if ((DestAddress > SrcAddress) &&\r
      (DestAddress < (SrcAddress + Count * Stride))) {\r
    Forward = FALSE;\r
    SrcAddress = SrcAddress + (Count - 1) * Stride;\r
    DestAddress = DestAddress + (Count - 1) * Stride;\r
  }\r
\r
  for (Index = 0; Index < Count; Index++) {\r
    Status = RootBridgeIoMemRead (\r
               This,\r
               Width,\r
               SrcAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    Status = RootBridgeIoMemWrite (\r
               This,\r
               Width,\r
               DestAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    if (Forward) {\r
      SrcAddress += Stride;\r
      DestAddress += Stride;\r
    } else {\r
      SrcAddress -= Stride;\r
      DestAddress -= Stride;\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  PCI configuration space access.\r
\r
  @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
  @param Read     TRUE indicating it's a read operation.\r
  @param Width    Signifies the width of the memory operation.\r
  @param Address  The address within the PCI configuration space\r
                  for the PCI controller.\r
  @param Count    The number of PCI configuration operations\r
                  to perform.\r
  @param Buffer   The destination buffer to store the results.\r
\r
  @retval EFI_SUCCESS            The data was read/written from/to the PCI root bridge.\r
  @retval EFI_INVALID_PARAMETER  Invalid parameters found.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciAccess (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,\r
  IN     BOOLEAN                               Read,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
  IN     UINT64                                Address,\r
  IN     UINTN                                 Count,\r
  IN OUT VOID                                  *Buffer\r
  )\r
{\r
  EFI_STATUS                                   Status;\r
  PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  PciAddress;\r
  UINT8                                        *Uint8Buffer;\r
  UINT8                                        InStride;\r
  UINT8                                        OutStride;\r
  UINTN                                        Size;\r
\r
  Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Read Pci configuration space\r
  //\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
  CopyMem (&PciAddress, &Address, sizeof (PciAddress));\r
\r
  if (PciAddress.ExtendedRegister == 0) {\r
    PciAddress.ExtendedRegister = PciAddress.Register;\r
  }\r
\r
  Address = PCI_SEGMENT_LIB_ADDRESS (\r
              RootBridge->RootBridgeIo.SegmentNumber,\r
              PciAddress.Bus,\r
              PciAddress.Device,\r
              PciAddress.Function,\r
              PciAddress.ExtendedRegister\r
              );\r
\r
  //\r
  // Select loop based on the width of the transfer\r
  //\r
  InStride  = mInStride[Width];\r
  OutStride = mOutStride[Width];\r
  Size      = (UINTN) (1 << (Width & 0x03));\r
  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
    if (Read) {\r
      PciSegmentReadBuffer (Address, Size, Uint8Buffer);\r
    } else {\r
      PciSegmentWriteBuffer (Address, Size, Uint8Buffer);\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Allows read from PCI configuration space.\r
\r
  @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
  @param Width    Signifies the width of the memory operation.\r
  @param Address  The address within the PCI configuration space\r
                  for the PCI controller.\r
  @param Count    The number of PCI configuration operations\r
                  to perform.\r
  @param Buffer   The destination buffer to store the results.\r
\r
  @retval EFI_SUCCESS           The data was read from the PCI root bridge.\r
  @retval EFI_INVALID_PARAMETER Invalid parameters found.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
  IN     UINT64                                Address,\r
  IN     UINTN                                 Count,\r
  IN OUT VOID                                  *Buffer\r
  )\r
{\r
  return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
  Allows write to PCI configuration space.\r
\r
  @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
  @param Width    Signifies the width of the memory operation.\r
  @param Address  The address within the PCI configuration space\r
                  for the PCI controller.\r
  @param Count    The number of PCI configuration operations\r
                  to perform.\r
  @param Buffer   The source buffer to get the results.\r
\r
  @retval EFI_SUCCESS            The data was written to the PCI root bridge.\r
  @retval EFI_INVALID_PARAMETER  Invalid parameters found.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
  IN     UINT64                                Address,\r
  IN     UINTN                                 Count,\r
  IN OUT VOID                                  *Buffer\r
  )\r
{\r
  return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
  Provides the PCI controller-specific address needed to access\r
  system memory for DMA.\r
\r
  @param This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param Operation      Indicate if the bus master is going to read or write\r
                        to system memory.\r
  @param HostAddress    The system memory address to map on the PCI controller.\r
  @param NumberOfBytes  On input the number of bytes to map.\r
                        On output the number of bytes that were mapped.\r
  @param DeviceAddress  The resulting map address for the bus master PCI\r
                        controller to use to access the system memory's HostAddress.\r
  @param Mapping        The value to pass to Unmap() when the bus master DMA\r
                        operation is complete.\r
\r
  @retval EFI_SUCCESS            Success.\r
  @retval EFI_INVALID_PARAMETER  Invalid parameters found.\r
  @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_DEVICE_ERROR       The System hardware could not map the requested address.\r
  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMap (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  )\r
{\r
  EFI_STATUS                                        Status;\r
  PCI_ROOT_BRIDGE_INSTANCE                          *RootBridge;\r
  EFI_PHYSICAL_ADDRESS                              PhysicalAddress;\r
  MAP_INFO                                          *MapInfo;\r
\r
  if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||\r
      Mapping == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Make sure that Operation is valid\r
  //\r
  if ((UINT32) Operation >= EfiPciOperationMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
\r
  if (mIoMmuProtocol != NULL) {\r
    if (!RootBridge->DmaAbove4G) {\r
      //\r
      // Clear 64bit support\r
      //\r
      if (Operation > EfiPciOperationBusMasterCommonBuffer) {\r
        Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - EfiPciOperationBusMasterRead64);\r
      }\r
    }\r
    Status = mIoMmuProtocol->Map (\r
                               mIoMmuProtocol,\r
                               (EDKII_IOMMU_OPERATION) Operation,\r
                               HostAddress,\r
                               NumberOfBytes,\r
                               DeviceAddress,\r
                               Mapping\r
                               );\r
    return Status;\r
  }\r
\r
  PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
  if ((!RootBridge->DmaAbove4G ||\r
       (Operation != EfiPciOperationBusMasterRead64 &&\r
        Operation != EfiPciOperationBusMasterWrite64 &&\r
        Operation != EfiPciOperationBusMasterCommonBuffer64)) &&\r
      ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) {\r
\r
    //\r
    // If the root bridge or the device cannot handle performing DMA above\r
    // 4GB but any part of the DMA transfer being mapped is above 4GB, then\r
    // map the DMA transfer to a buffer below 4GB.\r
    //\r
\r
    if (Operation == EfiPciOperationBusMasterCommonBuffer ||\r
        Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
      //\r
      // Common Buffer operations can not be remapped.  If the common buffer\r
      // if above 4GB, then it is not possible to generate a mapping, so return\r
      // an error.\r
      //\r
      return EFI_UNSUPPORTED;\r
    }\r
\r
    //\r
    // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
    // called later.\r
    //\r
    MapInfo = AllocatePool (sizeof (MAP_INFO));\r
    if (MapInfo == NULL) {\r
      *NumberOfBytes = 0;\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
\r
    //\r
    // Initialize the MAP_INFO structure\r
    //\r
    MapInfo->Signature         = MAP_INFO_SIGNATURE;\r
    MapInfo->Operation         = Operation;\r
    MapInfo->NumberOfBytes     = *NumberOfBytes;\r
    MapInfo->NumberOfPages     = EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes);\r
    MapInfo->HostAddress       = PhysicalAddress;\r
    MapInfo->MappedHostAddress = SIZE_4GB - 1;\r
\r
    //\r
    // Allocate a buffer below 4GB to map the transfer to.\r
    //\r
    Status = gBS->AllocatePages (\r
                    AllocateMaxAddress,\r
                    EfiBootServicesData,\r
                    MapInfo->NumberOfPages,\r
                    &MapInfo->MappedHostAddress\r
                    );\r
    if (EFI_ERROR (Status)) {\r
      FreePool (MapInfo);\r
      *NumberOfBytes = 0;\r
      return Status;\r
    }\r
\r
    //\r
    // If this is a read operation from the Bus Master's point of view,\r
    // then copy the contents of the real buffer into the mapped buffer\r
    // so the Bus Master can read the contents of the real buffer.\r
    //\r
    if (Operation == EfiPciOperationBusMasterRead ||\r
        Operation == EfiPciOperationBusMasterRead64) {\r
      CopyMem (\r
        (VOID *) (UINTN) MapInfo->MappedHostAddress,\r
        (VOID *) (UINTN) MapInfo->HostAddress,\r
        MapInfo->NumberOfBytes\r
        );\r
    }\r
\r
    InsertTailList (&RootBridge->Maps, &MapInfo->Link);\r
\r
    //\r
    // The DeviceAddress is the address of the maped buffer below 4GB\r
    //\r
    *DeviceAddress = MapInfo->MappedHostAddress;\r
    //\r
    // Return a pointer to the MAP_INFO structure in Mapping\r
    //\r
    *Mapping       = MapInfo;\r
  } else {\r
    //\r
    // If the root bridge CAN handle performing DMA above 4GB or\r
    // the transfer is below 4GB, so the DeviceAddress is simply the\r
    // HostAddress\r
    //\r
    *DeviceAddress = PhysicalAddress;\r
    *Mapping       = NO_MAPPING;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  The Unmap() function completes the Map() operation and releases any\r
  corresponding resources.\r
  If the operation was an EfiPciOperationBusMasterWrite or\r
  EfiPciOperationBusMasterWrite64, the data is committed to the target system\r
  memory.\r
  Any resources used for the mapping are freed.\r
\r
  @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in] Mapping   The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS            The range was unmapped.\r
  @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().\r
  @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoUnmap (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN VOID                             *Mapping\r
  )\r
{\r
  MAP_INFO                 *MapInfo;\r
  LIST_ENTRY               *Link;\r
  PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
  EFI_STATUS                Status;\r
\r
  if (mIoMmuProtocol != NULL) {\r
    Status = mIoMmuProtocol->Unmap (\r
                               mIoMmuProtocol,\r
                               Mapping\r
                               );\r
    return Status;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
\r
  //\r
  // See if the Map() operation associated with this Unmap() required a mapping\r
  // buffer. If a mapping buffer was not required, then this function simply\r
  // returns EFI_SUCCESS.\r
  //\r
  if (Mapping == NO_MAPPING) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  MapInfo = NO_MAPPING;\r
  for (Link = GetFirstNode (&RootBridge->Maps)\r
       ; !IsNull (&RootBridge->Maps, Link)\r
       ; Link = GetNextNode (&RootBridge->Maps, Link)\r
       ) {\r
    MapInfo = MAP_INFO_FROM_LINK (Link);\r
    if (MapInfo == Mapping) {\r
      break;\r
    }\r
  }\r
  //\r
  // Mapping is not a valid value returned by Map()\r
  //\r
  if (MapInfo != Mapping) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  RemoveEntryList (&MapInfo->Link);\r
\r
  //\r
  // If this is a write operation from the Bus Master's point of view,\r
  // then copy the contents of the mapped buffer into the real buffer\r
  // so the processor can read the contents of the real buffer.\r
  //\r
  if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||\r
      MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
    CopyMem (\r
      (VOID *) (UINTN) MapInfo->HostAddress,\r
      (VOID *) (UINTN) MapInfo->MappedHostAddress,\r
      MapInfo->NumberOfBytes\r
      );\r
  }\r
\r
  //\r
  // Free the mapped buffer and the MAP_INFO structure.\r
  //\r
  gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
  FreePool (Mapping);\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer\r
  or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
\r
  @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param Type        This parameter is not used and must be ignored.\r
  @param MemoryType  The type of memory to allocate, EfiBootServicesData or\r
                     EfiRuntimeServicesData.\r
  @param Pages       The number of pages to allocate.\r
  @param HostAddress A pointer to store the base system memory address of the\r
                     allocated range.\r
  @param Attributes  The requested bit mask of attributes for the allocated\r
                     range. Only the attributes\r
                     EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,\r
                     EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and\r
                     EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this\r
                     function.\r
\r
  @retval EFI_SUCCESS            The requested memory pages were allocated.\r
  @retval EFI_INVALID_PARAMETER  MemoryType is invalid.\r
  @retval EFI_INVALID_PARAMETER  HostAddress is NULL.\r
  @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal\r
                                 attribute bits are MEMORY_WRITE_COMBINE,\r
                                 MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
  @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoAllocateBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  EFI_ALLOCATE_TYPE                Type,\r
  IN  EFI_MEMORY_TYPE                  MemoryType,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             **HostAddress,\r
  IN  UINT64                           Attributes\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EFI_PHYSICAL_ADDRESS      PhysicalAddress;\r
  PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;\r
  EFI_ALLOCATE_TYPE         AllocateType;\r
\r
  //\r
  // Validate Attributes\r
  //\r
  if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Check for invalid inputs\r
  //\r
  if (HostAddress == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // The only valid memory types are EfiBootServicesData and\r
  // EfiRuntimeServicesData\r
  //\r
  if (MemoryType != EfiBootServicesData &&\r
      MemoryType != EfiRuntimeServicesData) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
\r
  if (mIoMmuProtocol != NULL) {\r
    if (!RootBridge->DmaAbove4G) {\r
      //\r
      // Clear DUAL_ADDRESS_CYCLE\r
      //\r
      Attributes &= ~((UINT64) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
    }\r
    Status = mIoMmuProtocol->AllocateBuffer (\r
                               mIoMmuProtocol,\r
                               Type,\r
                               MemoryType,\r
                               Pages,\r
                               HostAddress,\r
                               Attributes\r
                               );\r
    return Status;\r
  }\r
\r
  AllocateType = AllocateAnyPages;\r
  if (!RootBridge->DmaAbove4G ||\r
      (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {\r
    //\r
    // Limit allocations to memory below 4GB\r
    //\r
    AllocateType    = AllocateMaxAddress;\r
    PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (SIZE_4GB - 1);\r
  }\r
  Status = gBS->AllocatePages (\r
                  AllocateType,\r
                  MemoryType,\r
                  Pages,\r
                  &PhysicalAddress\r
                  );\r
  if (!EFI_ERROR (Status)) {\r
    *HostAddress = (VOID *) (UINTN) PhysicalAddress;\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  The FreeBuffer() function frees memory that was allocated with\r
  AllocateBuffer().\r
\r
  @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param Pages       The number of pages to free.\r
  @param HostAddress The base system memory address of the allocated range.\r
\r
  @retval EFI_SUCCESS            The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and\r
                                 Pages was not allocated with AllocateBuffer().\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFreeBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             *HostAddress\r
  )\r
{\r
  EFI_STATUS                Status;\r
\r
  if (mIoMmuProtocol != NULL) {\r
    Status = mIoMmuProtocol->FreeBuffer (\r
                               mIoMmuProtocol,\r
                               Pages,\r
                               HostAddress\r
                               );\r
    return Status;\r
  }\r
\r
  return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
}\r
\r
/**\r
  Flushes all PCI posted write transactions from a PCI host bridge to system\r
  memory.\r
\r
  The Flush() function flushes any PCI posted write transactions from a PCI\r
  host bridge to system memory. Posted write transactions are generated by PCI\r
  bus masters when they perform write transactions to target addresses in\r
  system memory.\r
  This function does not flush posted write transactions from any PCI bridges.\r
  A PCI controller specific action must be taken to guarantee that the posted\r
  write transactions have been flushed from the PCI controller and from all the\r
  PCI bridges into the PCI host bridge. This is typically done with a PCI read\r
  transaction from the PCI controller prior to calling Flush().\r
\r
  @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
\r
  @retval EFI_SUCCESS        The PCI posted write transactions were flushed\r
                             from the PCI host bridge to system memory.\r
  @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed\r
                             from the PCI host bridge due to a hardware error.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFlush (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This\r
  )\r
{\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Gets the attributes that a PCI root bridge supports setting with\r
  SetAttributes(), and the attributes that a PCI root bridge is currently\r
  using.\r
\r
  The GetAttributes() function returns the mask of attributes that this PCI\r
  root bridge supports and the mask of attributes that the PCI root bridge is\r
  currently using.\r
\r
  @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param Supported   A pointer to the mask of attributes that this PCI root\r
                     bridge supports setting with SetAttributes().\r
  @param Attributes  A pointer to the mask of attributes that this PCI root\r
                     bridge is currently using.\r
\r
  @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes\r
                                 that the PCI root bridge supports is returned\r
                                 in Supports. If Attributes is not NULL, then\r
                                 the attributes that the PCI root bridge is\r
                                 currently using is returned in Attributes.\r
  @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoGetAttributes (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  OUT UINT64                           *Supported,\r
  OUT UINT64                           *Attributes\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
\r
  if (Attributes == NULL && Supported == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
  //\r
  // Set the return value for Supported and Attributes\r
  //\r
  if (Supported != NULL) {\r
    *Supported  = RootBridge->Supports;\r
  }\r
\r
  if (Attributes != NULL) {\r
    *Attributes = RootBridge->Attributes;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Sets attributes for a resource range on a PCI root bridge.\r
\r
  The SetAttributes() function sets the attributes specified in Attributes for\r
  the PCI root bridge on the resource range specified by ResourceBase and\r
  ResourceLength. Since the granularity of setting these attributes may vary\r
  from resource type to resource type, and from platform to platform, the\r
  actual resource range and the one passed in by the caller may differ. As a\r
  result, this function may set the attributes specified by Attributes on a\r
  larger resource range than the caller requested. The actual range is returned\r
  in ResourceBase and ResourceLength. The caller is responsible for verifying\r
  that the actual range for which the attributes were set is acceptable.\r
\r
  @param This            A pointer to the\r
                         EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param Attributes      The mask of attributes to set. If the\r
                         attribute bit MEMORY_WRITE_COMBINE,\r
                         MEMORY_CACHED, or MEMORY_DISABLE is set,\r
                         then the resource range is specified by\r
                         ResourceBase and ResourceLength. If\r
                         MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
                         MEMORY_DISABLE are not set, then\r
                         ResourceBase and ResourceLength are ignored,\r
                         and may be NULL.\r
  @param ResourceBase    A pointer to the base address of the\r
                         resource range to be modified by the\r
                         attributes specified by Attributes.\r
  @param ResourceLength  A pointer to the length of the resource\r
                                   range to be modified by the attributes\r
                                   specified by Attributes.\r
\r
  @retval  EFI_SUCCESS           The current configuration of this PCI root bridge\r
                                 was returned in Resources.\r
  @retval  EFI_UNSUPPORTED       The current configuration of this PCI root bridge\r
                                 could not be retrieved.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoSetAttributes (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN     UINT64                           Attributes,\r
  IN OUT UINT64                           *ResourceBase,\r
  IN OUT UINT64                           *ResourceLength\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE            *RootBridge;\r
\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
\r
  if ((Attributes & (~RootBridge->Supports)) != 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  RootBridge->Attributes = Attributes;\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Retrieves the current resource settings of this PCI root bridge in the form\r
  of a set of ACPI resource descriptors.\r
\r
  There are only two resource descriptor types from the ACPI Specification that\r
  may be used to describe the current resources allocated to a PCI root bridge.\r
  These are the QWORD Address Space Descriptor, and the End Tag. The QWORD\r
  Address Space Descriptor can describe memory, I/O, and bus number ranges for\r
  dynamic or fixed resources. The configuration of a PCI root bridge is described\r
  with one or more QWORD Address Space Descriptors followed by an End Tag.\r
\r
  @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[out]  Resources   A pointer to the resource descriptors that\r
                           describe the current configuration of this PCI root\r
                           bridge. The storage for the resource\r
                           descriptors is allocated by this function. The\r
                           caller must treat the return buffer as read-only\r
                           data, and the buffer must not be freed by the\r
                           caller.\r
\r
  @retval  EFI_SUCCESS     The current configuration of this PCI root bridge\r
                           was returned in Resources.\r
  @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge\r
                           could not be retrieved.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoConfiguration (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *This,\r
  OUT VOID                                **Resources\r
  )\r
{\r
  PCI_RESOURCE_TYPE                 Index;\r
  PCI_ROOT_BRIDGE_INSTANCE          *RootBridge;\r
  PCI_RES_NODE                      *ResAllocNode;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
  EFI_ACPI_END_TAG_DESCRIPTOR       *End;\r
\r
  //\r
  // Get this instance of the Root Bridge.\r
  //\r
  RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r
  ZeroMem (\r
    RootBridge->ConfigBuffer,\r
    TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
    );\r
  Descriptor = RootBridge->ConfigBuffer;\r
  for (Index = TypeIo; Index < TypeMax; Index++) {\r
\r
    ResAllocNode = &RootBridge->ResAllocNode[Index];\r
\r
    if (ResAllocNode->Status != ResAllocated) {\r
      continue;\r
    }\r
\r
    Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
    Descriptor->Len  = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
    // According to UEFI 2.7, RootBridgeIo->Configuration should return address\r
    // range in CPU view (host address), and ResAllocNode->Base is already a CPU\r
    // view address (host address).\r
    Descriptor->AddrRangeMin  = ResAllocNode->Base;\r
    Descriptor->AddrRangeMax  = ResAllocNode->Base + ResAllocNode->Length - 1;\r
    Descriptor->AddrLen       = ResAllocNode->Length;\r
    Descriptor->AddrTranslationOffset = GetTranslationByResourceType (\r
      RootBridge,\r
      ResAllocNode->Type\r
      );\r
\r
    switch (ResAllocNode->Type) {\r
\r
    case TypeIo:\r
      Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_IO;\r
      break;\r
\r
    case TypePMem32:\r
      Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
    case TypeMem32:\r
      Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
      Descriptor->AddrSpaceGranularity  = 32;\r
      break;\r
\r
    case TypePMem64:\r
      Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
    case TypeMem64:\r
      Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
      Descriptor->AddrSpaceGranularity  = 64;\r
      break;\r
\r
    case TypeBus:\r
      Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
      break;\r
\r
    default:\r
      break;\r
    }\r
\r
    Descriptor++;\r
  }\r
  //\r
  // Terminate the entries.\r
  //\r
  End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;\r
  End->Desc     = ACPI_END_TAG_DESCRIPTOR;\r
  End->Checksum = 0x0;\r
\r
  *Resources = RootBridge->ConfigBuffer;\r
  return EFI_SUCCESS;\r
}\r