projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 48555339 FT |
1 | /** @file\r |
| 2 | This driver is used to manage SD/MMC PCI host controllers which are compliance\r | |
| 3 | with SD Host Controller Simplified Specification version 3.00.\r | |
| 4 | \r | |
| 5 | It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r | |
| 6 | \r | |
| 7 | Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 8 | This program and the accompanying materials\r | |
| 9 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 10 | which accompanies this distribution. The full text of the license may be found at\r | |
| 11 | http://opensource.org/licenses/bsd-license.php\r | |
| 12 | \r | |
| 13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 15 | \r | |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #include "SdMmcPciHcDxe.h"\r | |
| 19 | \r | |
| 20 | /**\r | |
| 21 | Dump the content of SD/MMC host controller's Capability Register.\r | |
| 22 | \r | |
| 23 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 24 | @param[in] Capability The buffer to store the capability data.\r | |
| 25 | \r | |
| 26 | **/\r | |
| 27 | VOID\r | |
| 28 | DumpCapabilityReg (\r | |
| 29 | IN UINT8 Slot,\r | |
| 30 | IN SD_MMC_HC_SLOT_CAP *Capability\r | |
| 31 | )\r | |
| 32 | {\r | |
| 33 | //\r | |
| 34 | // Dump Capability Data\r | |
| 35 | //\r | |
| 36 | DEBUG ((EFI_D_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));\r | |
| 37 | DEBUG ((EFI_D_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));\r | |
| 38 | DEBUG ((EFI_D_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));\r | |
| 39 | DEBUG ((EFI_D_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));\r | |
| 40 | DEBUG ((EFI_D_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));\r | |
| 41 | DEBUG ((EFI_D_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));\r | |
| 42 | DEBUG ((EFI_D_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));\r | |
| 43 | DEBUG ((EFI_D_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));\r | |
| 44 | DEBUG ((EFI_D_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));\r | |
| 45 | DEBUG ((EFI_D_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r | |
| 46 | DEBUG ((EFI_D_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r | |
| 47 | DEBUG ((EFI_D_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r | |
| 48 | DEBUG ((EFI_D_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));\r | |
| 49 | DEBUG ((EFI_D_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r | |
| 50 | DEBUG ((EFI_D_INFO, " SlotType "));\r | |
| 51 | if (Capability->SlotType == 0x00) {\r | |
| 52 | DEBUG ((EFI_D_INFO, "%a\n", "Removable Slot"));\r | |
| 53 | } else if (Capability->SlotType == 0x01) {\r | |
| 54 | DEBUG ((EFI_D_INFO, "%a\n", "Embedded Slot"));\r | |
| 55 | } else if (Capability->SlotType == 0x02) {\r | |
| 56 | DEBUG ((EFI_D_INFO, "%a\n", "Shared Bus Slot"));\r | |
| 57 | } else {\r | |
| 58 | DEBUG ((EFI_D_INFO, "%a\n", "Reserved"));\r | |
| 59 | }\r | |
| 60 | DEBUG ((EFI_D_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));\r | |
| 61 | DEBUG ((EFI_D_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));\r | |
| 62 | DEBUG ((EFI_D_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));\r | |
| 63 | DEBUG ((EFI_D_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));\r | |
| 64 | DEBUG ((EFI_D_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));\r | |
| 65 | DEBUG ((EFI_D_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));\r | |
| 66 | DEBUG ((EFI_D_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));\r | |
| 67 | if (Capability->TimerCount == 0) {\r | |
| 68 | DEBUG ((EFI_D_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));\r | |
| 69 | } else {\r | |
| 70 | DEBUG ((EFI_D_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));\r | |
| 71 | }\r | |
| 72 | DEBUG ((EFI_D_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));\r | |
| 73 | DEBUG ((EFI_D_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));\r | |
| 74 | DEBUG ((EFI_D_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));\r | |
| 75 | DEBUG ((EFI_D_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));\r | |
| 76 | return;\r | |
| 77 | }\r | |
| 78 | \r | |
| 79 | /**\r | |
| 80 | Read SlotInfo register from SD/MMC host controller pci config space.\r | |
| 81 | \r | |
| 82 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 83 | @param[out] FirstBar The buffer to store the first BAR value.\r | |
| 84 | @param[out] SlotNum The buffer to store the supported slot number.\r | |
| 85 | \r | |
| 86 | @retval EFI_SUCCESS The operation succeeds.\r | |
| 87 | @retval Others The operation fails.\r | |
| 88 | \r | |
| 89 | **/\r | |
| 90 | EFI_STATUS\r | |
| 91 | EFIAPI\r | |
| 92 | SdMmcHcGetSlotInfo (\r | |
| 93 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 94 | OUT UINT8 *FirstBar,\r | |
| 95 | OUT UINT8 *SlotNum\r | |
| 96 | )\r | |
| 97 | {\r | |
| 98 | EFI_STATUS Status;\r | |
| 99 | SD_MMC_HC_SLOT_INFO SlotInfo;\r | |
| 100 | \r | |
| 101 | Status = PciIo->Pci.Read (\r | |
| 102 | PciIo,\r | |
| 103 | EfiPciIoWidthUint8,\r | |
| 104 | SD_MMC_HC_SLOT_OFFSET,\r | |
| 105 | sizeof (SlotInfo),\r | |
| 106 | &SlotInfo\r | |
| 107 | );\r | |
| 108 | if (EFI_ERROR (Status)) {\r | |
| 109 | return Status;\r | |
| 110 | }\r | |
| 111 | \r | |
| 112 | *FirstBar = SlotInfo.FirstBar;\r | |
| 113 | *SlotNum = SlotInfo.SlotNum + 1;\r | |
| 114 | ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);\r | |
| 115 | return EFI_SUCCESS;\r | |
| 116 | }\r | |
| 117 | \r | |
| 118 | /**\r | |
| 119 | Read/Write specified SD/MMC host controller mmio register.\r | |
| 120 | \r | |
| 121 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 122 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
| 123 | header to use as the base address for the memory\r | |
| 124 | operation to perform.\r | |
| 125 | @param[in] Offset The offset within the selected BAR to start the\r | |
| 126 | memory operation.\r | |
| 127 | @param[in] Read A boolean to indicate it's read or write operation.\r | |
| 128 | @param[in] Count The width of the mmio register in bytes.\r | |
| 129 | Must be 1, 2 , 4 or 8 bytes.\r | |
| 130 | @param[in, out] Data For read operations, the destination buffer to store\r | |
| 131 | the results. For write operations, the source buffer\r | |
| 132 | to write data from. The caller is responsible for\r | |
| 133 | having ownership of the data buffer and ensuring its\r | |
| 134 | size not less than Count bytes.\r | |
| 135 | \r | |
| 136 | @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r | |
| 137 | @retval EFI_SUCCESS The read/write operation succeeds.\r | |
| 138 | @retval Others The read/write operation fails.\r | |
| 139 | \r | |
| 140 | **/\r | |
| 141 | EFI_STATUS\r | |
| 142 | EFIAPI\r | |
| 143 | SdMmcHcRwMmio (\r | |
| 144 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 145 | IN UINT8 BarIndex,\r | |
| 146 | IN UINT32 Offset,\r | |
| 147 | IN BOOLEAN Read,\r | |
| 148 | IN UINT8 Count,\r | |
| 149 | IN OUT VOID *Data\r | |
| 150 | )\r | |
| 151 | {\r | |
| 152 | EFI_STATUS Status;\r | |
| 153 | \r | |
| 154 | if ((PciIo == NULL) || (Data == NULL)) {\r | |
| 155 | return EFI_INVALID_PARAMETER;\r | |
| 156 | }\r | |
| 157 | \r | |
| 158 | if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {\r | |
| 159 | return EFI_INVALID_PARAMETER;\r | |
| 160 | }\r | |
| 161 | \r | |
| 162 | if (Read) {\r | |
| 163 | Status = PciIo->Mem.Read (\r | |
| 164 | PciIo,\r | |
| 165 | EfiPciIoWidthUint8,\r | |
| 166 | BarIndex,\r | |
| 167 | (UINT64) Offset,\r | |
| 168 | Count,\r | |
| 169 | Data\r | |
| 170 | );\r | |
| 171 | } else {\r | |
| 172 | Status = PciIo->Mem.Write (\r | |
| 173 | PciIo,\r | |
| 174 | EfiPciIoWidthUint8,\r | |
| 175 | BarIndex,\r | |
| 176 | (UINT64) Offset,\r | |
| 177 | Count,\r | |
| 178 | Data\r | |
| 179 | );\r | |
| 180 | }\r | |
| 181 | \r | |
| 182 | return Status;\r | |
| 183 | }\r | |
| 184 | \r | |
| 185 | /**\r | |
| 186 | Do OR operation with the value of the specified SD/MMC host controller mmio register.\r | |
| 187 | \r | |
| 188 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 189 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
| 190 | header to use as the base address for the memory\r | |
| 191 | operation to perform.\r | |
| 192 | @param[in] Offset The offset within the selected BAR to start the\r | |
| 193 | memory operation.\r | |
| 194 | @param[in] Count The width of the mmio register in bytes.\r | |
| 195 | Must be 1, 2 , 4 or 8 bytes.\r | |
| 196 | @param[in] OrData The pointer to the data used to do OR operation.\r | |
| 197 | The caller is responsible for having ownership of\r | |
| 198 | the data buffer and ensuring its size not less than\r | |
| 199 | Count bytes.\r | |
| 200 | \r | |
| 201 | @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r | |
| 202 | @retval EFI_SUCCESS The OR operation succeeds.\r | |
| 203 | @retval Others The OR operation fails.\r | |
| 204 | \r | |
| 205 | **/\r | |
| 206 | EFI_STATUS\r | |
| 207 | EFIAPI\r | |
| 208 | SdMmcHcOrMmio (\r | |
| 209 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 210 | IN UINT8 BarIndex,\r | |
| 211 | IN UINT32 Offset,\r | |
| 212 | IN UINT8 Count,\r | |
| 213 | IN VOID *OrData\r | |
| 214 | )\r | |
| 215 | {\r | |
| 216 | EFI_STATUS Status;\r | |
| 217 | UINT64 Data;\r | |
| 218 | UINT64 Or;\r | |
| 219 | \r | |
| 220 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
| 221 | if (EFI_ERROR (Status)) {\r | |
| 222 | return Status;\r | |
| 223 | }\r | |
| 224 | \r | |
| 225 | if (Count == 1) {\r | |
| 226 | Or = *(UINT8*) OrData;\r | |
| 227 | } else if (Count == 2) {\r | |
| 228 | Or = *(UINT16*) OrData;\r | |
| 229 | } else if (Count == 4) {\r | |
| 230 | Or = *(UINT32*) OrData;\r | |
| 231 | } else if (Count == 8) {\r | |
| 232 | Or = *(UINT64*) OrData;\r | |
| 233 | } else {\r | |
| 234 | return EFI_INVALID_PARAMETER;\r | |
| 235 | }\r | |
| 236 | \r | |
| 237 | Data |= Or;\r | |
| 238 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
| 239 | \r | |
| 240 | return Status;\r | |
| 241 | }\r | |
| 242 | \r | |
| 243 | /**\r | |
| 244 | Do AND operation with the value of the specified SD/MMC host controller mmio register.\r | |
| 245 | \r | |
| 246 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 247 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
| 248 | header to use as the base address for the memory\r | |
| 249 | operation to perform.\r | |
| 250 | @param[in] Offset The offset within the selected BAR to start the\r | |
| 251 | memory operation.\r | |
| 252 | @param[in] Count The width of the mmio register in bytes.\r | |
| 253 | Must be 1, 2 , 4 or 8 bytes.\r | |
| 254 | @param[in] AndData The pointer to the data used to do AND operation.\r | |
| 255 | The caller is responsible for having ownership of\r | |
| 256 | the data buffer and ensuring its size not less than\r | |
| 257 | Count bytes.\r | |
| 258 | \r | |
| 259 | @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r | |
| 260 | @retval EFI_SUCCESS The AND operation succeeds.\r | |
| 261 | @retval Others The AND operation fails.\r | |
| 262 | \r | |
| 263 | **/\r | |
| 264 | EFI_STATUS\r | |
| 265 | EFIAPI\r | |
| 266 | SdMmcHcAndMmio (\r | |
| 267 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 268 | IN UINT8 BarIndex,\r | |
| 269 | IN UINT32 Offset,\r | |
| 270 | IN UINT8 Count,\r | |
| 271 | IN VOID *AndData\r | |
| 272 | )\r | |
| 273 | {\r | |
| 274 | EFI_STATUS Status;\r | |
| 275 | UINT64 Data;\r | |
| 276 | UINT64 And;\r | |
| 277 | \r | |
| 278 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
| 279 | if (EFI_ERROR (Status)) {\r | |
| 280 | return Status;\r | |
| 281 | }\r | |
| 282 | \r | |
| 283 | if (Count == 1) {\r | |
| 284 | And = *(UINT8*) AndData;\r | |
| 285 | } else if (Count == 2) {\r | |
| 286 | And = *(UINT16*) AndData;\r | |
| 287 | } else if (Count == 4) {\r | |
| 288 | And = *(UINT32*) AndData;\r | |
| 289 | } else if (Count == 8) {\r | |
| 290 | And = *(UINT64*) AndData;\r | |
| 291 | } else {\r | |
| 292 | return EFI_INVALID_PARAMETER;\r | |
| 293 | }\r | |
| 294 | \r | |
| 295 | Data &= And;\r | |
| 296 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
| 297 | \r | |
| 298 | return Status;\r | |
| 299 | }\r | |
| 300 | \r | |
| 301 | /**\r | |
| 302 | Wait for the value of the specified MMIO register set to the test value.\r | |
| 303 | \r | |
| 304 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 305 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
| 306 | header to use as the base address for the memory\r | |
| 307 | operation to perform.\r | |
| 308 | @param[in] Offset The offset within the selected BAR to start the\r | |
| 309 | memory operation.\r | |
| 310 | @param[in] Count The width of the mmio register in bytes.\r | |
| 311 | Must be 1, 2, 4 or 8 bytes.\r | |
| 312 | @param[in] MaskValue The mask value of memory.\r | |
| 313 | @param[in] TestValue The test value of memory.\r | |
| 314 | \r | |
| 315 | @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r | |
| 316 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
| 317 | @retval Others The MMIO operation fails.\r | |
| 318 | \r | |
| 319 | **/\r | |
| 320 | EFI_STATUS\r | |
| 321 | EFIAPI\r | |
| 322 | SdMmcHcCheckMmioSet (\r | |
| 323 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 324 | IN UINT8 BarIndex,\r | |
| 325 | IN UINT32 Offset,\r | |
| 326 | IN UINT8 Count,\r | |
| 327 | IN UINT64 MaskValue,\r | |
| 328 | IN UINT64 TestValue\r | |
| 329 | )\r | |
| 330 | {\r | |
| 331 | EFI_STATUS Status;\r | |
| 332 | UINT64 Value;\r | |
| 333 | \r | |
| 334 | //\r | |
| 335 | // Access PCI MMIO space to see if the value is the tested one.\r | |
| 336 | //\r | |
| 337 | Value = 0;\r | |
| 338 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);\r | |
| 339 | if (EFI_ERROR (Status)) {\r | |
| 340 | return Status;\r | |
| 341 | }\r | |
| 342 | \r | |
| 343 | Value &= MaskValue;\r | |
| 344 | \r | |
| 345 | if (Value == TestValue) {\r | |
| 346 | return EFI_SUCCESS;\r | |
| 347 | }\r | |
| 348 | \r | |
| 349 | return EFI_NOT_READY;\r | |
| 350 | }\r | |
| 351 | \r | |
| 352 | /**\r | |
| 353 | Wait for the value of the specified MMIO register set to the test value.\r | |
| 354 | \r | |
| 355 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 356 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
| 357 | header to use as the base address for the memory\r | |
| 358 | operation to perform.\r | |
| 359 | @param[in] Offset The offset within the selected BAR to start the\r | |
| 360 | memory operation.\r | |
| 361 | @param[in] Count The width of the mmio register in bytes.\r | |
| 362 | Must be 1, 2, 4 or 8 bytes.\r | |
| 363 | @param[in] MaskValue The mask value of memory.\r | |
| 364 | @param[in] TestValue The test value of memory.\r | |
| 365 | @param[in] Timeout The time out value for wait memory set, uses 1\r | |
| 366 | microsecond as a unit.\r | |
| 367 | \r | |
| 368 | @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r | |
| 369 | range.\r | |
| 370 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
| 371 | @retval Others The MMIO operation fails.\r | |
| 372 | \r | |
| 373 | **/\r | |
| 374 | EFI_STATUS\r | |
| 375 | EFIAPI\r | |
| 376 | SdMmcHcWaitMmioSet (\r | |
| 377 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 378 | IN UINT8 BarIndex,\r | |
| 379 | IN UINT32 Offset,\r | |
| 380 | IN UINT8 Count,\r | |
| 381 | IN UINT64 MaskValue,\r | |
| 382 | IN UINT64 TestValue,\r | |
| 383 | IN UINT64 Timeout\r | |
| 384 | )\r | |
| 385 | {\r | |
| 386 | EFI_STATUS Status;\r | |
| 387 | BOOLEAN InfiniteWait;\r | |
| 388 | \r | |
| 389 | if (Timeout == 0) {\r | |
| 390 | InfiniteWait = TRUE;\r | |
| 391 | } else {\r | |
| 392 | InfiniteWait = FALSE;\r | |
| 393 | }\r | |
| 394 | \r | |
| 395 | while (InfiniteWait || (Timeout > 0)) {\r | |
| 396 | Status = SdMmcHcCheckMmioSet (\r | |
| 397 | PciIo,\r | |
| 398 | BarIndex,\r | |
| 399 | Offset,\r | |
| 400 | Count,\r | |
| 401 | MaskValue,\r | |
| 402 | TestValue\r | |
| 403 | );\r | |
| 404 | if (Status != EFI_NOT_READY) {\r | |
| 405 | return Status;\r | |
| 406 | }\r | |
| 407 | \r | |
| 408 | //\r | |
| 409 | // Stall for 1 microsecond.\r | |
| 410 | //\r | |
| 411 | gBS->Stall (1);\r | |
| 412 | \r | |
| 413 | Timeout--;\r | |
| 414 | }\r | |
| 415 | \r | |
| 416 | return EFI_TIMEOUT;\r | |
| 417 | }\r | |
| 418 | \r | |
| 419 | /**\r | |
| 420 | Software reset the specified SD/MMC host controller and enable all interrupts.\r | |
| 421 | \r | |
| 422 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 423 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 424 | \r | |
| 425 | @retval EFI_SUCCESS The software reset executes successfully.\r | |
| 426 | @retval Others The software reset fails.\r | |
| 427 | \r | |
| 428 | **/\r | |
| 429 | EFI_STATUS\r | |
| 430 | SdMmcHcReset (\r | |
| 431 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 432 | IN UINT8 Slot\r | |
| 433 | )\r | |
| 434 | {\r | |
| 435 | EFI_STATUS Status;\r | |
| 436 | UINT8 SwReset;\r | |
| 437 | \r | |
| 438 | SwReset = 0xFF;\r | |
| 439 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);\r | |
| 440 | \r | |
| 441 | if (EFI_ERROR (Status)) {\r | |
| 442 | DEBUG ((EFI_D_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Status));\r | |
| 443 | return Status;\r | |
| 444 | }\r | |
| 445 | \r | |
| 446 | Status = SdMmcHcWaitMmioSet (\r | |
| 447 | PciIo,\r | |
| 448 | Slot,\r | |
| 449 | SD_MMC_HC_SW_RST,\r | |
| 450 | sizeof (SwReset),\r | |
| 451 | 0xFF,\r | |
| 452 | 0x00,\r | |
| 453 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
| 454 | );\r | |
| 455 | if (EFI_ERROR (Status)) {\r | |
| 456 | DEBUG ((EFI_D_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r | |
| 457 | return Status;\r | |
| 458 | }\r | |
| 459 | //\r | |
| 460 | // Enable all interrupt after reset all.\r | |
| 461 | //\r | |
| 462 | Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r | |
| 463 | \r | |
| 464 | return Status;\r | |
| 465 | }\r | |
| 466 | \r | |
| 467 | /**\r | |
| 468 | Set all interrupt status bits in Normal and Error Interrupt Status Enable\r | |
| 469 | register.\r | |
| 470 | \r | |
| 471 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 472 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 473 | \r | |
| 474 | @retval EFI_SUCCESS The operation executes successfully.\r | |
| 475 | @retval Others The operation fails.\r | |
| 476 | \r | |
| 477 | **/\r | |
| 478 | EFI_STATUS\r | |
| 479 | SdMmcHcEnableInterrupt (\r | |
| 480 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 481 | IN UINT8 Slot\r | |
| 482 | )\r | |
| 483 | {\r | |
| 484 | EFI_STATUS Status;\r | |
| 485 | UINT16 IntStatus;\r | |
| 486 | \r | |
| 487 | //\r | |
| 488 | // Enable all bits in Error Interrupt Status Enable Register\r | |
| 489 | //\r | |
| 490 | IntStatus = 0xFFFF;\r | |
| 491 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
| 492 | if (EFI_ERROR (Status)) {\r | |
| 493 | return Status;\r | |
| 494 | }\r | |
| 495 | //\r | |
| 496 | // Enable all bits in Normal Interrupt Status Enable Register\r | |
| 497 | //\r | |
| 498 | IntStatus = 0xFFFF;\r | |
| 499 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
| 500 | \r | |
| 501 | return Status;\r | |
| 502 | }\r | |
| 503 | \r | |
| 504 | /**\r | |
| 505 | Get the capability data from the specified slot.\r | |
| 506 | \r | |
| 507 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 508 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 509 | @param[out] Capability The buffer to store the capability data.\r | |
| 510 | \r | |
| 511 | @retval EFI_SUCCESS The operation executes successfully.\r | |
| 512 | @retval Others The operation fails.\r | |
| 513 | \r | |
| 514 | **/\r | |
| 515 | EFI_STATUS\r | |
| 516 | SdMmcHcGetCapability (\r | |
| 517 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 518 | IN UINT8 Slot,\r | |
| 519 | OUT SD_MMC_HC_SLOT_CAP *Capability\r | |
| 520 | )\r | |
| 521 | {\r | |
| 522 | EFI_STATUS Status;\r | |
| 523 | UINT64 Cap;\r | |
| 524 | \r | |
| 525 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r | |
| 526 | if (EFI_ERROR (Status)) {\r | |
| 527 | return Status;\r | |
| 528 | }\r | |
| 529 | \r | |
| 530 | CopyMem (Capability, &Cap, sizeof (Cap));\r | |
| 531 | \r | |
| 532 | return EFI_SUCCESS;\r | |
| 533 | }\r | |
| 534 | \r | |
| 535 | /**\r | |
| 536 | Get the maximum current capability data from the specified slot.\r | |
| 537 | \r | |
| 538 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 539 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 540 | @param[out] MaxCurrent The buffer to store the maximum current capability data.\r | |
| 541 | \r | |
| 542 | @retval EFI_SUCCESS The operation executes successfully.\r | |
| 543 | @retval Others The operation fails.\r | |
| 544 | \r | |
| 545 | **/\r | |
| 546 | EFI_STATUS\r | |
| 547 | SdMmcHcGetMaxCurrent (\r | |
| 548 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 549 | IN UINT8 Slot,\r | |
| 550 | OUT UINT64 *MaxCurrent\r | |
| 551 | )\r | |
| 552 | {\r | |
| 553 | EFI_STATUS Status;\r | |
| 554 | \r | |
| 555 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);\r | |
| 556 | \r | |
| 557 | return Status;\r | |
| 558 | }\r | |
| 559 | \r | |
| 560 | /**\r | |
| 561 | Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r | |
| 562 | slot.\r | |
| 563 | \r | |
| 564 | Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r | |
| 565 | \r | |
| 566 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 567 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 568 | @param[out] MediaPresent The pointer to the media present boolean value.\r | |
| 569 | \r | |
| 570 | @retval EFI_SUCCESS There is no media change happened.\r | |
| 571 | @retval EFI_MEDIA_CHANGED There is media change happened.\r | |
| 572 | @retval Others The detection fails.\r | |
| 573 | \r | |
| 574 | **/\r | |
| 575 | EFI_STATUS\r | |
| 576 | SdMmcHcCardDetect (\r | |
| 577 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 578 | IN UINT8 Slot,\r | |
| 579 | OUT BOOLEAN *MediaPresent\r | |
| 580 | )\r | |
| 581 | {\r | |
| 582 | EFI_STATUS Status;\r | |
| 583 | UINT16 Data;\r | |
| 584 | UINT32 PresentState;\r | |
| 585 | \r | |
| 586 | //\r | |
| 587 | // Check Normal Interrupt Status Register\r | |
| 588 | //\r | |
| 589 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r | |
| 590 | if (EFI_ERROR (Status)) {\r | |
| 591 | return Status;\r | |
| 592 | }\r | |
| 593 | \r | |
| 594 | if ((Data & (BIT6 | BIT7)) != 0) {\r | |
| 595 | //\r | |
| 596 | // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r | |
| 597 | //\r | |
| 598 | Data &= BIT6 | BIT7;\r | |
| 599 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r | |
| 600 | if (EFI_ERROR (Status)) {\r | |
| 601 | return Status;\r | |
| 602 | }\r | |
| 603 | \r | |
| 604 | //\r | |
| 605 | // Check Present State Register to see if there is a card presented.\r | |
| 606 | //\r | |
| 607 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r | |
| 608 | if (EFI_ERROR (Status)) {\r | |
| 609 | return Status;\r | |
| 610 | }\r | |
| 611 | \r | |
| 612 | if ((PresentState & BIT16) != 0) {\r | |
| 613 | *MediaPresent = TRUE;\r | |
| 614 | } else {\r | |
| 615 | *MediaPresent = FALSE;\r | |
| 616 | }\r | |
| 617 | return EFI_MEDIA_CHANGED;\r | |
| 618 | }\r | |
| 619 | \r | |
| 620 | return EFI_SUCCESS;\r | |
| 621 | }\r | |
| 622 | \r | |
| 623 | /**\r | |
| 624 | Stop SD/MMC card clock.\r | |
| 625 | \r | |
| 626 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r | |
| 627 | \r | |
| 628 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 629 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 630 | \r | |
| 631 | @retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r | |
| 632 | @retval Others Fail to stop SD/MMC clock.\r | |
| 633 | \r | |
| 634 | **/\r | |
| 635 | EFI_STATUS\r | |
| 636 | SdMmcHcStopClock (\r | |
| 637 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 638 | IN UINT8 Slot\r | |
| 639 | )\r | |
| 640 | {\r | |
| 641 | EFI_STATUS Status;\r | |
| 642 | UINT32 PresentState;\r | |
| 643 | UINT16 ClockCtrl;\r | |
| 644 | \r | |
| 645 | //\r | |
| 646 | // Ensure no SD transactions are occurring on the SD Bus by\r | |
| 647 | // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r | |
| 648 | // in the Present State register to be 0.\r | |
| 649 | //\r | |
| 650 | Status = SdMmcHcWaitMmioSet (\r | |
| 651 | PciIo,\r | |
| 652 | Slot,\r | |
| 653 | SD_MMC_HC_PRESENT_STATE,\r | |
| 654 | sizeof (PresentState),\r | |
| 655 | BIT0 | BIT1,\r | |
| 656 | 0,\r | |
| 657 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
| 658 | );\r | |
| 659 | if (EFI_ERROR (Status)) {\r | |
| 660 | return Status;\r | |
| 661 | }\r | |
| 662 | \r | |
| 663 | //\r | |
| 664 | // Set SD Clock Enable in the Clock Control register to 0\r | |
| 665 | //\r | |
| 666 | ClockCtrl = (UINT16)~BIT2;\r | |
| 667 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
| 668 | \r | |
| 669 | return Status;\r | |
| 670 | }\r | |
| 671 | \r | |
| 672 | /**\r | |
| 673 | SD/MMC card clock supply.\r | |
| 674 | \r | |
| 675 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r | |
| 676 | \r | |
| 677 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 678 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 679 | @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r | |
| 680 | @param[in] Capability The capability of the slot.\r | |
| 681 | \r | |
| 682 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
| 683 | @retval Others The clock isn't supplied successfully.\r | |
| 684 | \r | |
| 685 | **/\r | |
| 686 | EFI_STATUS\r | |
| 687 | SdMmcHcClockSupply (\r | |
| 688 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 689 | IN UINT8 Slot,\r | |
| 690 | IN UINT64 ClockFreq,\r | |
| 691 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
| 692 | )\r | |
| 693 | {\r | |
| 694 | EFI_STATUS Status;\r | |
| 695 | UINT32 BaseClkFreq;\r | |
| 696 | UINT32 SettingFreq;\r | |
| 697 | UINT32 Divisor;\r | |
| 698 | UINT32 Remainder;\r | |
| 699 | UINT16 ControllerVer;\r | |
| 700 | UINT16 ClockCtrl;\r | |
| 701 | \r | |
| 702 | //\r | |
| 703 | // Calculate a divisor for SD clock frequency\r | |
| 704 | //\r | |
| 705 | ASSERT (Capability.BaseClkFreq != 0);\r | |
| 706 | \r | |
| 707 | BaseClkFreq = Capability.BaseClkFreq;\r | |
| 708 | if ((ClockFreq > (BaseClkFreq * 1000)) || (ClockFreq == 0)) {\r | |
| 709 | return EFI_INVALID_PARAMETER;\r | |
| 710 | }\r | |
| 711 | //\r | |
| 712 | // Calculate the divisor of base frequency.\r | |
| 713 | //\r | |
| 714 | Divisor = 0;\r | |
| 715 | SettingFreq = BaseClkFreq * 1000;\r | |
| 716 | while (ClockFreq < SettingFreq) {\r | |
| 717 | Divisor++;\r | |
| 718 | \r | |
| 719 | SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r | |
| 720 | Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r | |
| 721 | if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r | |
| 722 | break;\r | |
| 723 | }\r | |
| 724 | if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r | |
| 725 | SettingFreq ++;\r | |
| 726 | }\r | |
| 727 | }\r | |
| 728 | \r | |
| 729 | DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r | |
| 730 | \r | |
| 731 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);\r | |
| 732 | if (EFI_ERROR (Status)) {\r | |
| 733 | return Status;\r | |
| 734 | }\r | |
| 735 | //\r | |
| 736 | // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r | |
| 737 | //\r | |
| 738 | if ((ControllerVer & 0xFF) == 2) {\r | |
| 739 | ASSERT (Divisor <= 0x3FF);\r | |
| 740 | ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r | |
| 741 | } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r | |
| 742 | //\r | |
| 743 | // Only the most significant bit can be used as divisor.\r | |
| 744 | //\r | |
| 745 | if (((Divisor - 1) & Divisor) != 0) {\r | |
| 746 | Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r | |
| 747 | }\r | |
| 748 | ASSERT (Divisor <= 0x80);\r | |
| 749 | ClockCtrl = (Divisor & 0xFF) << 8;\r | |
| 750 | } else {\r | |
| 751 | DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r | |
| 752 | return EFI_UNSUPPORTED;\r | |
| 753 | }\r | |
| 754 | \r | |
| 755 | //\r | |
| 756 | // Stop bus clock at first\r | |
| 757 | //\r | |
| 758 | Status = SdMmcHcStopClock (PciIo, Slot);\r | |
| 759 | if (EFI_ERROR (Status)) {\r | |
| 760 | return Status;\r | |
| 761 | }\r | |
| 762 | \r | |
| 763 | //\r | |
| 764 | // Supply clock frequency with specified divisor\r | |
| 765 | //\r | |
| 766 | ClockCtrl |= BIT0;\r | |
| 767 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r | |
| 768 | if (EFI_ERROR (Status)) {\r | |
| 769 | DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r | |
| 770 | return Status;\r | |
| 771 | }\r | |
| 772 | \r | |
| 773 | //\r | |
| 774 | // Wait Internal Clock Stable in the Clock Control register to be 1\r | |
| 775 | //\r | |
| 776 | Status = SdMmcHcWaitMmioSet (\r | |
| 777 | PciIo,\r | |
| 778 | Slot,\r | |
| 779 | SD_MMC_HC_CLOCK_CTRL,\r | |
| 780 | sizeof (ClockCtrl),\r | |
| 781 | BIT1,\r | |
| 782 | BIT1,\r | |
| 783 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
| 784 | );\r | |
| 785 | if (EFI_ERROR (Status)) {\r | |
| 786 | return Status;\r | |
| 787 | }\r | |
| 788 | \r | |
| 789 | //\r | |
| 790 | // Set SD Clock Enable in the Clock Control register to 1\r | |
| 791 | //\r | |
| 792 | ClockCtrl = BIT2;\r | |
| 793 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
| 794 | \r | |
| 795 | return Status;\r | |
| 796 | }\r | |
| 797 | \r | |
| 798 | /**\r | |
| 799 | SD/MMC bus power control.\r | |
| 800 | \r | |
| 801 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
| 802 | \r | |
| 803 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 804 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 805 | @param[in] PowerCtrl The value setting to the power control register.\r | |
| 806 | \r | |
| 807 | @retval TRUE There is a SD/MMC card attached.\r | |
| 808 | @retval FALSE There is no a SD/MMC card attached.\r | |
| 809 | \r | |
| 810 | **/\r | |
| 811 | EFI_STATUS\r | |
| 812 | SdMmcHcPowerControl (\r | |
| 813 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 814 | IN UINT8 Slot,\r | |
| 815 | IN UINT8 PowerCtrl\r | |
| 816 | )\r | |
| 817 | {\r | |
| 818 | EFI_STATUS Status;\r | |
| 819 | \r | |
| 820 | //\r | |
| 821 | // Clr SD Bus Power\r | |
| 822 | //\r | |
| 823 | PowerCtrl &= (UINT8)~BIT0;\r | |
| 824 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
| 825 | if (EFI_ERROR (Status)) {\r | |
| 826 | return Status;\r | |
| 827 | }\r | |
| 828 | \r | |
| 829 | //\r | |
| 830 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
| 831 | //\r | |
| 832 | PowerCtrl |= BIT0;\r | |
| 833 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
| 834 | \r | |
| 835 | return Status;\r | |
| 836 | }\r | |
| 837 | \r | |
| 838 | /**\r | |
| 839 | Set the SD/MMC bus width.\r | |
| 840 | \r | |
| 841 | Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r | |
| 842 | \r | |
| 843 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 844 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 845 | @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r | |
| 846 | \r | |
| 847 | @retval EFI_SUCCESS The bus width is set successfully.\r | |
| 848 | @retval Others The bus width isn't set successfully.\r | |
| 849 | \r | |
| 850 | **/\r | |
| 851 | EFI_STATUS\r | |
| 852 | SdMmcHcSetBusWidth (\r | |
| 853 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 854 | IN UINT8 Slot,\r | |
| 855 | IN UINT16 BusWidth\r | |
| 856 | )\r | |
| 857 | {\r | |
| 858 | EFI_STATUS Status;\r | |
| 859 | UINT8 HostCtrl1;\r | |
| 860 | \r | |
| 861 | if (BusWidth == 1) {\r | |
| 862 | HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r | |
| 863 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 864 | } else if (BusWidth == 4) {\r | |
| 865 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 866 | if (EFI_ERROR (Status)) {\r | |
| 867 | return Status;\r | |
| 868 | }\r | |
| 869 | HostCtrl1 |= BIT1;\r | |
| 870 | HostCtrl1 &= (UINT8)~BIT5;\r | |
| 871 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 872 | } else if (BusWidth == 8) {\r | |
| 873 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 874 | if (EFI_ERROR (Status)) {\r | |
| 875 | return Status;\r | |
| 876 | }\r | |
| 877 | HostCtrl1 &= (UINT8)~BIT1;\r | |
| 878 | HostCtrl1 |= BIT5;\r | |
| 879 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 880 | } else {\r | |
| 881 | ASSERT (FALSE);\r | |
| 882 | return EFI_INVALID_PARAMETER;\r | |
| 883 | }\r | |
| 884 | \r | |
| 885 | return Status;\r | |
| 886 | }\r | |
| 887 | \r | |
| 888 | /**\r | |
| 889 | Supply SD/MMC card with lowest clock frequency at initialization.\r | |
| 890 | \r | |
| 891 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 892 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 893 | @param[in] Capability The capability of the slot.\r | |
| 894 | \r | |
| 895 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
| 896 | @retval Others The clock isn't supplied successfully.\r | |
| 897 | \r | |
| 898 | **/\r | |
| 899 | EFI_STATUS\r | |
| 900 | SdMmcHcInitClockFreq (\r | |
| 901 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 902 | IN UINT8 Slot,\r | |
| 903 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
| 904 | )\r | |
| 905 | {\r | |
| 906 | EFI_STATUS Status;\r | |
| 907 | UINT32 InitFreq;\r | |
| 908 | \r | |
| 909 | //\r | |
| 910 | // Calculate a divisor for SD clock frequency\r | |
| 911 | //\r | |
| 912 | if (Capability.BaseClkFreq == 0) {\r | |
| 913 | //\r | |
| 914 | // Don't support get Base Clock Frequency information via another method\r | |
| 915 | //\r | |
| 916 | return EFI_UNSUPPORTED;\r | |
| 917 | }\r | |
| 918 | //\r | |
| 919 | // Supply 400KHz clock frequency at initialization phase.\r | |
| 920 | //\r | |
| 921 | InitFreq = 400;\r | |
| 922 | Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);\r | |
| 923 | return Status;\r | |
| 924 | }\r | |
| 925 | \r | |
| 926 | /**\r | |
| 927 | Supply SD/MMC card with maximum voltage at initialization.\r | |
| 928 | \r | |
| 929 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
| 930 | \r | |
| 931 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 932 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 933 | @param[in] Capability The capability of the slot.\r | |
| 934 | \r | |
| 935 | @retval EFI_SUCCESS The voltage is supplied successfully.\r | |
| 936 | @retval Others The voltage isn't supplied successfully.\r | |
| 937 | \r | |
| 938 | **/\r | |
| 939 | EFI_STATUS\r | |
| 940 | SdMmcHcInitPowerVoltage (\r | |
| 941 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 942 | IN UINT8 Slot,\r | |
| 943 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
| 944 | )\r | |
| 945 | {\r | |
| 946 | EFI_STATUS Status;\r | |
| 947 | UINT8 MaxVoltage;\r | |
| 948 | UINT8 HostCtrl2;\r | |
| 949 | \r | |
| 950 | //\r | |
| 951 | // Calculate supported maximum voltage according to SD Bus Voltage Select\r | |
| 952 | //\r | |
| 953 | if (Capability.Voltage33 != 0) {\r | |
| 954 | //\r | |
| 955 | // Support 3.3V\r | |
| 956 | //\r | |
| 957 | MaxVoltage = 0x0E;\r | |
| 958 | } else if (Capability.Voltage30 != 0) {\r | |
| 959 | //\r | |
| 960 | // Support 3.0V\r | |
| 961 | //\r | |
| 962 | MaxVoltage = 0x0C;\r | |
| 963 | } else if (Capability.Voltage18 != 0) {\r | |
| 964 | //\r | |
| 965 | // Support 1.8V\r | |
| 966 | //\r | |
| 967 | MaxVoltage = 0x0A;\r | |
| 968 | HostCtrl2 = BIT3;\r | |
| 969 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
| 970 | gBS->Stall (5000);\r | |
| 971 | if (EFI_ERROR (Status)) {\r | |
| 972 | return Status;\r | |
| 973 | }\r | |
| 974 | } else {\r | |
| 975 | ASSERT (FALSE);\r | |
| 976 | return EFI_DEVICE_ERROR;\r | |
| 977 | }\r | |
| 978 | \r | |
| 979 | //\r | |
| 980 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
| 981 | //\r | |
| 982 | Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);\r | |
| 983 | \r | |
| 984 | return Status;\r | |
| 985 | }\r | |
| 986 | \r | |
| 987 | /**\r | |
| 988 | Initialize the Timeout Control register with most conservative value at initialization.\r | |
| 989 | \r | |
| 990 | Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r | |
| 991 | \r | |
| 992 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 993 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 994 | \r | |
| 995 | @retval EFI_SUCCESS The timeout control register is configured successfully.\r | |
| 996 | @retval Others The timeout control register isn't configured successfully.\r | |
| 997 | \r | |
| 998 | **/\r | |
| 999 | EFI_STATUS\r | |
| 1000 | SdMmcHcInitTimeoutCtrl (\r | |
| 1001 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 1002 | IN UINT8 Slot\r | |
| 1003 | )\r | |
| 1004 | {\r | |
| 1005 | EFI_STATUS Status;\r | |
| 1006 | UINT8 Timeout;\r | |
| 1007 | \r | |
| 1008 | Timeout = 0x0E;\r | |
| 1009 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r | |
| 1010 | \r | |
| 1011 | return Status;\r | |
| 1012 | }\r | |
| 1013 | \r | |
| 1014 | /**\r | |
| 1015 | Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r | |
| 1016 | at initialization.\r | |
| 1017 | \r | |
| 1018 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 1019 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 1020 | @param[in] Capability The capability of the slot.\r | |
| 1021 | \r | |
| 1022 | @retval EFI_SUCCESS The host controller is initialized successfully.\r | |
| 1023 | @retval Others The host controller isn't initialized successfully.\r | |
| 1024 | \r | |
| 1025 | **/\r | |
| 1026 | EFI_STATUS\r | |
| 1027 | SdMmcHcInitHost (\r | |
| 1028 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 1029 | IN UINT8 Slot,\r | |
| 1030 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
| 1031 | )\r | |
| 1032 | {\r | |
| 1033 | EFI_STATUS Status;\r | |
| 1034 | \r | |
| 1035 | Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);\r | |
| 1036 | if (EFI_ERROR (Status)) {\r | |
| 1037 | return Status;\r | |
| 1038 | }\r | |
| 1039 | \r | |
| 1040 | Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);\r | |
| 1041 | if (EFI_ERROR (Status)) {\r | |
| 1042 | return Status;\r | |
| 1043 | }\r | |
| 1044 | \r | |
| 1045 | Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r | |
| 1046 | return Status;\r | |
| 1047 | }\r | |
| 1048 | \r | |
| 1049 | /**\r | |
| 1050 | Turn on/off LED.\r | |
| 1051 | \r | |
| 1052 | @param[in] PciIo The PCI IO protocol instance.\r | |
| 1053 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 1054 | @param[in] On The boolean to turn on/off LED.\r | |
| 1055 | \r | |
| 1056 | @retval EFI_SUCCESS The LED is turned on/off successfully.\r | |
| 1057 | @retval Others The LED isn't turned on/off successfully.\r | |
| 1058 | \r | |
| 1059 | **/\r | |
| 1060 | EFI_STATUS\r | |
| 1061 | SdMmcHcLedOnOff (\r | |
| 1062 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
| 1063 | IN UINT8 Slot,\r | |
| 1064 | IN BOOLEAN On\r | |
| 1065 | )\r | |
| 1066 | {\r | |
| 1067 | EFI_STATUS Status;\r | |
| 1068 | UINT8 HostCtrl1;\r | |
| 1069 | \r | |
| 1070 | if (On) {\r | |
| 1071 | HostCtrl1 = BIT0;\r | |
| 1072 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 1073 | } else {\r | |
| 1074 | HostCtrl1 = (UINT8)~BIT0;\r | |
| 1075 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 1076 | }\r | |
| 1077 | \r | |
| 1078 | return Status;\r | |
| 1079 | }\r | |
| 1080 | \r | |
| 1081 | /**\r | |
| 1082 | Build ADMA descriptor table for transfer.\r | |
| 1083 | \r | |
| 1084 | Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.\r | |
| 1085 | \r | |
| 1086 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
| 1087 | \r | |
| 1088 | @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r | |
| 1089 | @retval Others The ADMA descriptor table isn't created successfully.\r | |
| 1090 | \r | |
| 1091 | **/\r | |
| 1092 | EFI_STATUS\r | |
| 1093 | BuildAdmaDescTable (\r | |
| 1094 | IN SD_MMC_HC_TRB *Trb\r | |
| 1095 | )\r | |
| 1096 | {\r | |
| 1097 | EFI_PHYSICAL_ADDRESS Data;\r | |
| 1098 | UINT64 DataLen;\r | |
| 1099 | UINT64 Entries;\r | |
| 1100 | UINT32 Index;\r | |
| 1101 | UINT64 Remaining;\r | |
| 1102 | UINT32 Address;\r | |
| 1103 | UINTN TableSize;\r | |
| 1104 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
| 1105 | EFI_STATUS Status;\r | |
| 1106 | UINTN Bytes;\r | |
| 1107 | \r | |
| 1108 | Data = Trb->DataPhy;\r | |
| 1109 | DataLen = Trb->DataLen;\r | |
| 1110 | PciIo = Trb->Private->PciIo;\r | |
| 1111 | //\r | |
| 1112 | // Only support 32bit ADMA Descriptor Table\r | |
| 1113 | //\r | |
| 1114 | if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {\r | |
| 1115 | return EFI_INVALID_PARAMETER;\r | |
| 1116 | }\r | |
| 1117 | //\r | |
| 1118 | // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r | |
| 1119 | // for 32-bit address descriptor table.\r | |
| 1120 | //\r | |
| 1121 | if ((Data & (BIT0 | BIT1)) != 0) {\r | |
| 1122 | DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r | |
| 1123 | }\r | |
| 1124 | \r | |
| 1125 | Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);\r | |
| 1126 | TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));\r | |
| 1127 | Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r | |
| 1128 | Status = PciIo->AllocateBuffer (\r | |
| 1129 | PciIo,\r | |
| 1130 | AllocateAnyPages,\r | |
| 1131 | EfiBootServicesData,\r | |
| 1132 | EFI_SIZE_TO_PAGES (TableSize),\r | |
| 1133 | (VOID **)&Trb->AdmaDesc,\r | |
| 1134 | 0\r | |
| 1135 | );\r | |
| 1136 | if (EFI_ERROR (Status)) {\r | |
| 1137 | return EFI_OUT_OF_RESOURCES;\r | |
| 1138 | }\r | |
| 1139 | ZeroMem (Trb->AdmaDesc, TableSize);\r | |
| 1140 | Bytes = TableSize;\r | |
| 1141 | Status = PciIo->Map (\r | |
| 1142 | PciIo,\r | |
| 1143 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
| 1144 | Trb->AdmaDesc,\r | |
| 1145 | &Bytes,\r | |
| 1146 | &Trb->AdmaDescPhy,\r | |
| 1147 | &Trb->AdmaMap\r | |
| 1148 | );\r | |
| 1149 | \r | |
| 1150 | if (EFI_ERROR (Status) || (Bytes != TableSize)) {\r | |
| 1151 | //\r | |
| 1152 | // Map error or unable to map the whole RFis buffer into a contiguous region.\r | |
| 1153 | //\r | |
| 1154 | PciIo->FreeBuffer (\r | |
| 1155 | PciIo,\r | |
| 1156 | EFI_SIZE_TO_PAGES (TableSize),\r | |
| 1157 | Trb->AdmaDesc\r | |
| 1158 | );\r | |
| 1159 | return EFI_OUT_OF_RESOURCES;\r | |
| 1160 | }\r | |
| 1161 | \r | |
| 1162 | if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r | |
| 1163 | //\r | |
| 1164 | // The ADMA doesn't support 64bit addressing.\r | |
| 1165 | //\r | |
| 1166 | PciIo->Unmap (\r | |
| 1167 | PciIo,\r | |
| 1168 | Trb->AdmaMap\r | |
| 1169 | );\r | |
| 1170 | PciIo->FreeBuffer (\r | |
| 1171 | PciIo,\r | |
| 1172 | EFI_SIZE_TO_PAGES (TableSize),\r | |
| 1173 | Trb->AdmaDesc\r | |
| 1174 | );\r | |
| 1175 | return EFI_DEVICE_ERROR;\r | |
| 1176 | }\r | |
| 1177 | \r | |
| 1178 | Remaining = DataLen;\r | |
| 1179 | Address = (UINT32)Data;\r | |
| 1180 | for (Index = 0; Index < Entries; Index++) {\r | |
| 1181 | if (Remaining <= ADMA_MAX_DATA_PER_LINE) {\r | |
| 1182 | Trb->AdmaDesc[Index].Valid = 1;\r | |
| 1183 | Trb->AdmaDesc[Index].Act = 2;\r | |
| 1184 | Trb->AdmaDesc[Index].Length = (UINT16)Remaining;\r | |
| 1185 | Trb->AdmaDesc[Index].Address = Address;\r | |
| 1186 | break;\r | |
| 1187 | } else {\r | |
| 1188 | Trb->AdmaDesc[Index].Valid = 1;\r | |
| 1189 | Trb->AdmaDesc[Index].Act = 2;\r | |
| 1190 | Trb->AdmaDesc[Index].Length = 0;\r | |
| 1191 | Trb->AdmaDesc[Index].Address = Address;\r | |
| 1192 | }\r | |
| 1193 | \r | |
| 1194 | Remaining -= ADMA_MAX_DATA_PER_LINE;\r | |
| 1195 | Address += ADMA_MAX_DATA_PER_LINE;\r | |
| 1196 | }\r | |
| 1197 | \r | |
| 1198 | //\r | |
| 1199 | // Set the last descriptor line as end of descriptor table\r | |
| 1200 | //\r | |
| 1201 | Trb->AdmaDesc[Index].End = 1;\r | |
| 1202 | return EFI_SUCCESS;\r | |
| 1203 | }\r | |
| 1204 | \r | |
| 1205 | /**\r | |
| 1206 | Create a new TRB for the SD/MMC cmd request.\r | |
| 1207 | \r | |
| 1208 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
| 1209 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
| 1210 | @param[in] Packet A pointer to the SD command data structure.\r | |
| 1211 | @param[in] Event If Event is NULL, blocking I/O is performed. If Event is\r | |
| 1212 | not NULL, then nonblocking I/O is performed, and Event\r | |
| 1213 | will be signaled when the Packet completes.\r | |
| 1214 | \r | |
| 1215 | @return Created Trb or NULL.\r | |
| 1216 | \r | |
| 1217 | **/\r | |
| 1218 | SD_MMC_HC_TRB *\r | |
| 1219 | SdMmcCreateTrb (\r | |
| 1220 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
| 1221 | IN UINT8 Slot,\r | |
| 1222 | IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r | |
| 1223 | IN EFI_EVENT Event\r | |
| 1224 | )\r | |
| 1225 | {\r | |
| 1226 | SD_MMC_HC_TRB *Trb;\r | |
| 1227 | EFI_STATUS Status;\r | |
| 1228 | EFI_TPL OldTpl;\r | |
| 1229 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r | |
| 1230 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
| 1231 | UINTN MapLength;\r | |
| 1232 | \r | |
| 1233 | Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));\r | |
| 1234 | if (Trb == NULL) {\r | |
| 1235 | return NULL;\r | |
| 1236 | }\r | |
| 1237 | \r | |
| 1238 | Trb->Signature = SD_MMC_HC_TRB_SIG;\r | |
| 1239 | Trb->Slot = Slot;\r | |
| 1240 | Trb->BlockSize = 0x200;\r | |
| 1241 | Trb->Packet = Packet;\r | |
| 1242 | Trb->Event = Event;\r | |
| 1243 | Trb->Started = FALSE;\r | |
| 1244 | Trb->Timeout = Packet->Timeout;\r | |
| 1245 | Trb->Private = Private;\r | |
| 1246 | \r | |
| 1247 | if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r | |
| 1248 | Trb->Data = Packet->InDataBuffer;\r | |
| 1249 | Trb->DataLen = Packet->InTransferLength;\r | |
| 1250 | Trb->Read = TRUE;\r | |
| 1251 | } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r | |
| 1252 | Trb->Data = Packet->OutDataBuffer;\r | |
| 1253 | Trb->DataLen = Packet->OutTransferLength;\r | |
| 1254 | Trb->Read = FALSE;\r | |
| 1255 | } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r | |
| 1256 | Trb->Data = NULL;\r | |
| 1257 | Trb->DataLen = 0;\r | |
| 1258 | } else {\r | |
| 1259 | goto Error;\r | |
| 1260 | }\r | |
| 1261 | \r | |
| 1262 | if (Trb->Read) {\r | |
| 1263 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
| 1264 | } else {\r | |
| 1265 | Flag = EfiPciIoOperationBusMasterRead;\r | |
| 1266 | }\r | |
| 1267 | \r | |
| 1268 | PciIo = Private->PciIo;\r | |
| 1269 | if (Trb->DataLen != 0) {\r | |
| 1270 | MapLength = Trb->DataLen;\r | |
| 1271 | Status = PciIo->Map (\r | |
| 1272 | PciIo,\r | |
| 1273 | Flag,\r | |
| 1274 | Trb->Data,\r | |
| 1275 | &MapLength,\r | |
| 1276 | &Trb->DataPhy,\r | |
| 1277 | &Trb->DataMap\r | |
| 1278 | );\r | |
| 1279 | if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {\r | |
| 1280 | Status = EFI_BAD_BUFFER_SIZE;\r | |
| 1281 | goto Error;\r | |
| 1282 | }\r | |
| 1283 | }\r | |
| 1284 | \r | |
| 1285 | if ((Trb->DataLen % Trb->BlockSize) != 0) {\r | |
| 1286 | if (Trb->DataLen < Trb->BlockSize) {\r | |
| 1287 | Trb->BlockSize = (UINT16)Trb->DataLen;\r | |
| 1288 | }\r | |
| 1289 | }\r | |
| 1290 | \r | |
| 1291 | if (Trb->DataLen == 0) {\r | |
| 1292 | Trb->Mode = SdMmcNoData;\r | |
| 1293 | } else if (Private->Capability[Slot].Adma2 != 0) {\r | |
| 1294 | Trb->Mode = SdMmcAdmaMode;\r | |
| 1295 | Status = BuildAdmaDescTable (Trb);\r | |
| 1296 | if (EFI_ERROR (Status)) {\r | |
| 1297 | PciIo->Unmap (PciIo, Trb->DataMap);\r | |
| 1298 | goto Error;\r | |
| 1299 | }\r | |
| 1300 | } else if (Private->Capability[Slot].Sdma != 0) {\r | |
| 1301 | Trb->Mode = SdMmcSdmaMode;\r | |
| 1302 | } else {\r | |
| 1303 | Trb->Mode = SdMmcPioMode;\r | |
| 1304 | }\r | |
| 1305 | \r | |
| 1306 | if (Event != NULL) {\r | |
| 1307 | OldTpl = gBS->RaiseTPL (TPL_CALLBACK);\r | |
| 1308 | InsertTailList (&Private->Queue, &Trb->TrbList);\r | |
| 1309 | gBS->RestoreTPL (OldTpl);\r | |
| 1310 | }\r | |
| 1311 | \r | |
| 1312 | return Trb;\r | |
| 1313 | \r | |
| 1314 | Error:\r | |
| 1315 | SdMmcFreeTrb (Trb);\r | |
| 1316 | return NULL;\r | |
| 1317 | }\r | |
| 1318 | \r | |
| 1319 | /**\r | |
| 1320 | Free the resource used by the TRB.\r | |
| 1321 | \r | |
| 1322 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
| 1323 | \r | |
| 1324 | **/\r | |
| 1325 | VOID\r | |
| 1326 | SdMmcFreeTrb (\r | |
| 1327 | IN SD_MMC_HC_TRB *Trb\r | |
| 1328 | )\r | |
| 1329 | {\r | |
| 1330 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
| 1331 | \r | |
| 1332 | PciIo = Trb->Private->PciIo;\r | |
| 1333 | \r | |
| 1334 | if (Trb->AdmaMap != NULL) {\r | |
| 1335 | PciIo->Unmap (\r | |
| 1336 | PciIo,\r | |
| 1337 | Trb->AdmaMap\r | |
| 1338 | );\r | |
| 1339 | }\r | |
| 1340 | if (Trb->AdmaDesc != NULL) {\r | |
| 1341 | PciIo->FreeBuffer (\r | |
| 1342 | PciIo,\r | |
| 1343 | Trb->AdmaPages,\r | |
| 1344 | Trb->AdmaDesc\r | |
| 1345 | );\r | |
| 1346 | }\r | |
| 1347 | if (Trb->DataMap != NULL) {\r | |
| 1348 | PciIo->Unmap (\r | |
| 1349 | PciIo,\r | |
| 1350 | Trb->DataMap\r | |
| 1351 | );\r | |
| 1352 | }\r | |
| 1353 | FreePool (Trb);\r | |
| 1354 | return;\r | |
| 1355 | }\r | |
| 1356 | \r | |
| 1357 | /**\r | |
| 1358 | Check if the env is ready for execute specified TRB.\r | |
| 1359 | \r | |
| 1360 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
| 1361 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
| 1362 | \r | |
| 1363 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
| 1364 | @retval EFI_NOT_READY The env is not ready for TRB execution.\r | |
| 1365 | @retval Others Some erros happen.\r | |
| 1366 | \r | |
| 1367 | **/\r | |
| 1368 | EFI_STATUS\r | |
| 1369 | SdMmcCheckTrbEnv (\r | |
| 1370 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
| 1371 | IN SD_MMC_HC_TRB *Trb\r | |
| 1372 | )\r | |
| 1373 | {\r | |
| 1374 | EFI_STATUS Status;\r | |
| 1375 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
| 1376 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
| 1377 | UINT32 PresentState;\r | |
| 1378 | \r | |
| 1379 | Packet = Trb->Packet;\r | |
| 1380 | \r | |
| 1381 | if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r | |
| 1382 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r | |
| 1383 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {\r | |
| 1384 | //\r | |
| 1385 | // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r | |
| 1386 | // the Present State register to be 0\r | |
| 1387 | //\r | |
| 1388 | PresentState = BIT0 | BIT1;\r | |
| 1389 | //\r | |
| 1390 | // For Send Tuning Block cmd, just wait for Command Inhibit (CMD) to be 0\r | |
| 1391 | //\r | |
| 1392 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
| 1393 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
| 1394 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
| 1395 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
| 1396 | PresentState = BIT0;\r | |
| 1397 | }\r | |
| 1398 | } else {\r | |
| 1399 | //\r | |
| 1400 | // Wait Command Inhibit (CMD) in the Present State register\r | |
| 1401 | // to be 0\r | |
| 1402 | //\r | |
| 1403 | PresentState = BIT0;\r | |
| 1404 | }\r | |
| 1405 | \r | |
| 1406 | PciIo = Private->PciIo;\r | |
| 1407 | Status = SdMmcHcCheckMmioSet (\r | |
| 1408 | PciIo,\r | |
| 1409 | Trb->Slot,\r | |
| 1410 | SD_MMC_HC_PRESENT_STATE,\r | |
| 1411 | sizeof (PresentState),\r | |
| 1412 | PresentState,\r | |
| 1413 | 0\r | |
| 1414 | );\r | |
| 1415 | \r | |
| 1416 | return Status;\r | |
| 1417 | }\r | |
| 1418 | \r | |
| 1419 | /**\r | |
| 1420 | Wait for the env to be ready for execute specified TRB.\r | |
| 1421 | \r | |
| 1422 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
| 1423 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
| 1424 | \r | |
| 1425 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
| 1426 | @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r | |
| 1427 | @retval Others Some erros happen.\r | |
| 1428 | \r | |
| 1429 | **/\r | |
| 1430 | EFI_STATUS\r | |
| 1431 | SdMmcWaitTrbEnv (\r | |
| 1432 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
| 1433 | IN SD_MMC_HC_TRB *Trb\r | |
| 1434 | )\r | |
| 1435 | {\r | |
| 1436 | EFI_STATUS Status;\r | |
| 1437 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
| 1438 | UINT64 Timeout;\r | |
| 1439 | BOOLEAN InfiniteWait;\r | |
| 1440 | \r | |
| 1441 | //\r | |
| 1442 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
| 1443 | //\r | |
| 1444 | Packet = Trb->Packet;\r | |
| 1445 | Timeout = Packet->Timeout;\r | |
| 1446 | if (Timeout == 0) {\r | |
| 1447 | InfiniteWait = TRUE;\r | |
| 1448 | } else {\r | |
| 1449 | InfiniteWait = FALSE;\r | |
| 1450 | }\r | |
| 1451 | \r | |
| 1452 | while (InfiniteWait || (Timeout > 0)) {\r | |
| 1453 | //\r | |
| 1454 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
| 1455 | //\r | |
| 1456 | Status = SdMmcCheckTrbEnv (Private, Trb);\r | |
| 1457 | if (Status != EFI_NOT_READY) {\r | |
| 1458 | return Status;\r | |
| 1459 | }\r | |
| 1460 | //\r | |
| 1461 | // Stall for 1 microsecond.\r | |
| 1462 | //\r | |
| 1463 | gBS->Stall (1);\r | |
| 1464 | \r | |
| 1465 | Timeout--;\r | |
| 1466 | }\r | |
| 1467 | \r | |
| 1468 | return EFI_TIMEOUT;\r | |
| 1469 | }\r | |
| 1470 | \r | |
| 1471 | /**\r | |
| 1472 | Execute the specified TRB.\r | |
| 1473 | \r | |
| 1474 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
| 1475 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
| 1476 | \r | |
| 1477 | @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r | |
| 1478 | @retval Others Some erros happen when sending this request to the host controller.\r | |
| 1479 | \r | |
| 1480 | **/\r | |
| 1481 | EFI_STATUS\r | |
| 1482 | SdMmcExecTrb (\r | |
| 1483 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
| 1484 | IN SD_MMC_HC_TRB *Trb\r | |
| 1485 | )\r | |
| 1486 | {\r | |
| 1487 | EFI_STATUS Status;\r | |
| 1488 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
| 1489 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
| 1490 | UINT16 Cmd;\r | |
| 1491 | UINT16 IntStatus;\r | |
| 1492 | UINT32 Argument;\r | |
| 1493 | UINT16 BlkCount;\r | |
| 1494 | UINT16 BlkSize;\r | |
| 1495 | UINT16 TransMode;\r | |
| 1496 | UINT8 HostCtrl1;\r | |
| 1497 | UINT32 SdmaAddr;\r | |
| 1498 | UINT64 AdmaAddr;\r | |
| 1499 | \r | |
| 1500 | Packet = Trb->Packet;\r | |
| 1501 | PciIo = Trb->Private->PciIo;\r | |
| 1502 | //\r | |
| 1503 | // Clear all bits in Error Interrupt Status Register\r | |
| 1504 | //\r | |
| 1505 | IntStatus = 0xFFFF;\r | |
| 1506 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
| 1507 | if (EFI_ERROR (Status)) {\r | |
| 1508 | return Status;\r | |
| 1509 | }\r | |
| 1510 | //\r | |
| 1511 | // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.\r | |
| 1512 | //\r | |
| 1513 | IntStatus = 0xFF3F;\r | |
| 1514 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
| 1515 | if (EFI_ERROR (Status)) {\r | |
| 1516 | return Status;\r | |
| 1517 | }\r | |
| 1518 | //\r | |
| 1519 | // Set Host Control 1 register DMA Select field\r | |
| 1520 | //\r | |
| 1521 | if (Trb->Mode == SdMmcAdmaMode) {\r | |
| 1522 | HostCtrl1 = BIT4;\r | |
| 1523 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
| 1524 | if (EFI_ERROR (Status)) {\r | |
| 1525 | return Status;\r | |
| 1526 | }\r | |
| 1527 | }\r | |
| 1528 | \r | |
| 1529 | SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r | |
| 1530 | \r | |
| 1531 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
| 1532 | if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {\r | |
| 1533 | return EFI_INVALID_PARAMETER;\r | |
| 1534 | }\r | |
| 1535 | \r | |
| 1536 | SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;\r | |
| 1537 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);\r | |
| 1538 | if (EFI_ERROR (Status)) {\r | |
| 1539 | return Status;\r | |
| 1540 | }\r | |
| 1541 | } else if (Trb->Mode == SdMmcAdmaMode) {\r | |
| 1542 | AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;\r | |
| 1543 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r | |
| 1544 | if (EFI_ERROR (Status)) {\r | |
| 1545 | return Status;\r | |
| 1546 | }\r | |
| 1547 | }\r | |
| 1548 | \r | |
| 1549 | BlkSize = Trb->BlockSize;\r | |
| 1550 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
| 1551 | //\r | |
| 1552 | // Set SDMA boundary to be 512K bytes.\r | |
| 1553 | //\r | |
| 1554 | BlkSize |= 0x7000;\r | |
| 1555 | }\r | |
| 1556 | \r | |
| 1557 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r | |
| 1558 | if (EFI_ERROR (Status)) {\r | |
| 1559 | return Status;\r | |
| 1560 | }\r | |
| 1561 | \r | |
| 1562 | BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);\r | |
| 1563 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r | |
| 1564 | if (EFI_ERROR (Status)) {\r | |
| 1565 | return Status;\r | |
| 1566 | }\r | |
| 1567 | \r | |
| 1568 | Argument = Packet->SdMmcCmdBlk->CommandArgument;\r | |
| 1569 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r | |
| 1570 | if (EFI_ERROR (Status)) {\r | |
| 1571 | return Status;\r | |
| 1572 | }\r | |
| 1573 | \r | |
| 1574 | TransMode = 0;\r | |
| 1575 | if (Trb->Mode != SdMmcNoData) {\r | |
| 1576 | if (Trb->Mode != SdMmcPioMode) {\r | |
| 1577 | TransMode |= BIT0;\r | |
| 1578 | }\r | |
| 1579 | if (Trb->Read) {\r | |
| 1580 | TransMode |= BIT4;\r | |
| 1581 | }\r | |
| 1582 | if (BlkCount != 0) {\r | |
| 1583 | TransMode |= BIT5 | BIT1;\r | |
| 1584 | }\r | |
| 1585 | //\r | |
| 1586 | // Only SD memory card needs to use AUTO CMD12 feature.\r | |
| 1587 | //\r | |
| 1588 | if (Private->Slot[Trb->Slot].CardType == SdCardType) {\r | |
| 1589 | if (BlkCount > 1) {\r | |
| 1590 | TransMode |= BIT2;\r | |
| 1591 | }\r | |
| 1592 | }\r | |
| 1593 | }\r | |
| 1594 | \r | |
| 1595 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r | |
| 1596 | if (EFI_ERROR (Status)) {\r | |
| 1597 | return Status;\r | |
| 1598 | }\r | |
| 1599 | \r | |
| 1600 | Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);\r | |
| 1601 | if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {\r | |
| 1602 | Cmd |= BIT5;\r | |
| 1603 | }\r | |
| 1604 | //\r | |
| 1605 | // Convert ResponseType to value\r | |
| 1606 | //\r | |
| 1607 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
| 1608 | switch (Packet->SdMmcCmdBlk->ResponseType) {\r | |
| 1609 | case SdMmcResponseTypeR1:\r | |
| 1610 | case SdMmcResponseTypeR5:\r | |
| 1611 | case SdMmcResponseTypeR6:\r | |
| 1612 | case SdMmcResponseTypeR7:\r | |
| 1613 | Cmd |= (BIT1 | BIT3 | BIT4);\r | |
| 1614 | break;\r | |
| 1615 | case SdMmcResponseTypeR2:\r | |
| 1616 | Cmd |= (BIT0 | BIT3);\r | |
| 1617 | break;\r | |
| 1618 | case SdMmcResponseTypeR3:\r | |
| 1619 | case SdMmcResponseTypeR4:\r | |
| 1620 | Cmd |= BIT1;\r | |
| 1621 | break;\r | |
| 1622 | case SdMmcResponseTypeR1b:\r | |
| 1623 | case SdMmcResponseTypeR5b:\r | |
| 1624 | Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r | |
| 1625 | break;\r | |
| 1626 | default:\r | |
| 1627 | ASSERT (FALSE);\r | |
| 1628 | break;\r | |
| 1629 | }\r | |
| 1630 | }\r | |
| 1631 | //\r | |
| 1632 | // Execute cmd\r | |
| 1633 | //\r | |
| 1634 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r | |
| 1635 | return Status;\r | |
| 1636 | }\r | |
| 1637 | \r | |
| 1638 | /**\r | |
| 1639 | Check the TRB execution result.\r | |
| 1640 | \r | |
| 1641 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
| 1642 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
| 1643 | \r | |
| 1644 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
| 1645 | @retval EFI_NOT_READY The TRB is not completed for execution.\r | |
| 1646 | @retval Others Some erros happen when executing this request.\r | |
| 1647 | \r | |
| 1648 | **/\r | |
| 1649 | EFI_STATUS\r | |
| 1650 | SdMmcCheckTrbResult (\r | |
| 1651 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
| 1652 | IN SD_MMC_HC_TRB *Trb\r | |
| 1653 | )\r | |
| 1654 | {\r | |
| 1655 | EFI_STATUS Status;\r | |
| 1656 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
| 1657 | UINT16 IntStatus;\r | |
| 1658 | UINT32 Response[4];\r | |
| 1659 | UINT32 SdmaAddr;\r | |
| 1660 | UINT8 Index;\r | |
| 1661 | UINT8 SwReset;\r | |
| 1662 | \r | |
| 1663 | SwReset = 0;\r | |
| 1664 | Packet = Trb->Packet;\r | |
| 1665 | //\r | |
| 1666 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
| 1667 | //\r | |
| 1668 | Status = SdMmcHcRwMmio (\r | |
| 1669 | Private->PciIo,\r | |
| 1670 | Trb->Slot,\r | |
| 1671 | SD_MMC_HC_NOR_INT_STS,\r | |
| 1672 | TRUE,\r | |
| 1673 | sizeof (IntStatus),\r | |
| 1674 | &IntStatus\r | |
| 1675 | );\r | |
| 1676 | if (EFI_ERROR (Status)) {\r | |
| 1677 | goto Done;\r | |
| 1678 | }\r | |
| 1679 | //\r | |
| 1680 | // Check Transfer Complete bit is set or not.\r | |
| 1681 | //\r | |
| 1682 | if ((IntStatus & BIT1) == BIT1) {\r | |
| 1683 | if ((IntStatus & BIT15) == BIT15) {\r | |
| 1684 | //\r | |
| 1685 | // Read Error Interrupt Status register to check if the error is\r | |
| 1686 | // Data Timeout Error.\r | |
| 1687 | // If yes, treat it as success as Transfer Complete has higher\r | |
| 1688 | // priority than Data Timeout Error.\r | |
| 1689 | //\r | |
| 1690 | Status = SdMmcHcRwMmio (\r | |
| 1691 | Private->PciIo,\r | |
| 1692 | Trb->Slot,\r | |
| 1693 | SD_MMC_HC_ERR_INT_STS,\r | |
| 1694 | TRUE,\r | |
| 1695 | sizeof (IntStatus),\r | |
| 1696 | &IntStatus\r | |
| 1697 | );\r | |
| 1698 | if (!EFI_ERROR (Status)) {\r | |
| 1699 | if ((IntStatus & BIT4) == BIT4) {\r | |
| 1700 | Status = EFI_SUCCESS;\r | |
| 1701 | } else {\r | |
| 1702 | Status = EFI_DEVICE_ERROR;\r | |
| 1703 | }\r | |
| 1704 | }\r | |
| 1705 | }\r | |
| 1706 | \r | |
| 1707 | goto Done;\r | |
| 1708 | }\r | |
| 1709 | //\r | |
| 1710 | // Check if there is a error happened during cmd execution.\r | |
| 1711 | // If yes, then do error recovery procedure to follow SD Host Controller\r | |
| 1712 | // Simplified Spec 3.0 section 3.10.1.\r | |
| 1713 | //\r | |
| 1714 | if ((IntStatus & BIT15) == BIT15) {\r | |
| 1715 | Status = SdMmcHcRwMmio (\r | |
| 1716 | Private->PciIo,\r | |
| 1717 | Trb->Slot,\r | |
| 1718 | SD_MMC_HC_ERR_INT_STS,\r | |
| 1719 | TRUE,\r | |
| 1720 | sizeof (IntStatus),\r | |
| 1721 | &IntStatus\r | |
| 1722 | );\r | |
| 1723 | if (EFI_ERROR (Status)) {\r | |
| 1724 | goto Done;\r | |
| 1725 | }\r | |
| 1726 | if ((IntStatus & 0x0F) != 0) {\r | |
| 1727 | SwReset |= BIT1;\r | |
| 1728 | }\r | |
| 1729 | if ((IntStatus & 0xF0) != 0) {\r | |
| 1730 | SwReset |= BIT2;\r | |
| 1731 | }\r | |
| 1732 | \r | |
| 1733 | Status = SdMmcHcRwMmio (\r | |
| 1734 | Private->PciIo,\r | |
| 1735 | Trb->Slot,\r | |
| 1736 | SD_MMC_HC_SW_RST,\r | |
| 1737 | FALSE,\r | |
| 1738 | sizeof (SwReset),\r | |
| 1739 | &SwReset\r | |
| 1740 | );\r | |
| 1741 | if (EFI_ERROR (Status)) {\r | |
| 1742 | goto Done;\r | |
| 1743 | }\r | |
| 1744 | Status = SdMmcHcWaitMmioSet (\r | |
| 1745 | Private->PciIo,\r | |
| 1746 | Trb->Slot,\r | |
| 1747 | SD_MMC_HC_SW_RST,\r | |
| 1748 | sizeof (SwReset),\r | |
| 1749 | 0xFF,\r | |
| 1750 | 0,\r | |
| 1751 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
| 1752 | );\r | |
| 1753 | if (EFI_ERROR (Status)) {\r | |
| 1754 | goto Done;\r | |
| 1755 | }\r | |
| 1756 | \r | |
| 1757 | Status = EFI_DEVICE_ERROR;\r | |
| 1758 | goto Done;\r | |
| 1759 | }\r | |
| 1760 | //\r | |
| 1761 | // Check if DMA interrupt is signalled for the SDMA transfer.\r | |
| 1762 | //\r | |
| 1763 | if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r | |
| 1764 | //\r | |
| 1765 | // Clear DMA interrupt bit.\r | |
| 1766 | //\r | |
| 1767 | IntStatus = BIT3;\r | |
| 1768 | Status = SdMmcHcRwMmio (\r | |
| 1769 | Private->PciIo,\r | |
| 1770 | Trb->Slot,\r | |
| 1771 | SD_MMC_HC_NOR_INT_STS,\r | |
| 1772 | FALSE,\r | |
| 1773 | sizeof (IntStatus),\r | |
| 1774 | &IntStatus\r | |
| 1775 | );\r | |
| 1776 | if (EFI_ERROR (Status)) {\r | |
| 1777 | goto Done;\r | |
| 1778 | }\r | |
| 1779 | //\r | |
| 1780 | // Update SDMA Address register.\r | |
| 1781 | //\r | |
| 1782 | SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r | |
| 1783 | Status = SdMmcHcRwMmio (\r | |
| 1784 | Private->PciIo,\r | |
| 1785 | Trb->Slot,\r | |
| 1786 | SD_MMC_HC_SDMA_ADDR,\r | |
| 1787 | FALSE,\r | |
| 1788 | sizeof (UINT32),\r | |
| 1789 | &SdmaAddr\r | |
| 1790 | );\r | |
| 1791 | if (EFI_ERROR (Status)) {\r | |
| 1792 | goto Done;\r | |
| 1793 | }\r | |
| 1794 | Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;\r | |
| 1795 | }\r | |
| 1796 | \r | |
| 1797 | if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&\r | |
| 1798 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&\r | |
| 1799 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {\r | |
| 1800 | if ((IntStatus & BIT0) == BIT0) {\r | |
| 1801 | Status = EFI_SUCCESS;\r | |
| 1802 | goto Done;\r | |
| 1803 | }\r | |
| 1804 | }\r | |
| 1805 | \r | |
| 1806 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
| 1807 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
| 1808 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
| 1809 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
| 1810 | //\r | |
| 1811 | // While performing tuning procedure (Execute Tuning is set to 1),\r | |
| 1812 | // Transfer Completeis not set to 1\r | |
| 1813 | // Refer to SD Host Controller Simplified Specification 3.0 table 2-23 for details.\r | |
| 1814 | //\r | |
| 1815 | Status = EFI_SUCCESS;\r | |
| 1816 | goto Done;\r | |
| 1817 | }\r | |
| 1818 | \r | |
| 1819 | Status = EFI_NOT_READY;\r | |
| 1820 | Done:\r | |
| 1821 | //\r | |
| 1822 | // Get response data when the cmd is executed successfully.\r | |
| 1823 | //\r | |
| 1824 | if (!EFI_ERROR (Status)) {\r | |
| 1825 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
| 1826 | for (Index = 0; Index < 4; Index++) {\r | |
| 1827 | Status = SdMmcHcRwMmio (\r | |
| 1828 | Private->PciIo,\r | |
| 1829 | Trb->Slot,\r | |
| 1830 | SD_MMC_HC_RESPONSE + Index * 4,\r | |
| 1831 | TRUE,\r | |
| 1832 | sizeof (UINT32),\r | |
| 1833 | &Response[Index]\r | |
| 1834 | );\r | |
| 1835 | if (EFI_ERROR (Status)) {\r | |
| 1836 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
| 1837 | return Status;\r | |
| 1838 | }\r | |
| 1839 | }\r | |
| 1840 | CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));\r | |
| 1841 | }\r | |
| 1842 | }\r | |
| 1843 | \r | |
| 1844 | if (Status != EFI_NOT_READY) {\r | |
| 1845 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
| 1846 | }\r | |
| 1847 | \r | |
| 1848 | return Status;\r | |
| 1849 | }\r | |
| 1850 | \r | |
| 1851 | /**\r | |
| 1852 | Wait for the TRB execution result.\r | |
| 1853 | \r | |
| 1854 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
| 1855 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
| 1856 | \r | |
| 1857 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
| 1858 | @retval Others Some erros happen when executing this request.\r | |
| 1859 | \r | |
| 1860 | **/\r | |
| 1861 | EFI_STATUS\r | |
| 1862 | SdMmcWaitTrbResult (\r | |
| 1863 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
| 1864 | IN SD_MMC_HC_TRB *Trb\r | |
| 1865 | )\r | |
| 1866 | {\r | |
| 1867 | EFI_STATUS Status;\r | |
| 1868 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
| 1869 | UINT64 Timeout;\r | |
| 1870 | BOOLEAN InfiniteWait;\r | |
| 1871 | \r | |
| 1872 | Packet = Trb->Packet;\r | |
| 1873 | //\r | |
| 1874 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
| 1875 | //\r | |
| 1876 | Timeout = Packet->Timeout;\r | |
| 1877 | if (Timeout == 0) {\r | |
| 1878 | InfiniteWait = TRUE;\r | |
| 1879 | } else {\r | |
| 1880 | InfiniteWait = FALSE;\r | |
| 1881 | }\r | |
| 1882 | \r | |
| 1883 | while (InfiniteWait || (Timeout > 0)) {\r | |
| 1884 | //\r | |
| 1885 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
| 1886 | //\r | |
| 1887 | Status = SdMmcCheckTrbResult (Private, Trb);\r | |
| 1888 | if (Status != EFI_NOT_READY) {\r | |
| 1889 | return Status;\r | |
| 1890 | }\r | |
| 1891 | //\r | |
| 1892 | // Stall for 1 microsecond.\r | |
| 1893 | //\r | |
| 1894 | gBS->Stall (1);\r | |
| 1895 | \r | |
| 1896 | Timeout--;\r | |
| 1897 | }\r | |
| 1898 | \r | |
| 1899 | return EFI_TIMEOUT;\r | |
| 1900 | }\r | |
| 1901 | \r |