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48555339 FT |
1 | /** @file\r |
2 | This driver is used to manage SD/MMC PCI host controllers which are compliance\r | |
48190274 HW |
3 | with SD Host Controller Simplified Specification version 3.00 plus the 64-bit\r |
4 | System Addressing support in SD Host Controller Simplified Specification version\r | |
5 | 4.20.\r | |
48555339 FT |
6 | \r |
7 | It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r | |
8 | \r | |
690d60c0 | 9 | Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r |
4e2ac806 | 10 | Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
48555339 FT |
12 | \r |
13 | **/\r | |
14 | \r | |
15 | #include "SdMmcPciHcDxe.h"\r | |
16 | \r | |
17 | /**\r | |
18 | Dump the content of SD/MMC host controller's Capability Register.\r | |
19 | \r | |
20 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
21 | @param[in] Capability The buffer to store the capability data.\r | |
22 | \r | |
23 | **/\r | |
24 | VOID\r | |
25 | DumpCapabilityReg (\r | |
1436aea4 MK |
26 | IN UINT8 Slot,\r |
27 | IN SD_MMC_HC_SLOT_CAP *Capability\r | |
48555339 FT |
28 | )\r |
29 | {\r | |
30 | //\r | |
31 | // Dump Capability Data\r | |
32 | //\r | |
e27ccaba FT |
33 | DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));\r |
34 | DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));\r | |
35 | DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));\r | |
36 | DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));\r | |
37 | DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));\r | |
38 | DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));\r | |
39 | DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));\r | |
40 | DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));\r | |
41 | DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));\r | |
42 | DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r | |
43 | DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r | |
44 | DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r | |
b5547b9c AS |
45 | DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));\r |
46 | DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));\r | |
e27ccaba FT |
47 | DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r |
48 | DEBUG ((DEBUG_INFO, " SlotType "));\r | |
48555339 | 49 | if (Capability->SlotType == 0x00) {\r |
e27ccaba | 50 | DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));\r |
48555339 | 51 | } else if (Capability->SlotType == 0x01) {\r |
e27ccaba | 52 | DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));\r |
48555339 | 53 | } else if (Capability->SlotType == 0x02) {\r |
e27ccaba | 54 | DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));\r |
48555339 | 55 | } else {\r |
e27ccaba | 56 | DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));\r |
48555339 | 57 | }\r |
1436aea4 | 58 | \r |
e27ccaba FT |
59 | DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));\r |
60 | DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));\r | |
61 | DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));\r | |
62 | DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));\r | |
63 | DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));\r | |
64 | DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));\r | |
65 | DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));\r | |
48555339 | 66 | if (Capability->TimerCount == 0) {\r |
1096a9b0 | 67 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n"));\r |
48555339 | 68 | } else {\r |
e27ccaba | 69 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));\r |
48555339 | 70 | }\r |
1436aea4 | 71 | \r |
e27ccaba FT |
72 | DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));\r |
73 | DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));\r | |
74 | DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));\r | |
75 | DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));\r | |
48555339 FT |
76 | return;\r |
77 | }\r | |
78 | \r | |
79 | /**\r | |
80 | Read SlotInfo register from SD/MMC host controller pci config space.\r | |
81 | \r | |
82 | @param[in] PciIo The PCI IO protocol instance.\r | |
83 | @param[out] FirstBar The buffer to store the first BAR value.\r | |
84 | @param[out] SlotNum The buffer to store the supported slot number.\r | |
85 | \r | |
86 | @retval EFI_SUCCESS The operation succeeds.\r | |
87 | @retval Others The operation fails.\r | |
88 | \r | |
89 | **/\r | |
90 | EFI_STATUS\r | |
91 | EFIAPI\r | |
92 | SdMmcHcGetSlotInfo (\r | |
1436aea4 MK |
93 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
94 | OUT UINT8 *FirstBar,\r | |
95 | OUT UINT8 *SlotNum\r | |
48555339 FT |
96 | )\r |
97 | {\r | |
1436aea4 MK |
98 | EFI_STATUS Status;\r |
99 | SD_MMC_HC_SLOT_INFO SlotInfo;\r | |
48555339 FT |
100 | \r |
101 | Status = PciIo->Pci.Read (\r | |
102 | PciIo,\r | |
103 | EfiPciIoWidthUint8,\r | |
104 | SD_MMC_HC_SLOT_OFFSET,\r | |
105 | sizeof (SlotInfo),\r | |
106 | &SlotInfo\r | |
107 | );\r | |
108 | if (EFI_ERROR (Status)) {\r | |
109 | return Status;\r | |
110 | }\r | |
111 | \r | |
112 | *FirstBar = SlotInfo.FirstBar;\r | |
113 | *SlotNum = SlotInfo.SlotNum + 1;\r | |
114 | ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);\r | |
115 | return EFI_SUCCESS;\r | |
116 | }\r | |
117 | \r | |
118 | /**\r | |
119 | Read/Write specified SD/MMC host controller mmio register.\r | |
120 | \r | |
121 | @param[in] PciIo The PCI IO protocol instance.\r | |
122 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
123 | header to use as the base address for the memory\r | |
124 | operation to perform.\r | |
125 | @param[in] Offset The offset within the selected BAR to start the\r | |
126 | memory operation.\r | |
127 | @param[in] Read A boolean to indicate it's read or write operation.\r | |
128 | @param[in] Count The width of the mmio register in bytes.\r | |
129 | Must be 1, 2 , 4 or 8 bytes.\r | |
130 | @param[in, out] Data For read operations, the destination buffer to store\r | |
131 | the results. For write operations, the source buffer\r | |
132 | to write data from. The caller is responsible for\r | |
133 | having ownership of the data buffer and ensuring its\r | |
134 | size not less than Count bytes.\r | |
135 | \r | |
136 | @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r | |
137 | @retval EFI_SUCCESS The read/write operation succeeds.\r | |
138 | @retval Others The read/write operation fails.\r | |
139 | \r | |
140 | **/\r | |
141 | EFI_STATUS\r | |
142 | EFIAPI\r | |
143 | SdMmcHcRwMmio (\r | |
1436aea4 MK |
144 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
145 | IN UINT8 BarIndex,\r | |
146 | IN UINT32 Offset,\r | |
147 | IN BOOLEAN Read,\r | |
148 | IN UINT8 Count,\r | |
149 | IN OUT VOID *Data\r | |
48555339 FT |
150 | )\r |
151 | {\r | |
1436aea4 MK |
152 | EFI_STATUS Status;\r |
153 | EFI_PCI_IO_PROTOCOL_WIDTH Width;\r | |
48555339 | 154 | \r |
1436aea4 | 155 | if ((PciIo == NULL) || (Data == NULL)) {\r |
48555339 FT |
156 | return EFI_INVALID_PARAMETER;\r |
157 | }\r | |
158 | \r | |
f168816c EH |
159 | switch (Count) {\r |
160 | case 1:\r | |
161 | Width = EfiPciIoWidthUint8;\r | |
162 | break;\r | |
163 | case 2:\r | |
164 | Width = EfiPciIoWidthUint16;\r | |
165 | Count = 1;\r | |
166 | break;\r | |
167 | case 4:\r | |
168 | Width = EfiPciIoWidthUint32;\r | |
169 | Count = 1;\r | |
170 | break;\r | |
171 | case 8:\r | |
172 | Width = EfiPciIoWidthUint32;\r | |
173 | Count = 2;\r | |
174 | break;\r | |
175 | default:\r | |
176 | return EFI_INVALID_PARAMETER;\r | |
48555339 FT |
177 | }\r |
178 | \r | |
179 | if (Read) {\r | |
180 | Status = PciIo->Mem.Read (\r | |
181 | PciIo,\r | |
f168816c | 182 | Width,\r |
48555339 | 183 | BarIndex,\r |
1436aea4 | 184 | (UINT64)Offset,\r |
48555339 FT |
185 | Count,\r |
186 | Data\r | |
187 | );\r | |
188 | } else {\r | |
189 | Status = PciIo->Mem.Write (\r | |
190 | PciIo,\r | |
f168816c | 191 | Width,\r |
48555339 | 192 | BarIndex,\r |
1436aea4 | 193 | (UINT64)Offset,\r |
48555339 FT |
194 | Count,\r |
195 | Data\r | |
196 | );\r | |
197 | }\r | |
198 | \r | |
199 | return Status;\r | |
200 | }\r | |
201 | \r | |
202 | /**\r | |
203 | Do OR operation with the value of the specified SD/MMC host controller mmio register.\r | |
204 | \r | |
205 | @param[in] PciIo The PCI IO protocol instance.\r | |
206 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
207 | header to use as the base address for the memory\r | |
208 | operation to perform.\r | |
209 | @param[in] Offset The offset within the selected BAR to start the\r | |
210 | memory operation.\r | |
211 | @param[in] Count The width of the mmio register in bytes.\r | |
212 | Must be 1, 2 , 4 or 8 bytes.\r | |
213 | @param[in] OrData The pointer to the data used to do OR operation.\r | |
214 | The caller is responsible for having ownership of\r | |
215 | the data buffer and ensuring its size not less than\r | |
216 | Count bytes.\r | |
217 | \r | |
218 | @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r | |
219 | @retval EFI_SUCCESS The OR operation succeeds.\r | |
220 | @retval Others The OR operation fails.\r | |
221 | \r | |
222 | **/\r | |
223 | EFI_STATUS\r | |
224 | EFIAPI\r | |
225 | SdMmcHcOrMmio (\r | |
1436aea4 MK |
226 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
227 | IN UINT8 BarIndex,\r | |
228 | IN UINT32 Offset,\r | |
229 | IN UINT8 Count,\r | |
230 | IN VOID *OrData\r | |
48555339 FT |
231 | )\r |
232 | {\r | |
1436aea4 MK |
233 | EFI_STATUS Status;\r |
234 | UINT64 Data;\r | |
235 | UINT64 Or;\r | |
48555339 FT |
236 | \r |
237 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
238 | if (EFI_ERROR (Status)) {\r | |
239 | return Status;\r | |
240 | }\r | |
241 | \r | |
242 | if (Count == 1) {\r | |
1436aea4 | 243 | Or = *(UINT8 *)OrData;\r |
48555339 | 244 | } else if (Count == 2) {\r |
1436aea4 | 245 | Or = *(UINT16 *)OrData;\r |
48555339 | 246 | } else if (Count == 4) {\r |
1436aea4 | 247 | Or = *(UINT32 *)OrData;\r |
48555339 | 248 | } else if (Count == 8) {\r |
1436aea4 | 249 | Or = *(UINT64 *)OrData;\r |
48555339 FT |
250 | } else {\r |
251 | return EFI_INVALID_PARAMETER;\r | |
252 | }\r | |
253 | \r | |
254 | Data |= Or;\r | |
255 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
256 | \r | |
257 | return Status;\r | |
258 | }\r | |
259 | \r | |
260 | /**\r | |
261 | Do AND operation with the value of the specified SD/MMC host controller mmio register.\r | |
262 | \r | |
263 | @param[in] PciIo The PCI IO protocol instance.\r | |
264 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
265 | header to use as the base address for the memory\r | |
266 | operation to perform.\r | |
267 | @param[in] Offset The offset within the selected BAR to start the\r | |
268 | memory operation.\r | |
269 | @param[in] Count The width of the mmio register in bytes.\r | |
270 | Must be 1, 2 , 4 or 8 bytes.\r | |
271 | @param[in] AndData The pointer to the data used to do AND operation.\r | |
272 | The caller is responsible for having ownership of\r | |
273 | the data buffer and ensuring its size not less than\r | |
274 | Count bytes.\r | |
275 | \r | |
276 | @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r | |
277 | @retval EFI_SUCCESS The AND operation succeeds.\r | |
278 | @retval Others The AND operation fails.\r | |
279 | \r | |
280 | **/\r | |
281 | EFI_STATUS\r | |
282 | EFIAPI\r | |
283 | SdMmcHcAndMmio (\r | |
1436aea4 MK |
284 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
285 | IN UINT8 BarIndex,\r | |
286 | IN UINT32 Offset,\r | |
287 | IN UINT8 Count,\r | |
288 | IN VOID *AndData\r | |
48555339 FT |
289 | )\r |
290 | {\r | |
1436aea4 MK |
291 | EFI_STATUS Status;\r |
292 | UINT64 Data;\r | |
293 | UINT64 And;\r | |
48555339 FT |
294 | \r |
295 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
296 | if (EFI_ERROR (Status)) {\r | |
297 | return Status;\r | |
298 | }\r | |
299 | \r | |
300 | if (Count == 1) {\r | |
1436aea4 | 301 | And = *(UINT8 *)AndData;\r |
48555339 | 302 | } else if (Count == 2) {\r |
1436aea4 | 303 | And = *(UINT16 *)AndData;\r |
48555339 | 304 | } else if (Count == 4) {\r |
1436aea4 | 305 | And = *(UINT32 *)AndData;\r |
48555339 | 306 | } else if (Count == 8) {\r |
1436aea4 | 307 | And = *(UINT64 *)AndData;\r |
48555339 FT |
308 | } else {\r |
309 | return EFI_INVALID_PARAMETER;\r | |
310 | }\r | |
311 | \r | |
312 | Data &= And;\r | |
313 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
314 | \r | |
315 | return Status;\r | |
316 | }\r | |
317 | \r | |
318 | /**\r | |
319 | Wait for the value of the specified MMIO register set to the test value.\r | |
320 | \r | |
321 | @param[in] PciIo The PCI IO protocol instance.\r | |
322 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
323 | header to use as the base address for the memory\r | |
324 | operation to perform.\r | |
325 | @param[in] Offset The offset within the selected BAR to start the\r | |
326 | memory operation.\r | |
327 | @param[in] Count The width of the mmio register in bytes.\r | |
328 | Must be 1, 2, 4 or 8 bytes.\r | |
329 | @param[in] MaskValue The mask value of memory.\r | |
330 | @param[in] TestValue The test value of memory.\r | |
331 | \r | |
332 | @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r | |
333 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
334 | @retval Others The MMIO operation fails.\r | |
335 | \r | |
336 | **/\r | |
337 | EFI_STATUS\r | |
338 | EFIAPI\r | |
339 | SdMmcHcCheckMmioSet (\r | |
1436aea4 MK |
340 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
341 | IN UINT8 BarIndex,\r | |
342 | IN UINT32 Offset,\r | |
343 | IN UINT8 Count,\r | |
344 | IN UINT64 MaskValue,\r | |
345 | IN UINT64 TestValue\r | |
48555339 FT |
346 | )\r |
347 | {\r | |
1436aea4 MK |
348 | EFI_STATUS Status;\r |
349 | UINT64 Value;\r | |
48555339 FT |
350 | \r |
351 | //\r | |
352 | // Access PCI MMIO space to see if the value is the tested one.\r | |
353 | //\r | |
354 | Value = 0;\r | |
355 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);\r | |
356 | if (EFI_ERROR (Status)) {\r | |
357 | return Status;\r | |
358 | }\r | |
359 | \r | |
360 | Value &= MaskValue;\r | |
361 | \r | |
362 | if (Value == TestValue) {\r | |
363 | return EFI_SUCCESS;\r | |
364 | }\r | |
365 | \r | |
366 | return EFI_NOT_READY;\r | |
367 | }\r | |
368 | \r | |
369 | /**\r | |
370 | Wait for the value of the specified MMIO register set to the test value.\r | |
371 | \r | |
372 | @param[in] PciIo The PCI IO protocol instance.\r | |
373 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
374 | header to use as the base address for the memory\r | |
375 | operation to perform.\r | |
376 | @param[in] Offset The offset within the selected BAR to start the\r | |
377 | memory operation.\r | |
378 | @param[in] Count The width of the mmio register in bytes.\r | |
379 | Must be 1, 2, 4 or 8 bytes.\r | |
380 | @param[in] MaskValue The mask value of memory.\r | |
381 | @param[in] TestValue The test value of memory.\r | |
382 | @param[in] Timeout The time out value for wait memory set, uses 1\r | |
383 | microsecond as a unit.\r | |
384 | \r | |
385 | @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r | |
386 | range.\r | |
387 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
388 | @retval Others The MMIO operation fails.\r | |
389 | \r | |
390 | **/\r | |
391 | EFI_STATUS\r | |
392 | EFIAPI\r | |
393 | SdMmcHcWaitMmioSet (\r | |
1436aea4 MK |
394 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
395 | IN UINT8 BarIndex,\r | |
396 | IN UINT32 Offset,\r | |
397 | IN UINT8 Count,\r | |
398 | IN UINT64 MaskValue,\r | |
399 | IN UINT64 TestValue,\r | |
400 | IN UINT64 Timeout\r | |
48555339 FT |
401 | )\r |
402 | {\r | |
1436aea4 MK |
403 | EFI_STATUS Status;\r |
404 | BOOLEAN InfiniteWait;\r | |
48555339 FT |
405 | \r |
406 | if (Timeout == 0) {\r | |
407 | InfiniteWait = TRUE;\r | |
408 | } else {\r | |
409 | InfiniteWait = FALSE;\r | |
410 | }\r | |
411 | \r | |
412 | while (InfiniteWait || (Timeout > 0)) {\r | |
413 | Status = SdMmcHcCheckMmioSet (\r | |
414 | PciIo,\r | |
415 | BarIndex,\r | |
416 | Offset,\r | |
417 | Count,\r | |
418 | MaskValue,\r | |
419 | TestValue\r | |
420 | );\r | |
421 | if (Status != EFI_NOT_READY) {\r | |
422 | return Status;\r | |
423 | }\r | |
424 | \r | |
425 | //\r | |
426 | // Stall for 1 microsecond.\r | |
427 | //\r | |
428 | gBS->Stall (1);\r | |
429 | \r | |
430 | Timeout--;\r | |
431 | }\r | |
432 | \r | |
433 | return EFI_TIMEOUT;\r | |
434 | }\r | |
435 | \r | |
b5547b9c AS |
436 | /**\r |
437 | Get the controller version information from the specified slot.\r | |
438 | \r | |
439 | @param[in] PciIo The PCI IO protocol instance.\r | |
440 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
441 | @param[out] Version The buffer to store the version information.\r | |
442 | \r | |
443 | @retval EFI_SUCCESS The operation executes successfully.\r | |
444 | @retval Others The operation fails.\r | |
445 | \r | |
446 | **/\r | |
447 | EFI_STATUS\r | |
448 | SdMmcHcGetControllerVersion (\r | |
449 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
450 | IN UINT8 Slot,\r | |
451 | OUT UINT16 *Version\r | |
452 | )\r | |
453 | {\r | |
1436aea4 | 454 | EFI_STATUS Status;\r |
b5547b9c AS |
455 | \r |
456 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);\r | |
457 | if (EFI_ERROR (Status)) {\r | |
458 | return Status;\r | |
459 | }\r | |
460 | \r | |
461 | *Version &= 0xFF;\r | |
462 | \r | |
463 | return EFI_SUCCESS;\r | |
464 | }\r | |
465 | \r | |
48555339 FT |
466 | /**\r |
467 | Software reset the specified SD/MMC host controller and enable all interrupts.\r | |
468 | \r | |
b23fc39c | 469 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 FT |
470 | @param[in] Slot The slot number of the SD card to send the command to.\r |
471 | \r | |
472 | @retval EFI_SUCCESS The software reset executes successfully.\r | |
473 | @retval Others The software reset fails.\r | |
474 | \r | |
475 | **/\r | |
476 | EFI_STATUS\r | |
477 | SdMmcHcReset (\r | |
1436aea4 MK |
478 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
479 | IN UINT8 Slot\r | |
48555339 FT |
480 | )\r |
481 | {\r | |
1436aea4 MK |
482 | EFI_STATUS Status;\r |
483 | UINT8 SwReset;\r | |
484 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
48555339 | 485 | \r |
b23fc39c AB |
486 | //\r |
487 | // Notify the SD/MMC override protocol that we are about to reset\r | |
488 | // the SD/MMC host controller.\r | |
489 | //\r | |
1436aea4 | 490 | if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {\r |
b23fc39c AB |
491 | Status = mOverride->NotifyPhase (\r |
492 | Private->ControllerHandle,\r | |
493 | Slot,\r | |
49c99534 | 494 | EdkiiSdMmcResetPre,\r |
1436aea4 MK |
495 | NULL\r |
496 | );\r | |
b23fc39c | 497 | if (EFI_ERROR (Status)) {\r |
1436aea4 MK |
498 | DEBUG ((\r |
499 | DEBUG_WARN,\r | |
b23fc39c | 500 | "%a: SD/MMC pre reset notifier callback failed - %r\n",\r |
1436aea4 MK |
501 | __FUNCTION__,\r |
502 | Status\r | |
503 | ));\r | |
b23fc39c AB |
504 | return Status;\r |
505 | }\r | |
506 | }\r | |
507 | \r | |
508 | PciIo = Private->PciIo;\r | |
064d301f TM |
509 | SwReset = BIT0;\r |
510 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);\r | |
48555339 FT |
511 | \r |
512 | if (EFI_ERROR (Status)) {\r | |
064d301f | 513 | DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));\r |
48555339 FT |
514 | return Status;\r |
515 | }\r | |
516 | \r | |
517 | Status = SdMmcHcWaitMmioSet (\r | |
518 | PciIo,\r | |
519 | Slot,\r | |
520 | SD_MMC_HC_SW_RST,\r | |
521 | sizeof (SwReset),\r | |
064d301f | 522 | BIT0,\r |
48555339 FT |
523 | 0x00,\r |
524 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
525 | );\r | |
526 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 527 | DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r |
48555339 FT |
528 | return Status;\r |
529 | }\r | |
b23fc39c | 530 | \r |
48555339 FT |
531 | //\r |
532 | // Enable all interrupt after reset all.\r | |
533 | //\r | |
534 | Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r | |
b23fc39c | 535 | if (EFI_ERROR (Status)) {\r |
1436aea4 MK |
536 | DEBUG ((\r |
537 | DEBUG_INFO,\r | |
538 | "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",\r | |
539 | Status\r | |
540 | ));\r | |
b23fc39c AB |
541 | return Status;\r |
542 | }\r | |
543 | \r | |
544 | //\r | |
545 | // Notify the SD/MMC override protocol that we have just reset\r | |
546 | // the SD/MMC host controller.\r | |
547 | //\r | |
1436aea4 | 548 | if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {\r |
b23fc39c AB |
549 | Status = mOverride->NotifyPhase (\r |
550 | Private->ControllerHandle,\r | |
551 | Slot,\r | |
49c99534 | 552 | EdkiiSdMmcResetPost,\r |
1436aea4 MK |
553 | NULL\r |
554 | );\r | |
b23fc39c | 555 | if (EFI_ERROR (Status)) {\r |
1436aea4 MK |
556 | DEBUG ((\r |
557 | DEBUG_WARN,\r | |
b23fc39c | 558 | "%a: SD/MMC post reset notifier callback failed - %r\n",\r |
1436aea4 MK |
559 | __FUNCTION__,\r |
560 | Status\r | |
561 | ));\r | |
b23fc39c AB |
562 | }\r |
563 | }\r | |
48555339 FT |
564 | \r |
565 | return Status;\r | |
566 | }\r | |
567 | \r | |
568 | /**\r | |
569 | Set all interrupt status bits in Normal and Error Interrupt Status Enable\r | |
570 | register.\r | |
571 | \r | |
572 | @param[in] PciIo The PCI IO protocol instance.\r | |
573 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
574 | \r | |
575 | @retval EFI_SUCCESS The operation executes successfully.\r | |
576 | @retval Others The operation fails.\r | |
577 | \r | |
578 | **/\r | |
579 | EFI_STATUS\r | |
580 | SdMmcHcEnableInterrupt (\r | |
1436aea4 MK |
581 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
582 | IN UINT8 Slot\r | |
48555339 FT |
583 | )\r |
584 | {\r | |
1436aea4 MK |
585 | EFI_STATUS Status;\r |
586 | UINT16 IntStatus;\r | |
48555339 FT |
587 | \r |
588 | //\r | |
589 | // Enable all bits in Error Interrupt Status Enable Register\r | |
590 | //\r | |
591 | IntStatus = 0xFFFF;\r | |
1436aea4 | 592 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r |
48555339 FT |
593 | if (EFI_ERROR (Status)) {\r |
594 | return Status;\r | |
595 | }\r | |
1436aea4 | 596 | \r |
48555339 FT |
597 | //\r |
598 | // Enable all bits in Normal Interrupt Status Enable Register\r | |
599 | //\r | |
600 | IntStatus = 0xFFFF;\r | |
1436aea4 | 601 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r |
48555339 FT |
602 | \r |
603 | return Status;\r | |
604 | }\r | |
605 | \r | |
606 | /**\r | |
607 | Get the capability data from the specified slot.\r | |
608 | \r | |
609 | @param[in] PciIo The PCI IO protocol instance.\r | |
610 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
611 | @param[out] Capability The buffer to store the capability data.\r | |
612 | \r | |
613 | @retval EFI_SUCCESS The operation executes successfully.\r | |
614 | @retval Others The operation fails.\r | |
615 | \r | |
616 | **/\r | |
617 | EFI_STATUS\r | |
618 | SdMmcHcGetCapability (\r | |
619 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
620 | IN UINT8 Slot,\r | |
1436aea4 | 621 | OUT SD_MMC_HC_SLOT_CAP *Capability\r |
48555339 FT |
622 | )\r |
623 | {\r | |
1436aea4 MK |
624 | EFI_STATUS Status;\r |
625 | UINT64 Cap;\r | |
48555339 FT |
626 | \r |
627 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r | |
628 | if (EFI_ERROR (Status)) {\r | |
629 | return Status;\r | |
630 | }\r | |
631 | \r | |
632 | CopyMem (Capability, &Cap, sizeof (Cap));\r | |
633 | \r | |
634 | return EFI_SUCCESS;\r | |
635 | }\r | |
636 | \r | |
637 | /**\r | |
638 | Get the maximum current capability data from the specified slot.\r | |
639 | \r | |
640 | @param[in] PciIo The PCI IO protocol instance.\r | |
641 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
642 | @param[out] MaxCurrent The buffer to store the maximum current capability data.\r | |
643 | \r | |
644 | @retval EFI_SUCCESS The operation executes successfully.\r | |
645 | @retval Others The operation fails.\r | |
646 | \r | |
647 | **/\r | |
648 | EFI_STATUS\r | |
649 | SdMmcHcGetMaxCurrent (\r | |
650 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
651 | IN UINT8 Slot,\r | |
1436aea4 | 652 | OUT UINT64 *MaxCurrent\r |
48555339 FT |
653 | )\r |
654 | {\r | |
1436aea4 | 655 | EFI_STATUS Status;\r |
48555339 FT |
656 | \r |
657 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);\r | |
658 | \r | |
659 | return Status;\r | |
660 | }\r | |
661 | \r | |
662 | /**\r | |
663 | Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r | |
664 | slot.\r | |
665 | \r | |
666 | Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r | |
667 | \r | |
668 | @param[in] PciIo The PCI IO protocol instance.\r | |
669 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
670 | @param[out] MediaPresent The pointer to the media present boolean value.\r | |
671 | \r | |
672 | @retval EFI_SUCCESS There is no media change happened.\r | |
673 | @retval EFI_MEDIA_CHANGED There is media change happened.\r | |
674 | @retval Others The detection fails.\r | |
675 | \r | |
676 | **/\r | |
677 | EFI_STATUS\r | |
678 | SdMmcHcCardDetect (\r | |
1436aea4 MK |
679 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
680 | IN UINT8 Slot,\r | |
681 | OUT BOOLEAN *MediaPresent\r | |
48555339 FT |
682 | )\r |
683 | {\r | |
1436aea4 MK |
684 | EFI_STATUS Status;\r |
685 | UINT16 Data;\r | |
686 | UINT32 PresentState;\r | |
48555339 | 687 | \r |
2e9107b8 FT |
688 | //\r |
689 | // Check Present State Register to see if there is a card presented.\r | |
690 | //\r | |
691 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r | |
692 | if (EFI_ERROR (Status)) {\r | |
693 | return Status;\r | |
694 | }\r | |
695 | \r | |
696 | if ((PresentState & BIT16) != 0) {\r | |
697 | *MediaPresent = TRUE;\r | |
698 | } else {\r | |
699 | *MediaPresent = FALSE;\r | |
700 | }\r | |
701 | \r | |
48555339 FT |
702 | //\r |
703 | // Check Normal Interrupt Status Register\r | |
704 | //\r | |
705 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r | |
706 | if (EFI_ERROR (Status)) {\r | |
707 | return Status;\r | |
708 | }\r | |
709 | \r | |
710 | if ((Data & (BIT6 | BIT7)) != 0) {\r | |
711 | //\r | |
712 | // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r | |
713 | //\r | |
714 | Data &= BIT6 | BIT7;\r | |
715 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r | |
716 | if (EFI_ERROR (Status)) {\r | |
717 | return Status;\r | |
718 | }\r | |
719 | \r | |
48555339 FT |
720 | return EFI_MEDIA_CHANGED;\r |
721 | }\r | |
722 | \r | |
723 | return EFI_SUCCESS;\r | |
724 | }\r | |
725 | \r | |
726 | /**\r | |
727 | Stop SD/MMC card clock.\r | |
728 | \r | |
729 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r | |
730 | \r | |
731 | @param[in] PciIo The PCI IO protocol instance.\r | |
732 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
733 | \r | |
734 | @retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r | |
735 | @retval Others Fail to stop SD/MMC clock.\r | |
736 | \r | |
737 | **/\r | |
738 | EFI_STATUS\r | |
739 | SdMmcHcStopClock (\r | |
1436aea4 MK |
740 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
741 | IN UINT8 Slot\r | |
48555339 FT |
742 | )\r |
743 | {\r | |
1436aea4 MK |
744 | EFI_STATUS Status;\r |
745 | UINT32 PresentState;\r | |
746 | UINT16 ClockCtrl;\r | |
48555339 FT |
747 | \r |
748 | //\r | |
749 | // Ensure no SD transactions are occurring on the SD Bus by\r | |
750 | // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r | |
751 | // in the Present State register to be 0.\r | |
752 | //\r | |
753 | Status = SdMmcHcWaitMmioSet (\r | |
754 | PciIo,\r | |
755 | Slot,\r | |
756 | SD_MMC_HC_PRESENT_STATE,\r | |
757 | sizeof (PresentState),\r | |
758 | BIT0 | BIT1,\r | |
759 | 0,\r | |
760 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
761 | );\r | |
762 | if (EFI_ERROR (Status)) {\r | |
763 | return Status;\r | |
764 | }\r | |
765 | \r | |
766 | //\r | |
767 | // Set SD Clock Enable in the Clock Control register to 0\r | |
768 | //\r | |
1436aea4 MK |
769 | ClockCtrl = (UINT16) ~BIT2;\r |
770 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
48555339 FT |
771 | \r |
772 | return Status;\r | |
773 | }\r | |
774 | \r | |
f68cb23c AM |
775 | /**\r |
776 | Start the SD clock.\r | |
777 | \r | |
778 | @param[in] PciIo The PCI IO protocol instance.\r | |
779 | @param[in] Slot The slot number.\r | |
780 | \r | |
781 | @retval EFI_SUCCESS Succeeded to start the SD clock.\r | |
27f44ea1 | 782 | @retval Others Failed to start the SD clock.\r |
f68cb23c AM |
783 | **/\r |
784 | EFI_STATUS\r | |
785 | SdMmcHcStartSdClock (\r | |
786 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
787 | IN UINT8 Slot\r | |
788 | )\r | |
789 | {\r | |
1436aea4 | 790 | UINT16 ClockCtrl;\r |
f68cb23c AM |
791 | \r |
792 | //\r | |
793 | // Set SD Clock Enable in the Clock Control register to 1\r | |
794 | //\r | |
795 | ClockCtrl = BIT2;\r | |
796 | return SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
797 | }\r | |
798 | \r | |
48555339 FT |
799 | /**\r |
800 | SD/MMC card clock supply.\r | |
801 | \r | |
802 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r | |
803 | \r | |
49accded AM |
804 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
805 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
806 | @param[in] BusTiming BusTiming at which the frequency change is done.\r | |
807 | @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.\r | |
808 | @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r | |
48555339 FT |
809 | \r |
810 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
811 | @retval Others The clock isn't supplied successfully.\r | |
812 | \r | |
813 | **/\r | |
814 | EFI_STATUS\r | |
815 | SdMmcHcClockSupply (\r | |
49accded AM |
816 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
817 | IN UINT8 Slot,\r | |
818 | IN SD_MMC_BUS_MODE BusTiming,\r | |
819 | IN BOOLEAN FirstTimeSetup,\r | |
820 | IN UINT64 ClockFreq\r | |
48555339 FT |
821 | )\r |
822 | {\r | |
1436aea4 MK |
823 | EFI_STATUS Status;\r |
824 | UINT32 SettingFreq;\r | |
825 | UINT32 Divisor;\r | |
826 | UINT32 Remainder;\r | |
827 | UINT16 ClockCtrl;\r | |
828 | UINT32 BaseClkFreq;\r | |
829 | UINT16 ControllerVer;\r | |
830 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
831 | \r | |
832 | PciIo = Private->PciIo;\r | |
833 | BaseClkFreq = Private->BaseClkFreq[Slot];\r | |
49accded | 834 | ControllerVer = Private->ControllerVersion[Slot];\r |
48555339 | 835 | \r |
1436aea4 | 836 | if ((BaseClkFreq == 0) || (ClockFreq == 0)) {\r |
48555339 FT |
837 | return EFI_INVALID_PARAMETER;\r |
838 | }\r | |
cb9cb9e2 FT |
839 | \r |
840 | if (ClockFreq > (BaseClkFreq * 1000)) {\r | |
841 | ClockFreq = BaseClkFreq * 1000;\r | |
842 | }\r | |
843 | \r | |
48555339 FT |
844 | //\r |
845 | // Calculate the divisor of base frequency.\r | |
846 | //\r | |
847 | Divisor = 0;\r | |
848 | SettingFreq = BaseClkFreq * 1000;\r | |
849 | while (ClockFreq < SettingFreq) {\r | |
850 | Divisor++;\r | |
851 | \r | |
852 | SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r | |
853 | Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r | |
854 | if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r | |
855 | break;\r | |
856 | }\r | |
1436aea4 | 857 | \r |
48555339 | 858 | if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r |
1436aea4 | 859 | SettingFreq++;\r |
48555339 FT |
860 | }\r |
861 | }\r | |
862 | \r | |
e27ccaba | 863 | DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r |
48555339 | 864 | \r |
48555339 FT |
865 | //\r |
866 | // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r | |
867 | //\r | |
b5547b9c | 868 | if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&\r |
1436aea4 MK |
869 | (ControllerVer <= SD_MMC_HC_CTRL_VER_420))\r |
870 | {\r | |
48555339 FT |
871 | ASSERT (Divisor <= 0x3FF);\r |
872 | ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r | |
b5547b9c | 873 | } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||\r |
1436aea4 MK |
874 | (ControllerVer == SD_MMC_HC_CTRL_VER_200))\r |
875 | {\r | |
48555339 FT |
876 | //\r |
877 | // Only the most significant bit can be used as divisor.\r | |
878 | //\r | |
879 | if (((Divisor - 1) & Divisor) != 0) {\r | |
880 | Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r | |
881 | }\r | |
1436aea4 | 882 | \r |
48555339 FT |
883 | ASSERT (Divisor <= 0x80);\r |
884 | ClockCtrl = (Divisor & 0xFF) << 8;\r | |
885 | } else {\r | |
e27ccaba | 886 | DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r |
48555339 FT |
887 | return EFI_UNSUPPORTED;\r |
888 | }\r | |
889 | \r | |
890 | //\r | |
891 | // Stop bus clock at first\r | |
892 | //\r | |
893 | Status = SdMmcHcStopClock (PciIo, Slot);\r | |
894 | if (EFI_ERROR (Status)) {\r | |
895 | return Status;\r | |
896 | }\r | |
897 | \r | |
898 | //\r | |
899 | // Supply clock frequency with specified divisor\r | |
900 | //\r | |
901 | ClockCtrl |= BIT0;\r | |
1436aea4 | 902 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r |
48555339 | 903 | if (EFI_ERROR (Status)) {\r |
e27ccaba | 904 | DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r |
48555339 FT |
905 | return Status;\r |
906 | }\r | |
907 | \r | |
908 | //\r | |
909 | // Wait Internal Clock Stable in the Clock Control register to be 1\r | |
910 | //\r | |
911 | Status = SdMmcHcWaitMmioSet (\r | |
912 | PciIo,\r | |
913 | Slot,\r | |
914 | SD_MMC_HC_CLOCK_CTRL,\r | |
915 | sizeof (ClockCtrl),\r | |
916 | BIT1,\r | |
917 | BIT1,\r | |
918 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
919 | );\r | |
920 | if (EFI_ERROR (Status)) {\r | |
921 | return Status;\r | |
922 | }\r | |
923 | \r | |
f68cb23c AM |
924 | Status = SdMmcHcStartSdClock (PciIo, Slot);\r |
925 | if (EFI_ERROR (Status)) {\r | |
926 | return Status;\r | |
927 | }\r | |
48555339 | 928 | \r |
49accded AM |
929 | //\r |
930 | // We don't notify the platform on first time setup to avoid changing\r | |
931 | // legacy behavior. During first time setup we also don't know what type\r | |
932 | // of the card slot it is and which enum value of BusTiming applies.\r | |
933 | //\r | |
1436aea4 | 934 | if (!FirstTimeSetup && (mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {\r |
49accded AM |
935 | Status = mOverride->NotifyPhase (\r |
936 | Private->ControllerHandle,\r | |
937 | Slot,\r | |
938 | EdkiiSdMmcSwitchClockFreqPost,\r | |
939 | &BusTiming\r | |
940 | );\r | |
941 | if (EFI_ERROR (Status)) {\r | |
942 | DEBUG ((\r | |
943 | DEBUG_ERROR,\r | |
944 | "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",\r | |
945 | __FUNCTION__,\r | |
946 | Status\r | |
947 | ));\r | |
948 | return Status;\r | |
949 | }\r | |
950 | }\r | |
951 | \r | |
64362314 AM |
952 | Private->Slot[Slot].CurrentFreq = ClockFreq;\r |
953 | \r | |
48555339 FT |
954 | return Status;\r |
955 | }\r | |
956 | \r | |
957 | /**\r | |
958 | SD/MMC bus power control.\r | |
959 | \r | |
960 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
961 | \r | |
962 | @param[in] PciIo The PCI IO protocol instance.\r | |
963 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
964 | @param[in] PowerCtrl The value setting to the power control register.\r | |
965 | \r | |
966 | @retval TRUE There is a SD/MMC card attached.\r | |
967 | @retval FALSE There is no a SD/MMC card attached.\r | |
968 | \r | |
969 | **/\r | |
970 | EFI_STATUS\r | |
971 | SdMmcHcPowerControl (\r | |
1436aea4 MK |
972 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
973 | IN UINT8 Slot,\r | |
974 | IN UINT8 PowerCtrl\r | |
48555339 FT |
975 | )\r |
976 | {\r | |
1436aea4 | 977 | EFI_STATUS Status;\r |
48555339 FT |
978 | \r |
979 | //\r | |
980 | // Clr SD Bus Power\r | |
981 | //\r | |
1436aea4 MK |
982 | PowerCtrl &= (UINT8) ~BIT0;\r |
983 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
48555339 FT |
984 | if (EFI_ERROR (Status)) {\r |
985 | return Status;\r | |
986 | }\r | |
987 | \r | |
988 | //\r | |
989 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
990 | //\r | |
991 | PowerCtrl |= BIT0;\r | |
1436aea4 | 992 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r |
48555339 FT |
993 | \r |
994 | return Status;\r | |
995 | }\r | |
996 | \r | |
997 | /**\r | |
998 | Set the SD/MMC bus width.\r | |
999 | \r | |
1000 | Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r | |
1001 | \r | |
1002 | @param[in] PciIo The PCI IO protocol instance.\r | |
1003 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1004 | @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r | |
1005 | \r | |
1006 | @retval EFI_SUCCESS The bus width is set successfully.\r | |
1007 | @retval Others The bus width isn't set successfully.\r | |
1008 | \r | |
1009 | **/\r | |
1010 | EFI_STATUS\r | |
1011 | SdMmcHcSetBusWidth (\r | |
1436aea4 MK |
1012 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
1013 | IN UINT8 Slot,\r | |
1014 | IN UINT16 BusWidth\r | |
48555339 FT |
1015 | )\r |
1016 | {\r | |
1436aea4 MK |
1017 | EFI_STATUS Status;\r |
1018 | UINT8 HostCtrl1;\r | |
48555339 FT |
1019 | \r |
1020 | if (BusWidth == 1) {\r | |
1436aea4 MK |
1021 | HostCtrl1 = (UINT8) ~(BIT5 | BIT1);\r |
1022 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
48555339 FT |
1023 | } else if (BusWidth == 4) {\r |
1024 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
1025 | if (EFI_ERROR (Status)) {\r | |
1026 | return Status;\r | |
1027 | }\r | |
1436aea4 | 1028 | \r |
48555339 | 1029 | HostCtrl1 |= BIT1;\r |
1436aea4 MK |
1030 | HostCtrl1 &= (UINT8) ~BIT5;\r |
1031 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
48555339 FT |
1032 | } else if (BusWidth == 8) {\r |
1033 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
1034 | if (EFI_ERROR (Status)) {\r | |
1035 | return Status;\r | |
1036 | }\r | |
1436aea4 MK |
1037 | \r |
1038 | HostCtrl1 &= (UINT8) ~BIT1;\r | |
48555339 | 1039 | HostCtrl1 |= BIT5;\r |
1436aea4 | 1040 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r |
48555339 FT |
1041 | } else {\r |
1042 | ASSERT (FALSE);\r | |
1043 | return EFI_INVALID_PARAMETER;\r | |
1044 | }\r | |
1045 | \r | |
1046 | return Status;\r | |
1047 | }\r | |
1048 | \r | |
b5547b9c AS |
1049 | /**\r |
1050 | Configure V4 controller enhancements at initialization.\r | |
1051 | \r | |
1052 | @param[in] PciIo The PCI IO protocol instance.\r | |
1053 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1054 | @param[in] Capability The capability of the slot.\r | |
1055 | @param[in] ControllerVer The version of host controller.\r | |
1056 | \r | |
1057 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
1058 | \r | |
1059 | **/\r | |
1060 | EFI_STATUS\r | |
1061 | SdMmcHcInitV4Enhancements (\r | |
1436aea4 MK |
1062 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
1063 | IN UINT8 Slot,\r | |
1064 | IN SD_MMC_HC_SLOT_CAP Capability,\r | |
1065 | IN UINT16 ControllerVer\r | |
b5547b9c AS |
1066 | )\r |
1067 | {\r | |
1436aea4 MK |
1068 | EFI_STATUS Status;\r |
1069 | UINT16 HostCtrl2;\r | |
b5547b9c AS |
1070 | \r |
1071 | //\r | |
1072 | // Check if controller version V4 or higher\r | |
1073 | //\r | |
1074 | if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r | |
1075 | HostCtrl2 = SD_MMC_HC_V4_EN;\r | |
1076 | //\r | |
690d60c0 | 1077 | // Check if controller version V4.0\r |
b5547b9c | 1078 | //\r |
690d60c0 AS |
1079 | if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {\r |
1080 | //\r | |
1081 | // Check if 64bit support is available\r | |
1082 | //\r | |
1083 | if (Capability.SysBus64V3 != 0) {\r | |
1084 | HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r | |
1085 | DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r | |
1086 | }\r | |
b5547b9c AS |
1087 | }\r |
1088 | //\r | |
1089 | // Check if controller version V4.10 or higher\r | |
1090 | //\r | |
690d60c0 AS |
1091 | else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {\r |
1092 | //\r | |
1093 | // Check if 64bit support is available\r | |
1094 | //\r | |
1095 | if (Capability.SysBus64V4 != 0) {\r | |
1096 | HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r | |
1097 | DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r | |
1098 | }\r | |
1436aea4 | 1099 | \r |
b5547b9c AS |
1100 | HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;\r |
1101 | DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));\r | |
1102 | }\r | |
1436aea4 | 1103 | \r |
b5547b9c AS |
1104 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r |
1105 | if (EFI_ERROR (Status)) {\r | |
1106 | return Status;\r | |
1107 | }\r | |
1108 | }\r | |
1109 | \r | |
1110 | return EFI_SUCCESS;\r | |
1111 | }\r | |
1112 | \r | |
48555339 FT |
1113 | /**\r |
1114 | Supply SD/MMC card with maximum voltage at initialization.\r | |
1115 | \r | |
1116 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
1117 | \r | |
1118 | @param[in] PciIo The PCI IO protocol instance.\r | |
1119 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1120 | @param[in] Capability The capability of the slot.\r | |
1121 | \r | |
1122 | @retval EFI_SUCCESS The voltage is supplied successfully.\r | |
1123 | @retval Others The voltage isn't supplied successfully.\r | |
1124 | \r | |
1125 | **/\r | |
1126 | EFI_STATUS\r | |
1127 | SdMmcHcInitPowerVoltage (\r | |
1436aea4 MK |
1128 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
1129 | IN UINT8 Slot,\r | |
1130 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
48555339 FT |
1131 | )\r |
1132 | {\r | |
1436aea4 MK |
1133 | EFI_STATUS Status;\r |
1134 | UINT8 MaxVoltage;\r | |
1135 | UINT8 HostCtrl2;\r | |
48555339 FT |
1136 | \r |
1137 | //\r | |
1138 | // Calculate supported maximum voltage according to SD Bus Voltage Select\r | |
1139 | //\r | |
1140 | if (Capability.Voltage33 != 0) {\r | |
1141 | //\r | |
1142 | // Support 3.3V\r | |
1143 | //\r | |
1144 | MaxVoltage = 0x0E;\r | |
1145 | } else if (Capability.Voltage30 != 0) {\r | |
1146 | //\r | |
1147 | // Support 3.0V\r | |
1148 | //\r | |
1149 | MaxVoltage = 0x0C;\r | |
1150 | } else if (Capability.Voltage18 != 0) {\r | |
1151 | //\r | |
1152 | // Support 1.8V\r | |
1153 | //\r | |
1154 | MaxVoltage = 0x0A;\r | |
1155 | HostCtrl2 = BIT3;\r | |
1436aea4 | 1156 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r |
48555339 FT |
1157 | gBS->Stall (5000);\r |
1158 | if (EFI_ERROR (Status)) {\r | |
1159 | return Status;\r | |
1160 | }\r | |
1161 | } else {\r | |
1162 | ASSERT (FALSE);\r | |
1163 | return EFI_DEVICE_ERROR;\r | |
1164 | }\r | |
1165 | \r | |
1166 | //\r | |
1167 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
1168 | //\r | |
1169 | Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);\r | |
1170 | \r | |
1171 | return Status;\r | |
1172 | }\r | |
1173 | \r | |
1174 | /**\r | |
1175 | Initialize the Timeout Control register with most conservative value at initialization.\r | |
1176 | \r | |
1177 | Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r | |
1178 | \r | |
1179 | @param[in] PciIo The PCI IO protocol instance.\r | |
1180 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1181 | \r | |
1182 | @retval EFI_SUCCESS The timeout control register is configured successfully.\r | |
1183 | @retval Others The timeout control register isn't configured successfully.\r | |
1184 | \r | |
1185 | **/\r | |
1186 | EFI_STATUS\r | |
1187 | SdMmcHcInitTimeoutCtrl (\r | |
1436aea4 MK |
1188 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
1189 | IN UINT8 Slot\r | |
48555339 FT |
1190 | )\r |
1191 | {\r | |
1436aea4 MK |
1192 | EFI_STATUS Status;\r |
1193 | UINT8 Timeout;\r | |
48555339 FT |
1194 | \r |
1195 | Timeout = 0x0E;\r | |
1196 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r | |
1197 | \r | |
1198 | return Status;\r | |
1199 | }\r | |
1200 | \r | |
1201 | /**\r | |
1202 | Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r | |
1203 | at initialization.\r | |
1204 | \r | |
b23fc39c | 1205 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 | 1206 | @param[in] Slot The slot number of the SD card to send the command to.\r |
48555339 FT |
1207 | \r |
1208 | @retval EFI_SUCCESS The host controller is initialized successfully.\r | |
1209 | @retval Others The host controller isn't initialized successfully.\r | |
1210 | \r | |
1211 | **/\r | |
1212 | EFI_STATUS\r | |
1213 | SdMmcHcInitHost (\r | |
1436aea4 MK |
1214 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
1215 | IN UINT8 Slot\r | |
48555339 FT |
1216 | )\r |
1217 | {\r | |
1436aea4 MK |
1218 | EFI_STATUS Status;\r |
1219 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1220 | SD_MMC_HC_SLOT_CAP Capability;\r | |
b23fc39c AB |
1221 | \r |
1222 | //\r | |
1223 | // Notify the SD/MMC override protocol that we are about to initialize\r | |
1224 | // the SD/MMC host controller.\r | |
1225 | //\r | |
1436aea4 | 1226 | if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {\r |
b23fc39c AB |
1227 | Status = mOverride->NotifyPhase (\r |
1228 | Private->ControllerHandle,\r | |
1229 | Slot,\r | |
49c99534 | 1230 | EdkiiSdMmcInitHostPre,\r |
1436aea4 MK |
1231 | NULL\r |
1232 | );\r | |
b23fc39c | 1233 | if (EFI_ERROR (Status)) {\r |
1436aea4 MK |
1234 | DEBUG ((\r |
1235 | DEBUG_WARN,\r | |
b23fc39c | 1236 | "%a: SD/MMC pre init notifier callback failed - %r\n",\r |
1436aea4 MK |
1237 | __FUNCTION__,\r |
1238 | Status\r | |
1239 | ));\r | |
b23fc39c AB |
1240 | return Status;\r |
1241 | }\r | |
1242 | }\r | |
1243 | \r | |
1436aea4 | 1244 | PciIo = Private->PciIo;\r |
b23fc39c | 1245 | Capability = Private->Capability[Slot];\r |
48555339 | 1246 | \r |
b5547b9c AS |
1247 | Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);\r |
1248 | if (EFI_ERROR (Status)) {\r | |
1249 | return Status;\r | |
1250 | }\r | |
1251 | \r | |
49accded AM |
1252 | //\r |
1253 | // Perform first time clock setup with 400 KHz frequency.\r | |
1254 | // We send the 0 as the BusTiming value because at this time\r | |
1255 | // we still do not know the slot type and which enum value will apply.\r | |
1256 | // Since it is a first time setup SdMmcHcClockSupply won't notify\r | |
1257 | // the platofrm driver anyway so it doesn't matter.\r | |
1258 | //\r | |
1259 | Status = SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);\r | |
48555339 FT |
1260 | if (EFI_ERROR (Status)) {\r |
1261 | return Status;\r | |
1262 | }\r | |
1263 | \r | |
1264 | Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);\r | |
1265 | if (EFI_ERROR (Status)) {\r | |
1266 | return Status;\r | |
1267 | }\r | |
1268 | \r | |
1269 | Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r | |
b23fc39c AB |
1270 | if (EFI_ERROR (Status)) {\r |
1271 | return Status;\r | |
1272 | }\r | |
1273 | \r | |
1274 | //\r | |
1275 | // Notify the SD/MMC override protocol that we are have just initialized\r | |
1276 | // the SD/MMC host controller.\r | |
1277 | //\r | |
1436aea4 | 1278 | if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {\r |
b23fc39c AB |
1279 | Status = mOverride->NotifyPhase (\r |
1280 | Private->ControllerHandle,\r | |
1281 | Slot,\r | |
49c99534 | 1282 | EdkiiSdMmcInitHostPost,\r |
1436aea4 MK |
1283 | NULL\r |
1284 | );\r | |
b23fc39c | 1285 | if (EFI_ERROR (Status)) {\r |
1436aea4 MK |
1286 | DEBUG ((\r |
1287 | DEBUG_WARN,\r | |
b23fc39c | 1288 | "%a: SD/MMC post init notifier callback failed - %r\n",\r |
1436aea4 MK |
1289 | __FUNCTION__,\r |
1290 | Status\r | |
1291 | ));\r | |
b23fc39c AB |
1292 | }\r |
1293 | }\r | |
1436aea4 | 1294 | \r |
48555339 FT |
1295 | return Status;\r |
1296 | }\r | |
1297 | \r | |
a4708009 TM |
1298 | /**\r |
1299 | Set SD Host Controler control 2 registry according to selected speed.\r | |
1300 | \r | |
1301 | @param[in] ControllerHandle The handle of the controller.\r | |
1302 | @param[in] PciIo The PCI IO protocol instance.\r | |
1303 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1304 | @param[in] Timing The timing to select.\r | |
1305 | \r | |
1306 | @retval EFI_SUCCESS The timing is set successfully.\r | |
1307 | @retval Others The timing isn't set successfully.\r | |
1308 | **/\r | |
1309 | EFI_STATUS\r | |
1310 | SdMmcHcUhsSignaling (\r | |
1436aea4 MK |
1311 | IN EFI_HANDLE ControllerHandle,\r |
1312 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1313 | IN UINT8 Slot,\r | |
1314 | IN SD_MMC_BUS_MODE Timing\r | |
a4708009 TM |
1315 | )\r |
1316 | {\r | |
1436aea4 MK |
1317 | EFI_STATUS Status;\r |
1318 | UINT8 HostCtrl2;\r | |
a4708009 | 1319 | \r |
1436aea4 MK |
1320 | HostCtrl2 = (UINT8) ~SD_MMC_HC_CTRL_UHS_MASK;\r |
1321 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
a4708009 TM |
1322 | if (EFI_ERROR (Status)) {\r |
1323 | return Status;\r | |
1324 | }\r | |
1325 | \r | |
1326 | switch (Timing) {\r | |
1327 | case SdMmcUhsSdr12:\r | |
1328 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;\r | |
1329 | break;\r | |
1330 | case SdMmcUhsSdr25:\r | |
1331 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;\r | |
1332 | break;\r | |
1333 | case SdMmcUhsSdr50:\r | |
1334 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;\r | |
1335 | break;\r | |
1336 | case SdMmcUhsSdr104:\r | |
1337 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;\r | |
1338 | break;\r | |
1339 | case SdMmcUhsDdr50:\r | |
1340 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;\r | |
1341 | break;\r | |
1342 | case SdMmcMmcLegacy:\r | |
1343 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;\r | |
1344 | break;\r | |
1345 | case SdMmcMmcHsSdr:\r | |
1346 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;\r | |
1347 | break;\r | |
1348 | case SdMmcMmcHsDdr:\r | |
1349 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;\r | |
1350 | break;\r | |
1351 | case SdMmcMmcHs200:\r | |
1352 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;\r | |
1353 | break;\r | |
1354 | case SdMmcMmcHs400:\r | |
1355 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;\r | |
1356 | break;\r | |
1357 | default:\r | |
1436aea4 MK |
1358 | HostCtrl2 = 0;\r |
1359 | break;\r | |
a4708009 | 1360 | }\r |
1436aea4 | 1361 | \r |
a4708009 TM |
1362 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r |
1363 | if (EFI_ERROR (Status)) {\r | |
1364 | return Status;\r | |
1365 | }\r | |
1366 | \r | |
1436aea4 | 1367 | if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {\r |
a4708009 TM |
1368 | Status = mOverride->NotifyPhase (\r |
1369 | ControllerHandle,\r | |
1370 | Slot,\r | |
1371 | EdkiiSdMmcUhsSignaling,\r | |
1372 | &Timing\r | |
1373 | );\r | |
1374 | if (EFI_ERROR (Status)) {\r | |
1375 | DEBUG ((\r | |
1376 | DEBUG_ERROR,\r | |
1377 | "%a: SD/MMC uhs signaling notifier callback failed - %r\n",\r | |
1378 | __FUNCTION__,\r | |
1379 | Status\r | |
1380 | ));\r | |
1381 | return Status;\r | |
1382 | }\r | |
1383 | }\r | |
1384 | \r | |
1385 | return EFI_SUCCESS;\r | |
1386 | }\r | |
1387 | \r | |
adec1f5d AM |
1388 | /**\r |
1389 | Set driver strength in host controller.\r | |
1390 | \r | |
1391 | @param[in] PciIo The PCI IO protocol instance.\r | |
1392 | @param[in] SlotIndex The slot index of the card.\r | |
1393 | @param[in] DriverStrength DriverStrength to set in the controller.\r | |
1394 | \r | |
1395 | @retval EFI_SUCCESS Driver strength programmed successfully.\r | |
1396 | @retval Others Failed to set driver strength.\r | |
1397 | **/\r | |
1398 | EFI_STATUS\r | |
1399 | SdMmcSetDriverStrength (\r | |
1400 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1401 | IN UINT8 SlotIndex,\r | |
1402 | IN SD_DRIVER_STRENGTH_TYPE DriverStrength\r | |
1403 | )\r | |
1404 | {\r | |
1405 | EFI_STATUS Status;\r | |
1406 | UINT16 HostCtrl2;\r | |
1407 | \r | |
1408 | if (DriverStrength == SdDriverStrengthIgnore) {\r | |
1409 | return EFI_SUCCESS;\r | |
1410 | }\r | |
1411 | \r | |
1436aea4 MK |
1412 | HostCtrl2 = (UINT16) ~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;\r |
1413 | Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
adec1f5d AM |
1414 | if (EFI_ERROR (Status)) {\r |
1415 | return Status;\r | |
1416 | }\r | |
1417 | \r | |
1418 | HostCtrl2 = (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;\r | |
1419 | return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1420 | }\r | |
1421 | \r | |
48555339 FT |
1422 | /**\r |
1423 | Turn on/off LED.\r | |
1424 | \r | |
1425 | @param[in] PciIo The PCI IO protocol instance.\r | |
1426 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1427 | @param[in] On The boolean to turn on/off LED.\r | |
1428 | \r | |
1429 | @retval EFI_SUCCESS The LED is turned on/off successfully.\r | |
1430 | @retval Others The LED isn't turned on/off successfully.\r | |
1431 | \r | |
1432 | **/\r | |
1433 | EFI_STATUS\r | |
1434 | SdMmcHcLedOnOff (\r | |
1436aea4 MK |
1435 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
1436 | IN UINT8 Slot,\r | |
1437 | IN BOOLEAN On\r | |
48555339 FT |
1438 | )\r |
1439 | {\r | |
1436aea4 MK |
1440 | EFI_STATUS Status;\r |
1441 | UINT8 HostCtrl1;\r | |
48555339 FT |
1442 | \r |
1443 | if (On) {\r | |
1444 | HostCtrl1 = BIT0;\r | |
1445 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1446 | } else {\r | |
1436aea4 | 1447 | HostCtrl1 = (UINT8) ~BIT0;\r |
48555339 FT |
1448 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r |
1449 | }\r | |
1450 | \r | |
1451 | return Status;\r | |
1452 | }\r | |
1453 | \r | |
1454 | /**\r | |
1455 | Build ADMA descriptor table for transfer.\r | |
1456 | \r | |
b5547b9c | 1457 | Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.\r |
48555339 FT |
1458 | \r |
1459 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
b5547b9c | 1460 | @param[in] ControllerVer The version of host controller.\r |
48555339 FT |
1461 | \r |
1462 | @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r | |
1463 | @retval Others The ADMA descriptor table isn't created successfully.\r | |
1464 | \r | |
1465 | **/\r | |
1466 | EFI_STATUS\r | |
1467 | BuildAdmaDescTable (\r | |
1436aea4 MK |
1468 | IN SD_MMC_HC_TRB *Trb,\r |
1469 | IN UINT16 ControllerVer\r | |
48555339 FT |
1470 | )\r |
1471 | {\r | |
1436aea4 MK |
1472 | EFI_PHYSICAL_ADDRESS Data;\r |
1473 | UINT64 DataLen;\r | |
1474 | UINT64 Entries;\r | |
1475 | UINT32 Index;\r | |
1476 | UINT64 Remaining;\r | |
1477 | UINT64 Address;\r | |
1478 | UINTN TableSize;\r | |
1479 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1480 | EFI_STATUS Status;\r | |
1481 | UINTN Bytes;\r | |
1482 | UINT32 AdmaMaxDataPerLine;\r | |
1483 | UINT32 DescSize;\r | |
1484 | VOID *AdmaDesc;\r | |
b5547b9c | 1485 | \r |
b5547b9c AS |
1486 | AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;\r |
1487 | DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);\r | |
1488 | AdmaDesc = NULL;\r | |
48555339 FT |
1489 | \r |
1490 | Data = Trb->DataPhy;\r | |
1491 | DataLen = Trb->DataLen;\r | |
1492 | PciIo = Trb->Private->PciIo;\r | |
b5547b9c | 1493 | \r |
b5547b9c AS |
1494 | //\r |
1495 | // Check for valid ranges in 32bit ADMA Descriptor Table\r | |
1496 | //\r | |
690d60c0 | 1497 | if ((Trb->Mode == SdMmcAdma32bMode) &&\r |
1436aea4 MK |
1498 | ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)))\r |
1499 | {\r | |
48555339 FT |
1500 | return EFI_INVALID_PARAMETER;\r |
1501 | }\r | |
1436aea4 | 1502 | \r |
48555339 | 1503 | //\r |
b5547b9c | 1504 | // Check address field alignment\r |
48555339 | 1505 | //\r |
690d60c0 | 1506 | if (Trb->Mode != SdMmcAdma32bMode) {\r |
b5547b9c AS |
1507 | //\r |
1508 | // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)\r | |
1509 | //\r | |
1510 | if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {\r | |
1511 | DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));\r | |
1512 | }\r | |
1513 | } else {\r | |
1514 | //\r | |
1515 | // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r | |
1516 | //\r | |
1517 | if ((Data & (BIT0 | BIT1)) != 0) {\r | |
1518 | DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r | |
1519 | }\r | |
1520 | }\r | |
690d60c0 AS |
1521 | \r |
1522 | //\r | |
1523 | // Configure 64b ADMA.\r | |
b5547b9c | 1524 | //\r |
690d60c0 AS |
1525 | if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1526 | DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);\r | |
1436aea4 | 1527 | } else if (Trb->Mode == SdMmcAdma64bV4Mode) {\r |
690d60c0 AS |
1528 | DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);\r |
1529 | }\r | |
1436aea4 | 1530 | \r |
b5547b9c | 1531 | //\r |
690d60c0 AS |
1532 | // Configure 26b data length.\r |
1533 | //\r | |
1534 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
b5547b9c | 1535 | AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;\r |
48555339 FT |
1536 | }\r |
1537 | \r | |
1436aea4 MK |
1538 | Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);\r |
1539 | TableSize = (UINTN)MultU64x32 (Entries, DescSize);\r | |
48555339 | 1540 | Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r |
1436aea4 MK |
1541 | Status = PciIo->AllocateBuffer (\r |
1542 | PciIo,\r | |
1543 | AllocateAnyPages,\r | |
1544 | EfiBootServicesData,\r | |
1545 | EFI_SIZE_TO_PAGES (TableSize),\r | |
1546 | (VOID **)&AdmaDesc,\r | |
1547 | 0\r | |
1548 | );\r | |
48555339 FT |
1549 | if (EFI_ERROR (Status)) {\r |
1550 | return EFI_OUT_OF_RESOURCES;\r | |
1551 | }\r | |
1436aea4 | 1552 | \r |
b5547b9c | 1553 | ZeroMem (AdmaDesc, TableSize);\r |
48555339 FT |
1554 | Bytes = TableSize;\r |
1555 | Status = PciIo->Map (\r | |
1556 | PciIo,\r | |
1557 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
b5547b9c | 1558 | AdmaDesc,\r |
48555339 FT |
1559 | &Bytes,\r |
1560 | &Trb->AdmaDescPhy,\r | |
1561 | &Trb->AdmaMap\r | |
1562 | );\r | |
1563 | \r | |
1564 | if (EFI_ERROR (Status) || (Bytes != TableSize)) {\r | |
1565 | //\r | |
1566 | // Map error or unable to map the whole RFis buffer into a contiguous region.\r | |
1567 | //\r | |
1568 | PciIo->FreeBuffer (\r | |
1569 | PciIo,\r | |
1570 | EFI_SIZE_TO_PAGES (TableSize),\r | |
b5547b9c | 1571 | AdmaDesc\r |
48555339 FT |
1572 | );\r |
1573 | return EFI_OUT_OF_RESOURCES;\r | |
1574 | }\r | |
1575 | \r | |
690d60c0 | 1576 | if ((Trb->Mode == SdMmcAdma32bMode) &&\r |
1436aea4 MK |
1577 | ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul))\r |
1578 | {\r | |
48555339 FT |
1579 | //\r |
1580 | // The ADMA doesn't support 64bit addressing.\r | |
1581 | //\r | |
1582 | PciIo->Unmap (\r | |
1436aea4 MK |
1583 | PciIo,\r |
1584 | Trb->AdmaMap\r | |
1585 | );\r | |
e36d5ac7 HW |
1586 | Trb->AdmaMap = NULL;\r |
1587 | \r | |
48555339 | 1588 | PciIo->FreeBuffer (\r |
1436aea4 MK |
1589 | PciIo,\r |
1590 | EFI_SIZE_TO_PAGES (TableSize),\r | |
1591 | AdmaDesc\r | |
1592 | );\r | |
48555339 FT |
1593 | return EFI_DEVICE_ERROR;\r |
1594 | }\r | |
1595 | \r | |
1596 | Remaining = DataLen;\r | |
b5547b9c | 1597 | Address = Data;\r |
690d60c0 | 1598 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
b5547b9c | 1599 | Trb->Adma32Desc = AdmaDesc;\r |
690d60c0 AS |
1600 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1601 | Trb->Adma64V3Desc = AdmaDesc;\r | |
b5547b9c | 1602 | } else {\r |
690d60c0 | 1603 | Trb->Adma64V4Desc = AdmaDesc;\r |
b5547b9c | 1604 | }\r |
690d60c0 | 1605 | \r |
48555339 | 1606 | for (Index = 0; Index < Entries; Index++) {\r |
690d60c0 | 1607 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
b5547b9c AS |
1608 | if (Remaining <= AdmaMaxDataPerLine) {\r |
1609 | Trb->Adma32Desc[Index].Valid = 1;\r | |
1610 | Trb->Adma32Desc[Index].Act = 2;\r | |
690d60c0 | 1611 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r |
46f4c967 | 1612 | Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r |
b5547b9c | 1613 | }\r |
1436aea4 | 1614 | \r |
b5547b9c | 1615 | Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r |
1436aea4 | 1616 | Trb->Adma32Desc[Index].Address = (UINT32)Address;\r |
b5547b9c AS |
1617 | break;\r |
1618 | } else {\r | |
1619 | Trb->Adma32Desc[Index].Valid = 1;\r | |
1620 | Trb->Adma32Desc[Index].Act = 2;\r | |
690d60c0 | 1621 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r |
1436aea4 | 1622 | Trb->Adma32Desc[Index].UpperLength = 0;\r |
b5547b9c | 1623 | }\r |
1436aea4 MK |
1624 | \r |
1625 | Trb->Adma32Desc[Index].LowerLength = 0;\r | |
1626 | Trb->Adma32Desc[Index].Address = (UINT32)Address;\r | |
b5547b9c | 1627 | }\r |
690d60c0 AS |
1628 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1629 | if (Remaining <= AdmaMaxDataPerLine) {\r | |
1630 | Trb->Adma64V3Desc[Index].Valid = 1;\r | |
1631 | Trb->Adma64V3Desc[Index].Act = 2;\r | |
1632 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1436aea4 | 1633 | Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r |
690d60c0 | 1634 | }\r |
1436aea4 | 1635 | \r |
690d60c0 AS |
1636 | Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r |
1637 | Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r | |
1638 | Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
1639 | break;\r | |
1640 | } else {\r | |
1641 | Trb->Adma64V3Desc[Index].Valid = 1;\r | |
1642 | Trb->Adma64V3Desc[Index].Act = 2;\r | |
1643 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1436aea4 | 1644 | Trb->Adma64V3Desc[Index].UpperLength = 0;\r |
690d60c0 | 1645 | }\r |
1436aea4 | 1646 | \r |
690d60c0 AS |
1647 | Trb->Adma64V3Desc[Index].LowerLength = 0;\r |
1648 | Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r | |
1649 | Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
1650 | }\r | |
48555339 | 1651 | } else {\r |
b5547b9c | 1652 | if (Remaining <= AdmaMaxDataPerLine) {\r |
690d60c0 AS |
1653 | Trb->Adma64V4Desc[Index].Valid = 1;\r |
1654 | Trb->Adma64V4Desc[Index].Act = 2;\r | |
1655 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1436aea4 | 1656 | Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r |
b5547b9c | 1657 | }\r |
1436aea4 | 1658 | \r |
690d60c0 AS |
1659 | Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r |
1660 | Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r | |
1661 | Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
b5547b9c AS |
1662 | break;\r |
1663 | } else {\r | |
690d60c0 AS |
1664 | Trb->Adma64V4Desc[Index].Valid = 1;\r |
1665 | Trb->Adma64V4Desc[Index].Act = 2;\r | |
1666 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1436aea4 | 1667 | Trb->Adma64V4Desc[Index].UpperLength = 0;\r |
b5547b9c | 1668 | }\r |
1436aea4 | 1669 | \r |
690d60c0 AS |
1670 | Trb->Adma64V4Desc[Index].LowerLength = 0;\r |
1671 | Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r | |
1672 | Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
b5547b9c | 1673 | }\r |
48555339 FT |
1674 | }\r |
1675 | \r | |
b5547b9c AS |
1676 | Remaining -= AdmaMaxDataPerLine;\r |
1677 | Address += AdmaMaxDataPerLine;\r | |
48555339 FT |
1678 | }\r |
1679 | \r | |
1680 | //\r | |
1681 | // Set the last descriptor line as end of descriptor table\r | |
1682 | //\r | |
690d60c0 AS |
1683 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
1684 | Trb->Adma32Desc[Index].End = 1;\r | |
1685 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r | |
1686 | Trb->Adma64V3Desc[Index].End = 1;\r | |
1687 | } else {\r | |
1688 | Trb->Adma64V4Desc[Index].End = 1;\r | |
1689 | }\r | |
1436aea4 | 1690 | \r |
48555339 FT |
1691 | return EFI_SUCCESS;\r |
1692 | }\r | |
1693 | \r | |
9767a597 AM |
1694 | /**\r |
1695 | Prints the contents of the command packet to the debug port.\r | |
1696 | \r | |
1697 | @param[in] DebugLevel Debug level at which the packet should be printed.\r | |
1698 | @param[in] Packet Pointer to packet to print.\r | |
1699 | **/\r | |
1700 | VOID\r | |
1701 | SdMmcPrintPacket (\r | |
1702 | IN UINT32 DebugLevel,\r | |
1703 | IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet\r | |
1704 | )\r | |
1705 | {\r | |
1706 | if (Packet == NULL) {\r | |
1707 | return;\r | |
1708 | }\r | |
1709 | \r | |
1710 | DEBUG ((DebugLevel, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));\r | |
1711 | if (Packet->SdMmcCmdBlk != NULL) {\r | |
1712 | DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", Packet->SdMmcCmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument));\r | |
1713 | DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", Packet->SdMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType));\r | |
1714 | }\r | |
1436aea4 | 1715 | \r |
9767a597 | 1716 | if (Packet->SdMmcStatusBlk != NULL) {\r |
1436aea4 MK |
1717 | DEBUG ((\r |
1718 | DebugLevel,\r | |
1719 | "Response 0: %X, 1: %X, 2: %X, 3: %X\n",\r | |
1720 | Packet->SdMmcStatusBlk->Resp0,\r | |
1721 | Packet->SdMmcStatusBlk->Resp1,\r | |
1722 | Packet->SdMmcStatusBlk->Resp2,\r | |
1723 | Packet->SdMmcStatusBlk->Resp3\r | |
1724 | ));\r | |
9767a597 | 1725 | }\r |
1436aea4 | 1726 | \r |
9767a597 AM |
1727 | DEBUG ((DebugLevel, "Timeout: %ld\n", Packet->Timeout));\r |
1728 | DEBUG ((DebugLevel, "InDataBuffer: %p\n", Packet->InDataBuffer));\r | |
1729 | DEBUG ((DebugLevel, "OutDataBuffer: %p\n", Packet->OutDataBuffer));\r | |
1730 | DEBUG ((DebugLevel, "InTransferLength: %d\n", Packet->InTransferLength));\r | |
1731 | DEBUG ((DebugLevel, "OutTransferLength: %d\n", Packet->OutTransferLength));\r | |
1732 | DEBUG ((DebugLevel, "TransactionStatus: %r\n", Packet->TransactionStatus));\r | |
1733 | }\r | |
1734 | \r | |
1735 | /**\r | |
1736 | Prints the contents of the TRB to the debug port.\r | |
1737 | \r | |
1738 | @param[in] DebugLevel Debug level at which the TRB should be printed.\r | |
1739 | @param[in] Trb Pointer to the TRB structure.\r | |
1740 | **/\r | |
1741 | VOID\r | |
1742 | SdMmcPrintTrb (\r | |
1743 | IN UINT32 DebugLevel,\r | |
1744 | IN SD_MMC_HC_TRB *Trb\r | |
1745 | )\r | |
1746 | {\r | |
1747 | if (Trb == NULL) {\r | |
1748 | return;\r | |
1749 | }\r | |
1750 | \r | |
1751 | DEBUG ((DebugLevel, "Printing SD_MMC_HC_TRB\n"));\r | |
1752 | DEBUG ((DebugLevel, "Slot: %d\n", Trb->Slot));\r | |
1753 | DEBUG ((DebugLevel, "BlockSize: %d\n", Trb->BlockSize));\r | |
1754 | DEBUG ((DebugLevel, "Data: %p\n", Trb->Data));\r | |
1755 | DEBUG ((DebugLevel, "DataLen: %d\n", Trb->DataLen));\r | |
1756 | DEBUG ((DebugLevel, "Read: %d\n", Trb->Read));\r | |
1757 | DEBUG ((DebugLevel, "DataPhy: %lX\n", Trb->DataPhy));\r | |
1758 | DEBUG ((DebugLevel, "DataMap: %p\n", Trb->DataMap));\r | |
1759 | DEBUG ((DebugLevel, "Mode: %d\n", Trb->Mode));\r | |
1760 | DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));\r | |
1761 | DEBUG ((DebugLevel, "Event: %p\n", Trb->Event));\r | |
1762 | DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));\r | |
6d387610 | 1763 | DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));\r |
9767a597 AM |
1764 | DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));\r |
1765 | DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));\r | |
9bfaa3da AM |
1766 | DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", Trb->PioModeTransferCompleted));\r |
1767 | DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex));\r | |
9767a597 AM |
1768 | DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));\r |
1769 | DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc));\r | |
1770 | DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc));\r | |
1771 | DEBUG ((DebugLevel, "AdmaMap: %p\n", Trb->AdmaMap));\r | |
1772 | DEBUG ((DebugLevel, "AdmaPages: %X\n", Trb->AdmaPages));\r | |
1773 | \r | |
1774 | SdMmcPrintPacket (DebugLevel, Trb->Packet);\r | |
1775 | }\r | |
1776 | \r | |
63fd7f38 AM |
1777 | /**\r |
1778 | Sets up host memory to allow DMA transfer.\r | |
1779 | \r | |
1780 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1781 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1782 | @param[in] Packet A pointer to the SD command data structure.\r | |
1783 | \r | |
1784 | @retval EFI_SUCCESS Memory has been mapped for DMA transfer.\r | |
1785 | @retval Others Memory has not been mapped.\r | |
1786 | **/\r | |
1787 | EFI_STATUS\r | |
1788 | SdMmcSetupMemoryForDmaTransfer (\r | |
1789 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1790 | IN UINT8 Slot,\r | |
1791 | IN SD_MMC_HC_TRB *Trb\r | |
1792 | )\r | |
1793 | {\r | |
1436aea4 MK |
1794 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r |
1795 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1796 | UINTN MapLength;\r | |
1797 | EFI_STATUS Status;\r | |
63fd7f38 AM |
1798 | \r |
1799 | if (Trb->Read) {\r | |
1800 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
1801 | } else {\r | |
1802 | Flag = EfiPciIoOperationBusMasterRead;\r | |
1803 | }\r | |
1804 | \r | |
1805 | PciIo = Private->PciIo;\r | |
1436aea4 | 1806 | if ((Trb->Data != NULL) && (Trb->DataLen != 0)) {\r |
63fd7f38 | 1807 | MapLength = Trb->DataLen;\r |
1436aea4 MK |
1808 | Status = PciIo->Map (\r |
1809 | PciIo,\r | |
1810 | Flag,\r | |
1811 | Trb->Data,\r | |
1812 | &MapLength,\r | |
1813 | &Trb->DataPhy,\r | |
1814 | &Trb->DataMap\r | |
1815 | );\r | |
63fd7f38 AM |
1816 | if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {\r |
1817 | return EFI_BAD_BUFFER_SIZE;\r | |
1818 | }\r | |
1819 | }\r | |
1820 | \r | |
1436aea4 MK |
1821 | if ((Trb->Mode == SdMmcAdma32bMode) ||\r |
1822 | (Trb->Mode == SdMmcAdma64bV3Mode) ||\r | |
1823 | (Trb->Mode == SdMmcAdma64bV4Mode))\r | |
1824 | {\r | |
63fd7f38 AM |
1825 | Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);\r |
1826 | if (EFI_ERROR (Status)) {\r | |
1827 | return Status;\r | |
1828 | }\r | |
1829 | }\r | |
1830 | \r | |
1831 | return EFI_SUCCESS;\r | |
1832 | }\r | |
1833 | \r | |
48555339 FT |
1834 | /**\r |
1835 | Create a new TRB for the SD/MMC cmd request.\r | |
1836 | \r | |
1837 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1838 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1839 | @param[in] Packet A pointer to the SD command data structure.\r | |
1840 | @param[in] Event If Event is NULL, blocking I/O is performed. If Event is\r | |
1841 | not NULL, then nonblocking I/O is performed, and Event\r | |
1842 | will be signaled when the Packet completes.\r | |
1843 | \r | |
1844 | @return Created Trb or NULL.\r | |
1845 | \r | |
1846 | **/\r | |
1847 | SD_MMC_HC_TRB *\r | |
1848 | SdMmcCreateTrb (\r | |
1436aea4 MK |
1849 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
1850 | IN UINT8 Slot,\r | |
1851 | IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r | |
1852 | IN EFI_EVENT Event\r | |
48555339 FT |
1853 | )\r |
1854 | {\r | |
1436aea4 MK |
1855 | SD_MMC_HC_TRB *Trb;\r |
1856 | EFI_STATUS Status;\r | |
1857 | EFI_TPL OldTpl;\r | |
48555339 FT |
1858 | \r |
1859 | Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));\r | |
1860 | if (Trb == NULL) {\r | |
1861 | return NULL;\r | |
1862 | }\r | |
1863 | \r | |
1436aea4 MK |
1864 | Trb->Signature = SD_MMC_HC_TRB_SIG;\r |
1865 | Trb->Slot = Slot;\r | |
1866 | Trb->BlockSize = 0x200;\r | |
1867 | Trb->Packet = Packet;\r | |
1868 | Trb->Event = Event;\r | |
1869 | Trb->Started = FALSE;\r | |
1870 | Trb->CommandComplete = FALSE;\r | |
1871 | Trb->Timeout = Packet->Timeout;\r | |
1872 | Trb->Retries = SD_MMC_TRB_RETRIES;\r | |
9bfaa3da | 1873 | Trb->PioModeTransferCompleted = FALSE;\r |
1436aea4 MK |
1874 | Trb->PioBlockIndex = 0;\r |
1875 | Trb->Private = Private;\r | |
48555339 FT |
1876 | \r |
1877 | if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r | |
1878 | Trb->Data = Packet->InDataBuffer;\r | |
1879 | Trb->DataLen = Packet->InTransferLength;\r | |
1880 | Trb->Read = TRUE;\r | |
1881 | } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r | |
1882 | Trb->Data = Packet->OutDataBuffer;\r | |
1883 | Trb->DataLen = Packet->OutTransferLength;\r | |
1884 | Trb->Read = FALSE;\r | |
1885 | } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r | |
1886 | Trb->Data = NULL;\r | |
1887 | Trb->DataLen = 0;\r | |
1888 | } else {\r | |
1889 | goto Error;\r | |
1890 | }\r | |
1891 | \r | |
54228046 | 1892 | if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r |
e7e89b08 FT |
1893 | Trb->BlockSize = (UINT16)Trb->DataLen;\r |
1894 | }\r | |
1895 | \r | |
1896 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
1897 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
1898 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
1436aea4 MK |
1899 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK)))\r |
1900 | {\r | |
e7e89b08 | 1901 | Trb->Mode = SdMmcPioMode;\r |
48555339 | 1902 | } else {\r |
e7e89b08 FT |
1903 | if (Trb->DataLen == 0) {\r |
1904 | Trb->Mode = SdMmcNoData;\r | |
1905 | } else if (Private->Capability[Slot].Adma2 != 0) {\r | |
1436aea4 | 1906 | Trb->Mode = SdMmcAdma32bMode;\r |
690d60c0 AS |
1907 | Trb->AdmaLengthMode = SdMmcAdmaLen16b;\r |
1908 | if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&\r | |
1436aea4 MK |
1909 | (Private->Capability[Slot].SysBus64V3 == 1))\r |
1910 | {\r | |
690d60c0 AS |
1911 | Trb->Mode = SdMmcAdma64bV3Mode;\r |
1912 | } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&\r | |
1913 | (Private->Capability[Slot].SysBus64V3 == 1)) ||\r | |
1914 | ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&\r | |
1436aea4 MK |
1915 | (Private->Capability[Slot].SysBus64V4 == 1)))\r |
1916 | {\r | |
690d60c0 AS |
1917 | Trb->Mode = SdMmcAdma64bV4Mode;\r |
1918 | }\r | |
1436aea4 | 1919 | \r |
690d60c0 AS |
1920 | if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {\r |
1921 | Trb->AdmaLengthMode = SdMmcAdmaLen26b;\r | |
1922 | }\r | |
1436aea4 | 1923 | \r |
63fd7f38 | 1924 | Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);\r |
e7e89b08 | 1925 | if (EFI_ERROR (Status)) {\r |
e7e89b08 FT |
1926 | goto Error;\r |
1927 | }\r | |
1928 | } else if (Private->Capability[Slot].Sdma != 0) {\r | |
1929 | Trb->Mode = SdMmcSdmaMode;\r | |
1436aea4 | 1930 | Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);\r |
63fd7f38 AM |
1931 | if (EFI_ERROR (Status)) {\r |
1932 | goto Error;\r | |
1933 | }\r | |
e7e89b08 FT |
1934 | } else {\r |
1935 | Trb->Mode = SdMmcPioMode;\r | |
48555339 | 1936 | }\r |
48555339 FT |
1937 | }\r |
1938 | \r | |
1939 | if (Event != NULL) {\r | |
3b1d8241 | 1940 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r |
48555339 FT |
1941 | InsertTailList (&Private->Queue, &Trb->TrbList);\r |
1942 | gBS->RestoreTPL (OldTpl);\r | |
1943 | }\r | |
1944 | \r | |
1945 | return Trb;\r | |
1946 | \r | |
1947 | Error:\r | |
1948 | SdMmcFreeTrb (Trb);\r | |
1949 | return NULL;\r | |
1950 | }\r | |
1951 | \r | |
1952 | /**\r | |
1953 | Free the resource used by the TRB.\r | |
1954 | \r | |
1955 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1956 | \r | |
1957 | **/\r | |
1958 | VOID\r | |
1959 | SdMmcFreeTrb (\r | |
1436aea4 | 1960 | IN SD_MMC_HC_TRB *Trb\r |
48555339 FT |
1961 | )\r |
1962 | {\r | |
1436aea4 | 1963 | EFI_PCI_IO_PROTOCOL *PciIo;\r |
48555339 FT |
1964 | \r |
1965 | PciIo = Trb->Private->PciIo;\r | |
1966 | \r | |
1967 | if (Trb->AdmaMap != NULL) {\r | |
1968 | PciIo->Unmap (\r | |
1436aea4 MK |
1969 | PciIo,\r |
1970 | Trb->AdmaMap\r | |
1971 | );\r | |
48555339 | 1972 | }\r |
1436aea4 | 1973 | \r |
b5547b9c AS |
1974 | if (Trb->Adma32Desc != NULL) {\r |
1975 | PciIo->FreeBuffer (\r | |
1436aea4 MK |
1976 | PciIo,\r |
1977 | Trb->AdmaPages,\r | |
1978 | Trb->Adma32Desc\r | |
1979 | );\r | |
b5547b9c | 1980 | }\r |
1436aea4 | 1981 | \r |
690d60c0 | 1982 | if (Trb->Adma64V3Desc != NULL) {\r |
48555339 | 1983 | PciIo->FreeBuffer (\r |
1436aea4 MK |
1984 | PciIo,\r |
1985 | Trb->AdmaPages,\r | |
1986 | Trb->Adma64V3Desc\r | |
1987 | );\r | |
690d60c0 | 1988 | }\r |
1436aea4 | 1989 | \r |
690d60c0 AS |
1990 | if (Trb->Adma64V4Desc != NULL) {\r |
1991 | PciIo->FreeBuffer (\r | |
1436aea4 MK |
1992 | PciIo,\r |
1993 | Trb->AdmaPages,\r | |
1994 | Trb->Adma64V4Desc\r | |
1995 | );\r | |
48555339 | 1996 | }\r |
1436aea4 | 1997 | \r |
48555339 FT |
1998 | if (Trb->DataMap != NULL) {\r |
1999 | PciIo->Unmap (\r | |
1436aea4 MK |
2000 | PciIo,\r |
2001 | Trb->DataMap\r | |
2002 | );\r | |
48555339 | 2003 | }\r |
1436aea4 | 2004 | \r |
48555339 FT |
2005 | FreePool (Trb);\r |
2006 | return;\r | |
2007 | }\r | |
2008 | \r | |
2009 | /**\r | |
2010 | Check if the env is ready for execute specified TRB.\r | |
2011 | \r | |
2012 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2013 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2014 | \r | |
2015 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
2016 | @retval EFI_NOT_READY The env is not ready for TRB execution.\r | |
2017 | @retval Others Some erros happen.\r | |
2018 | \r | |
2019 | **/\r | |
2020 | EFI_STATUS\r | |
2021 | SdMmcCheckTrbEnv (\r | |
1436aea4 MK |
2022 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
2023 | IN SD_MMC_HC_TRB *Trb\r | |
48555339 FT |
2024 | )\r |
2025 | {\r | |
1436aea4 MK |
2026 | EFI_STATUS Status;\r |
2027 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2028 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
2029 | UINT32 PresentState;\r | |
48555339 FT |
2030 | \r |
2031 | Packet = Trb->Packet;\r | |
2032 | \r | |
2033 | if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r | |
2034 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r | |
1436aea4 MK |
2035 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b))\r |
2036 | {\r | |
48555339 FT |
2037 | //\r |
2038 | // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r | |
2039 | // the Present State register to be 0\r | |
2040 | //\r | |
2041 | PresentState = BIT0 | BIT1;\r | |
48555339 FT |
2042 | } else {\r |
2043 | //\r | |
2044 | // Wait Command Inhibit (CMD) in the Present State register\r | |
2045 | // to be 0\r | |
2046 | //\r | |
2047 | PresentState = BIT0;\r | |
2048 | }\r | |
2049 | \r | |
2050 | PciIo = Private->PciIo;\r | |
2051 | Status = SdMmcHcCheckMmioSet (\r | |
2052 | PciIo,\r | |
2053 | Trb->Slot,\r | |
2054 | SD_MMC_HC_PRESENT_STATE,\r | |
2055 | sizeof (PresentState),\r | |
2056 | PresentState,\r | |
2057 | 0\r | |
2058 | );\r | |
2059 | \r | |
2060 | return Status;\r | |
2061 | }\r | |
2062 | \r | |
2063 | /**\r | |
2064 | Wait for the env to be ready for execute specified TRB.\r | |
2065 | \r | |
2066 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2067 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2068 | \r | |
2069 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
2070 | @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r | |
2071 | @retval Others Some erros happen.\r | |
2072 | \r | |
2073 | **/\r | |
2074 | EFI_STATUS\r | |
2075 | SdMmcWaitTrbEnv (\r | |
1436aea4 MK |
2076 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
2077 | IN SD_MMC_HC_TRB *Trb\r | |
48555339 FT |
2078 | )\r |
2079 | {\r | |
1436aea4 MK |
2080 | EFI_STATUS Status;\r |
2081 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2082 | UINT64 Timeout;\r | |
2083 | BOOLEAN InfiniteWait;\r | |
48555339 FT |
2084 | \r |
2085 | //\r | |
2086 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
2087 | //\r | |
2088 | Packet = Trb->Packet;\r | |
2089 | Timeout = Packet->Timeout;\r | |
2090 | if (Timeout == 0) {\r | |
2091 | InfiniteWait = TRUE;\r | |
2092 | } else {\r | |
2093 | InfiniteWait = FALSE;\r | |
2094 | }\r | |
2095 | \r | |
2096 | while (InfiniteWait || (Timeout > 0)) {\r | |
2097 | //\r | |
2098 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2099 | //\r | |
2100 | Status = SdMmcCheckTrbEnv (Private, Trb);\r | |
2101 | if (Status != EFI_NOT_READY) {\r | |
2102 | return Status;\r | |
2103 | }\r | |
1436aea4 | 2104 | \r |
48555339 FT |
2105 | //\r |
2106 | // Stall for 1 microsecond.\r | |
2107 | //\r | |
2108 | gBS->Stall (1);\r | |
2109 | \r | |
2110 | Timeout--;\r | |
2111 | }\r | |
2112 | \r | |
2113 | return EFI_TIMEOUT;\r | |
2114 | }\r | |
2115 | \r | |
2116 | /**\r | |
2117 | Execute the specified TRB.\r | |
2118 | \r | |
2119 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2120 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2121 | \r | |
2122 | @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r | |
2123 | @retval Others Some erros happen when sending this request to the host controller.\r | |
2124 | \r | |
2125 | **/\r | |
2126 | EFI_STATUS\r | |
2127 | SdMmcExecTrb (\r | |
1436aea4 MK |
2128 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
2129 | IN SD_MMC_HC_TRB *Trb\r | |
48555339 FT |
2130 | )\r |
2131 | {\r | |
1436aea4 MK |
2132 | EFI_STATUS Status;\r |
2133 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2134 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
2135 | UINT16 Cmd;\r | |
2136 | UINT16 IntStatus;\r | |
2137 | UINT32 Argument;\r | |
2138 | UINT32 BlkCount;\r | |
2139 | UINT16 BlkSize;\r | |
2140 | UINT16 TransMode;\r | |
2141 | UINT8 HostCtrl1;\r | |
2142 | UINT64 SdmaAddr;\r | |
2143 | UINT64 AdmaAddr;\r | |
2144 | BOOLEAN AddressingMode64;\r | |
b5547b9c AS |
2145 | \r |
2146 | AddressingMode64 = FALSE;\r | |
48555339 FT |
2147 | \r |
2148 | Packet = Trb->Packet;\r | |
2149 | PciIo = Trb->Private->PciIo;\r | |
2150 | //\r | |
2151 | // Clear all bits in Error Interrupt Status Register\r | |
2152 | //\r | |
2153 | IntStatus = 0xFFFF;\r | |
2154 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
2155 | if (EFI_ERROR (Status)) {\r | |
2156 | return Status;\r | |
2157 | }\r | |
1436aea4 | 2158 | \r |
48555339 FT |
2159 | //\r |
2160 | // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.\r | |
2161 | //\r | |
2162 | IntStatus = 0xFF3F;\r | |
2163 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
2164 | if (EFI_ERROR (Status)) {\r | |
2165 | return Status;\r | |
2166 | }\r | |
690d60c0 AS |
2167 | \r |
2168 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
1436aea4 MK |
2169 | Status = SdMmcHcCheckMmioSet (\r |
2170 | PciIo,\r | |
2171 | Trb->Slot,\r | |
2172 | SD_MMC_HC_HOST_CTRL2,\r | |
2173 | sizeof (UINT16),\r | |
2174 | SD_MMC_HC_64_ADDR_EN,\r | |
2175 | SD_MMC_HC_64_ADDR_EN\r | |
2176 | );\r | |
690d60c0 AS |
2177 | if (!EFI_ERROR (Status)) {\r |
2178 | AddressingMode64 = TRUE;\r | |
2179 | }\r | |
2180 | }\r | |
2181 | \r | |
48555339 FT |
2182 | //\r |
2183 | // Set Host Control 1 register DMA Select field\r | |
2184 | //\r | |
690d60c0 | 2185 | if ((Trb->Mode == SdMmcAdma32bMode) ||\r |
1436aea4 MK |
2186 | (Trb->Mode == SdMmcAdma64bV4Mode))\r |
2187 | {\r | |
48555339 | 2188 | HostCtrl1 = BIT4;\r |
1436aea4 | 2189 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r |
48555339 FT |
2190 | if (EFI_ERROR (Status)) {\r |
2191 | return Status;\r | |
2192 | }\r | |
690d60c0 AS |
2193 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
2194 | HostCtrl1 = BIT4|BIT3;\r | |
1436aea4 | 2195 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r |
690d60c0 AS |
2196 | if (EFI_ERROR (Status)) {\r |
2197 | return Status;\r | |
2198 | }\r | |
48555339 FT |
2199 | }\r |
2200 | \r | |
2201 | SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r | |
2202 | \r | |
2203 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
b5547b9c | 2204 | if ((!AddressingMode64) &&\r |
1436aea4 MK |
2205 | ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul))\r |
2206 | {\r | |
48555339 FT |
2207 | return EFI_INVALID_PARAMETER;\r |
2208 | }\r | |
2209 | \r | |
b5547b9c AS |
2210 | SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;\r |
2211 | \r | |
2212 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
2213 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);\r | |
2214 | } else {\r | |
2215 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);\r | |
2216 | }\r | |
2217 | \r | |
48555339 FT |
2218 | if (EFI_ERROR (Status)) {\r |
2219 | return Status;\r | |
2220 | }\r | |
690d60c0 AS |
2221 | } else if ((Trb->Mode == SdMmcAdma32bMode) ||\r |
2222 | (Trb->Mode == SdMmcAdma64bV3Mode) ||\r | |
1436aea4 MK |
2223 | (Trb->Mode == SdMmcAdma64bV4Mode))\r |
2224 | {\r | |
48555339 FT |
2225 | AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;\r |
2226 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r | |
2227 | if (EFI_ERROR (Status)) {\r | |
2228 | return Status;\r | |
2229 | }\r | |
2230 | }\r | |
2231 | \r | |
2232 | BlkSize = Trb->BlockSize;\r | |
2233 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
2234 | //\r | |
2235 | // Set SDMA boundary to be 512K bytes.\r | |
2236 | //\r | |
2237 | BlkSize |= 0x7000;\r | |
2238 | }\r | |
2239 | \r | |
2240 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r | |
2241 | if (EFI_ERROR (Status)) {\r | |
2242 | return Status;\r | |
2243 | }\r | |
2244 | \r | |
e7e89b08 FT |
2245 | BlkCount = 0;\r |
2246 | if (Trb->Mode != SdMmcNoData) {\r | |
2247 | //\r | |
2248 | // Calcuate Block Count.\r | |
2249 | //\r | |
b5547b9c AS |
2250 | BlkCount = (Trb->DataLen / Trb->BlockSize);\r |
2251 | }\r | |
1436aea4 | 2252 | \r |
b5547b9c AS |
2253 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {\r |
2254 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);\r | |
2255 | } else {\r | |
2256 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);\r | |
e7e89b08 | 2257 | }\r |
1436aea4 | 2258 | \r |
48555339 FT |
2259 | if (EFI_ERROR (Status)) {\r |
2260 | return Status;\r | |
2261 | }\r | |
2262 | \r | |
2263 | Argument = Packet->SdMmcCmdBlk->CommandArgument;\r | |
2264 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r | |
2265 | if (EFI_ERROR (Status)) {\r | |
2266 | return Status;\r | |
2267 | }\r | |
2268 | \r | |
2269 | TransMode = 0;\r | |
2270 | if (Trb->Mode != SdMmcNoData) {\r | |
2271 | if (Trb->Mode != SdMmcPioMode) {\r | |
2272 | TransMode |= BIT0;\r | |
2273 | }\r | |
1436aea4 | 2274 | \r |
48555339 FT |
2275 | if (Trb->Read) {\r |
2276 | TransMode |= BIT4;\r | |
2277 | }\r | |
1436aea4 | 2278 | \r |
e7e89b08 | 2279 | if (BlkCount > 1) {\r |
48555339 FT |
2280 | TransMode |= BIT5 | BIT1;\r |
2281 | }\r | |
1436aea4 | 2282 | \r |
48555339 FT |
2283 | //\r |
2284 | // Only SD memory card needs to use AUTO CMD12 feature.\r | |
2285 | //\r | |
2286 | if (Private->Slot[Trb->Slot].CardType == SdCardType) {\r | |
2287 | if (BlkCount > 1) {\r | |
2288 | TransMode |= BIT2;\r | |
2289 | }\r | |
2290 | }\r | |
2291 | }\r | |
2292 | \r | |
2293 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r | |
2294 | if (EFI_ERROR (Status)) {\r | |
2295 | return Status;\r | |
2296 | }\r | |
2297 | \r | |
1436aea4 | 2298 | Cmd = (UINT16)LShiftU64 (Packet->SdMmcCmdBlk->CommandIndex, 8);\r |
48555339 FT |
2299 | if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {\r |
2300 | Cmd |= BIT5;\r | |
2301 | }\r | |
1436aea4 | 2302 | \r |
48555339 FT |
2303 | //\r |
2304 | // Convert ResponseType to value\r | |
2305 | //\r | |
2306 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
2307 | switch (Packet->SdMmcCmdBlk->ResponseType) {\r | |
2308 | case SdMmcResponseTypeR1:\r | |
2309 | case SdMmcResponseTypeR5:\r | |
2310 | case SdMmcResponseTypeR6:\r | |
2311 | case SdMmcResponseTypeR7:\r | |
2312 | Cmd |= (BIT1 | BIT3 | BIT4);\r | |
2313 | break;\r | |
2314 | case SdMmcResponseTypeR2:\r | |
2315 | Cmd |= (BIT0 | BIT3);\r | |
1436aea4 | 2316 | break;\r |
48555339 FT |
2317 | case SdMmcResponseTypeR3:\r |
2318 | case SdMmcResponseTypeR4:\r | |
2319 | Cmd |= BIT1;\r | |
2320 | break;\r | |
2321 | case SdMmcResponseTypeR1b:\r | |
2322 | case SdMmcResponseTypeR5b:\r | |
2323 | Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r | |
2324 | break;\r | |
2325 | default:\r | |
2326 | ASSERT (FALSE);\r | |
2327 | break;\r | |
2328 | }\r | |
2329 | }\r | |
1436aea4 | 2330 | \r |
48555339 FT |
2331 | //\r |
2332 | // Execute cmd\r | |
2333 | //\r | |
2334 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r | |
2335 | return Status;\r | |
2336 | }\r | |
2337 | \r | |
a22f4c34 AM |
2338 | /**\r |
2339 | Performs SW reset based on passed error status mask.\r | |
2340 | \r | |
2341 | @param[in] Private Pointer to driver private data.\r | |
2342 | @param[in] Slot Index of the slot to reset.\r | |
2343 | @param[in] ErrIntStatus Error interrupt status mask.\r | |
2344 | \r | |
2345 | @retval EFI_SUCCESS Software reset performed successfully.\r | |
2346 | @retval Other Software reset failed.\r | |
2347 | **/\r | |
2348 | EFI_STATUS\r | |
2349 | SdMmcSoftwareReset (\r | |
2350 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2351 | IN UINT8 Slot,\r | |
2352 | IN UINT16 ErrIntStatus\r | |
2353 | )\r | |
2354 | {\r | |
2355 | UINT8 SwReset;\r | |
2356 | EFI_STATUS Status;\r | |
2357 | \r | |
2358 | SwReset = 0;\r | |
2359 | if ((ErrIntStatus & 0x0F) != 0) {\r | |
2360 | SwReset |= BIT1;\r | |
2361 | }\r | |
1436aea4 | 2362 | \r |
a22f4c34 AM |
2363 | if ((ErrIntStatus & 0x70) != 0) {\r |
2364 | SwReset |= BIT2;\r | |
2365 | }\r | |
2366 | \r | |
1436aea4 MK |
2367 | Status = SdMmcHcRwMmio (\r |
2368 | Private->PciIo,\r | |
2369 | Slot,\r | |
2370 | SD_MMC_HC_SW_RST,\r | |
2371 | FALSE,\r | |
2372 | sizeof (SwReset),\r | |
2373 | &SwReset\r | |
2374 | );\r | |
a22f4c34 AM |
2375 | if (EFI_ERROR (Status)) {\r |
2376 | return Status;\r | |
2377 | }\r | |
2378 | \r | |
2379 | Status = SdMmcHcWaitMmioSet (\r | |
2380 | Private->PciIo,\r | |
2381 | Slot,\r | |
2382 | SD_MMC_HC_SW_RST,\r | |
2383 | sizeof (SwReset),\r | |
2384 | 0xFF,\r | |
2385 | 0,\r | |
2386 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
2387 | );\r | |
2388 | if (EFI_ERROR (Status)) {\r | |
2389 | return Status;\r | |
2390 | }\r | |
2391 | \r | |
2392 | return EFI_SUCCESS;\r | |
2393 | }\r | |
2394 | \r | |
2395 | /**\r | |
2396 | Checks the error status in error status register\r | |
2397 | and issues appropriate software reset as described in\r | |
2398 | SD specification section 3.10.\r | |
2399 | \r | |
2400 | @param[in] Private Pointer to driver private data.\r | |
1e947f9b | 2401 | @param[in] Slot Index of the slot for device.\r |
a22f4c34 AM |
2402 | @param[in] IntStatus Normal interrupt status mask.\r |
2403 | \r | |
2404 | @retval EFI_CRC_ERROR CRC error happened during CMD execution.\r | |
2405 | @retval EFI_SUCCESS No error reported.\r | |
2406 | @retval Others Some other error happened.\r | |
2407 | \r | |
2408 | **/\r | |
2409 | EFI_STATUS\r | |
2410 | SdMmcCheckAndRecoverErrors (\r | |
2411 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2412 | IN UINT8 Slot,\r | |
2413 | IN UINT16 IntStatus\r | |
2414 | )\r | |
2415 | {\r | |
2416 | UINT16 ErrIntStatus;\r | |
2417 | EFI_STATUS Status;\r | |
2418 | EFI_STATUS ErrorStatus;\r | |
2419 | \r | |
2420 | if ((IntStatus & BIT15) == 0) {\r | |
2421 | return EFI_SUCCESS;\r | |
2422 | }\r | |
2423 | \r | |
2424 | Status = SdMmcHcRwMmio (\r | |
2425 | Private->PciIo,\r | |
2426 | Slot,\r | |
2427 | SD_MMC_HC_ERR_INT_STS,\r | |
2428 | TRUE,\r | |
2429 | sizeof (ErrIntStatus),\r | |
2430 | &ErrIntStatus\r | |
2431 | );\r | |
2432 | if (EFI_ERROR (Status)) {\r | |
2433 | return Status;\r | |
2434 | }\r | |
2435 | \r | |
9767a597 AM |
2436 | DEBUG ((DEBUG_ERROR, "Error reported by SDHCI\n"));\r |
2437 | DEBUG ((DEBUG_ERROR, "Interrupt status = %X\n", IntStatus));\r | |
2438 | DEBUG ((DEBUG_ERROR, "Error interrupt status = %X\n", ErrIntStatus));\r | |
2439 | \r | |
a22f4c34 AM |
2440 | //\r |
2441 | // If the data timeout error is reported\r | |
2442 | // but data transfer is signaled as completed we\r | |
2443 | // have to ignore data timeout. We also assume that no\r | |
2444 | // other error is present on the link since data transfer\r | |
2445 | // completed successfully. Error interrupt status\r | |
2446 | // register is going to be reset when the next command\r | |
2447 | // is started.\r | |
2448 | //\r | |
2449 | if (((ErrIntStatus & BIT4) != 0) && ((IntStatus & BIT1) != 0)) {\r | |
2450 | return EFI_SUCCESS;\r | |
2451 | }\r | |
2452 | \r | |
2453 | //\r | |
2454 | // We treat both CMD and DAT CRC errors and\r | |
2455 | // end bits errors as EFI_CRC_ERROR. This will\r | |
2456 | // let higher layer know that the error possibly\r | |
2457 | // happened due to random bus condition and the\r | |
2458 | // command can be retried.\r | |
2459 | //\r | |
2460 | if ((ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) != 0) {\r | |
2461 | ErrorStatus = EFI_CRC_ERROR;\r | |
2462 | } else {\r | |
2463 | ErrorStatus = EFI_DEVICE_ERROR;\r | |
2464 | }\r | |
2465 | \r | |
2466 | Status = SdMmcSoftwareReset (Private, Slot, ErrIntStatus);\r | |
2467 | if (EFI_ERROR (Status)) {\r | |
2468 | return Status;\r | |
2469 | }\r | |
2470 | \r | |
2471 | return ErrorStatus;\r | |
2472 | }\r | |
2473 | \r | |
6d387610 AM |
2474 | /**\r |
2475 | Reads the response data into the TRB buffer.\r | |
2476 | This function assumes that caller made sure that\r | |
2477 | command has completed.\r | |
2478 | \r | |
2479 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2480 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2481 | \r | |
2482 | @retval EFI_SUCCESS Response read successfully.\r | |
2483 | @retval Others Failed to get response.\r | |
2484 | **/\r | |
2485 | EFI_STATUS\r | |
2486 | SdMmcGetResponse (\r | |
2487 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2488 | IN SD_MMC_HC_TRB *Trb\r | |
2489 | )\r | |
2490 | {\r | |
2491 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2492 | UINT8 Index;\r | |
2493 | UINT32 Response[4];\r | |
2494 | EFI_STATUS Status;\r | |
2495 | \r | |
2496 | Packet = Trb->Packet;\r | |
2497 | \r | |
2498 | if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeBc) {\r | |
2499 | return EFI_SUCCESS;\r | |
2500 | }\r | |
2501 | \r | |
2502 | for (Index = 0; Index < 4; Index++) {\r | |
2503 | Status = SdMmcHcRwMmio (\r | |
2504 | Private->PciIo,\r | |
2505 | Trb->Slot,\r | |
2506 | SD_MMC_HC_RESPONSE + Index * 4,\r | |
2507 | TRUE,\r | |
2508 | sizeof (UINT32),\r | |
2509 | &Response[Index]\r | |
2510 | );\r | |
1436aea4 MK |
2511 | if (EFI_ERROR (Status)) {\r |
2512 | return Status;\r | |
6d387610 | 2513 | }\r |
1436aea4 MK |
2514 | }\r |
2515 | \r | |
6d387610 AM |
2516 | CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));\r |
2517 | \r | |
2518 | return EFI_SUCCESS;\r | |
2519 | }\r | |
2520 | \r | |
2521 | /**\r | |
2522 | Checks if the command completed. If the command\r | |
2523 | completed it gets the response and records the\r | |
2524 | command completion in the TRB.\r | |
2525 | \r | |
2526 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2527 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2528 | @param[in] IntStatus Snapshot of the normal interrupt status register.\r | |
2529 | \r | |
2530 | @retval EFI_SUCCESS Command completed successfully.\r | |
2531 | @retval EFI_NOT_READY Command completion still pending.\r | |
2532 | @retval Others Command failed to complete.\r | |
2533 | **/\r | |
2534 | EFI_STATUS\r | |
2535 | SdMmcCheckCommandComplete (\r | |
2536 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2537 | IN SD_MMC_HC_TRB *Trb,\r | |
2538 | IN UINT16 IntStatus\r | |
2539 | )\r | |
2540 | {\r | |
2541 | UINT16 Data16;\r | |
2542 | EFI_STATUS Status;\r | |
2543 | \r | |
2544 | if ((IntStatus & BIT0) != 0) {\r | |
2545 | Data16 = BIT0;\r | |
2546 | Status = SdMmcHcRwMmio (\r | |
2547 | Private->PciIo,\r | |
2548 | Trb->Slot,\r | |
2549 | SD_MMC_HC_NOR_INT_STS,\r | |
2550 | FALSE,\r | |
2551 | sizeof (Data16),\r | |
2552 | &Data16\r | |
2553 | );\r | |
2554 | if (EFI_ERROR (Status)) {\r | |
2555 | return Status;\r | |
2556 | }\r | |
1436aea4 | 2557 | \r |
6d387610 AM |
2558 | Status = SdMmcGetResponse (Private, Trb);\r |
2559 | if (EFI_ERROR (Status)) {\r | |
2560 | return Status;\r | |
2561 | }\r | |
1436aea4 | 2562 | \r |
6d387610 AM |
2563 | Trb->CommandComplete = TRUE;\r |
2564 | return EFI_SUCCESS;\r | |
2565 | }\r | |
2566 | \r | |
2567 | return EFI_NOT_READY;\r | |
2568 | }\r | |
2569 | \r | |
9bfaa3da AM |
2570 | /**\r |
2571 | Transfers data from card using PIO method.\r | |
2572 | \r | |
2573 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2574 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2575 | @param[in] IntStatus Snapshot of the normal interrupt status register.\r | |
2576 | \r | |
2577 | @retval EFI_SUCCESS PIO transfer completed successfully.\r | |
2578 | @retval EFI_NOT_READY PIO transfer completion still pending.\r | |
2579 | @retval Others PIO transfer failed to complete.\r | |
2580 | **/\r | |
2581 | EFI_STATUS\r | |
2582 | SdMmcTransferDataWithPio (\r | |
2583 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2584 | IN SD_MMC_HC_TRB *Trb,\r | |
2585 | IN UINT16 IntStatus\r | |
2586 | )\r | |
2587 | {\r | |
1436aea4 MK |
2588 | EFI_STATUS Status;\r |
2589 | UINT16 Data16;\r | |
2590 | UINT32 BlockCount;\r | |
9bfaa3da | 2591 | EFI_PCI_IO_PROTOCOL_WIDTH Width;\r |
1436aea4 | 2592 | UINTN Count;\r |
9bfaa3da AM |
2593 | \r |
2594 | BlockCount = (Trb->DataLen / Trb->BlockSize);\r | |
2595 | if (Trb->DataLen % Trb->BlockSize != 0) {\r | |
2596 | BlockCount += 1;\r | |
2597 | }\r | |
2598 | \r | |
2599 | if (Trb->PioBlockIndex >= BlockCount) {\r | |
2600 | return EFI_SUCCESS;\r | |
2601 | }\r | |
2602 | \r | |
2603 | switch (Trb->BlockSize % sizeof (UINT32)) {\r | |
2604 | case 0:\r | |
2605 | Width = EfiPciIoWidthFifoUint32;\r | |
2606 | Count = Trb->BlockSize / sizeof (UINT32);\r | |
2607 | break;\r | |
2608 | case 2:\r | |
2609 | Width = EfiPciIoWidthFifoUint16;\r | |
2610 | Count = Trb->BlockSize / sizeof (UINT16);\r | |
2611 | break;\r | |
2612 | case 1:\r | |
2613 | case 3:\r | |
2614 | default:\r | |
2615 | Width = EfiPciIoWidthFifoUint8;\r | |
2616 | Count = Trb->BlockSize;\r | |
2617 | break;\r | |
1436aea4 | 2618 | }\r |
9bfaa3da AM |
2619 | \r |
2620 | if (Trb->Read) {\r | |
2621 | if ((IntStatus & BIT5) == 0) {\r | |
2622 | return EFI_NOT_READY;\r | |
2623 | }\r | |
1436aea4 | 2624 | \r |
9bfaa3da AM |
2625 | Data16 = BIT5;\r |
2626 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16);\r | |
2627 | \r | |
2628 | Status = Private->PciIo->Mem.Read (\r | |
1436aea4 MK |
2629 | Private->PciIo,\r |
2630 | Width,\r | |
2631 | Trb->Slot,\r | |
2632 | SD_MMC_HC_BUF_DAT_PORT,\r | |
2633 | Count,\r | |
2634 | (VOID *)((UINT8 *)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))\r | |
2635 | );\r | |
9bfaa3da AM |
2636 | if (EFI_ERROR (Status)) {\r |
2637 | return Status;\r | |
2638 | }\r | |
1436aea4 | 2639 | \r |
9bfaa3da AM |
2640 | Trb->PioBlockIndex++;\r |
2641 | } else {\r | |
2642 | if ((IntStatus & BIT4) == 0) {\r | |
2643 | return EFI_NOT_READY;\r | |
2644 | }\r | |
1436aea4 | 2645 | \r |
9bfaa3da AM |
2646 | Data16 = BIT4;\r |
2647 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16);\r | |
2648 | \r | |
2649 | Status = Private->PciIo->Mem.Write (\r | |
1436aea4 MK |
2650 | Private->PciIo,\r |
2651 | Width,\r | |
2652 | Trb->Slot,\r | |
2653 | SD_MMC_HC_BUF_DAT_PORT,\r | |
2654 | Count,\r | |
2655 | (VOID *)((UINT8 *)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))\r | |
2656 | );\r | |
9bfaa3da AM |
2657 | if (EFI_ERROR (Status)) {\r |
2658 | return Status;\r | |
2659 | }\r | |
1436aea4 | 2660 | \r |
9bfaa3da AM |
2661 | Trb->PioBlockIndex++;\r |
2662 | }\r | |
2663 | \r | |
2664 | if (Trb->PioBlockIndex >= BlockCount) {\r | |
2665 | Trb->PioModeTransferCompleted = TRUE;\r | |
2666 | return EFI_SUCCESS;\r | |
2667 | } else {\r | |
2668 | return EFI_NOT_READY;\r | |
2669 | }\r | |
2670 | }\r | |
2671 | \r | |
7d48d20a AM |
2672 | /**\r |
2673 | Update the SDMA address on the SDMA buffer boundary interrupt.\r | |
2674 | \r | |
2675 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2676 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2677 | \r | |
2678 | @retval EFI_SUCCESS Updated SDMA buffer address.\r | |
2679 | @retval Others Failed to update SDMA buffer address.\r | |
2680 | **/\r | |
2681 | EFI_STATUS\r | |
2682 | SdMmcUpdateSdmaAddress (\r | |
2683 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2684 | IN SD_MMC_HC_TRB *Trb\r | |
2685 | )\r | |
2686 | {\r | |
2687 | UINT64 SdmaAddr;\r | |
2688 | EFI_STATUS Status;\r | |
2689 | \r | |
2690 | SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r | |
2691 | \r | |
2692 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
2693 | Status = SdMmcHcRwMmio (\r | |
2694 | Private->PciIo,\r | |
2695 | Trb->Slot,\r | |
2696 | SD_MMC_HC_ADMA_SYS_ADDR,\r | |
2697 | FALSE,\r | |
2698 | sizeof (UINT64),\r | |
2699 | &SdmaAddr\r | |
2700 | );\r | |
2701 | } else {\r | |
2702 | Status = SdMmcHcRwMmio (\r | |
2703 | Private->PciIo,\r | |
2704 | Trb->Slot,\r | |
2705 | SD_MMC_HC_SDMA_ADDR,\r | |
2706 | FALSE,\r | |
2707 | sizeof (UINT32),\r | |
2708 | &SdmaAddr\r | |
2709 | );\r | |
2710 | }\r | |
2711 | \r | |
2712 | if (EFI_ERROR (Status)) {\r | |
2713 | return Status;\r | |
2714 | }\r | |
2715 | \r | |
2716 | Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;\r | |
2717 | return EFI_SUCCESS;\r | |
2718 | }\r | |
2719 | \r | |
2720 | /**\r | |
2721 | Checks if the data transfer completed and performs any actions\r | |
2722 | neccessary to continue the data transfer such as SDMA system\r | |
2723 | address fixup or PIO data transfer.\r | |
2724 | \r | |
2725 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2726 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2727 | @param[in] IntStatus Snapshot of the normal interrupt status register.\r | |
2728 | \r | |
2729 | @retval EFI_SUCCESS Data transfer completed successfully.\r | |
2730 | @retval EFI_NOT_READY Data transfer completion still pending.\r | |
2731 | @retval Others Data transfer failed to complete.\r | |
2732 | **/\r | |
2733 | EFI_STATUS\r | |
2734 | SdMmcCheckDataTransfer (\r | |
2735 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2736 | IN SD_MMC_HC_TRB *Trb,\r | |
2737 | IN UINT16 IntStatus\r | |
2738 | )\r | |
2739 | {\r | |
2740 | UINT16 Data16;\r | |
2741 | EFI_STATUS Status;\r | |
2742 | \r | |
2743 | if ((IntStatus & BIT1) != 0) {\r | |
2744 | Data16 = BIT1;\r | |
2745 | Status = SdMmcHcRwMmio (\r | |
2746 | Private->PciIo,\r | |
2747 | Trb->Slot,\r | |
2748 | SD_MMC_HC_NOR_INT_STS,\r | |
2749 | FALSE,\r | |
2750 | sizeof (Data16),\r | |
2751 | &Data16\r | |
2752 | );\r | |
2753 | return Status;\r | |
2754 | }\r | |
2755 | \r | |
1436aea4 | 2756 | if ((Trb->Mode == SdMmcPioMode) && !Trb->PioModeTransferCompleted) {\r |
9bfaa3da AM |
2757 | Status = SdMmcTransferDataWithPio (Private, Trb, IntStatus);\r |
2758 | if (EFI_ERROR (Status)) {\r | |
2759 | return Status;\r | |
2760 | }\r | |
2761 | }\r | |
2762 | \r | |
7d48d20a AM |
2763 | if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) != 0)) {\r |
2764 | Data16 = BIT3;\r | |
2765 | Status = SdMmcHcRwMmio (\r | |
2766 | Private->PciIo,\r | |
2767 | Trb->Slot,\r | |
2768 | SD_MMC_HC_NOR_INT_STS,\r | |
2769 | FALSE,\r | |
2770 | sizeof (Data16),\r | |
2771 | &Data16\r | |
2772 | );\r | |
2773 | if (EFI_ERROR (Status)) {\r | |
2774 | return Status;\r | |
2775 | }\r | |
1436aea4 | 2776 | \r |
7d48d20a AM |
2777 | Status = SdMmcUpdateSdmaAddress (Private, Trb);\r |
2778 | if (EFI_ERROR (Status)) {\r | |
2779 | return Status;\r | |
2780 | }\r | |
2781 | }\r | |
2782 | \r | |
2783 | return EFI_NOT_READY;\r | |
2784 | }\r | |
2785 | \r | |
48555339 FT |
2786 | /**\r |
2787 | Check the TRB execution result.\r | |
2788 | \r | |
2789 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2790 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2791 | \r | |
2792 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
2793 | @retval EFI_NOT_READY The TRB is not completed for execution.\r | |
2794 | @retval Others Some erros happen when executing this request.\r | |
2795 | \r | |
2796 | **/\r | |
2797 | EFI_STATUS\r | |
2798 | SdMmcCheckTrbResult (\r | |
1436aea4 MK |
2799 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
2800 | IN SD_MMC_HC_TRB *Trb\r | |
48555339 FT |
2801 | )\r |
2802 | {\r | |
1436aea4 MK |
2803 | EFI_STATUS Status;\r |
2804 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2805 | UINT16 IntStatus;\r | |
48555339 | 2806 | \r |
1436aea4 | 2807 | Packet = Trb->Packet;\r |
48555339 FT |
2808 | //\r |
2809 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2810 | //\r | |
2811 | Status = SdMmcHcRwMmio (\r | |
2812 | Private->PciIo,\r | |
2813 | Trb->Slot,\r | |
2814 | SD_MMC_HC_NOR_INT_STS,\r | |
2815 | TRUE,\r | |
2816 | sizeof (IntStatus),\r | |
2817 | &IntStatus\r | |
2818 | );\r | |
2819 | if (EFI_ERROR (Status)) {\r | |
2820 | goto Done;\r | |
2821 | }\r | |
a22f4c34 | 2822 | \r |
48555339 | 2823 | //\r |
a22f4c34 AM |
2824 | // Check if there are any errors reported by host controller\r |
2825 | // and if neccessary recover the controller before next command is executed.\r | |
48555339 | 2826 | //\r |
a22f4c34 AM |
2827 | Status = SdMmcCheckAndRecoverErrors (Private, Trb->Slot, IntStatus);\r |
2828 | if (EFI_ERROR (Status)) {\r | |
48555339 FT |
2829 | goto Done;\r |
2830 | }\r | |
a22f4c34 | 2831 | \r |
6d387610 AM |
2832 | //\r |
2833 | // Tuning commands are the only ones that do not generate command\r | |
2834 | // complete interrupt. Process them here before entering the code\r | |
2835 | // that waits for command completion.\r | |
2836 | //\r | |
2837 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
2838 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
2839 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
1436aea4 MK |
2840 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK)))\r |
2841 | {\r | |
9bfaa3da AM |
2842 | Status = SdMmcTransferDataWithPio (Private, Trb, IntStatus);\r |
2843 | goto Done;\r | |
6d387610 AM |
2844 | }\r |
2845 | \r | |
2846 | if (!Trb->CommandComplete) {\r | |
2847 | Status = SdMmcCheckCommandComplete (Private, Trb, IntStatus);\r | |
2848 | if (EFI_ERROR (Status)) {\r | |
2849 | goto Done;\r | |
6d387610 AM |
2850 | }\r |
2851 | }\r | |
2852 | \r | |
1436aea4 MK |
2853 | if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r |
2854 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r | |
2855 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b))\r | |
2856 | {\r | |
7d48d20a AM |
2857 | Status = SdMmcCheckDataTransfer (Private, Trb, IntStatus);\r |
2858 | } else {\r | |
2859 | Status = EFI_SUCCESS;\r | |
48555339 FT |
2860 | }\r |
2861 | \r | |
48555339 | 2862 | Done:\r |
48555339 FT |
2863 | if (Status != EFI_NOT_READY) {\r |
2864 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
9767a597 AM |
2865 | if (EFI_ERROR (Status)) {\r |
2866 | DEBUG ((DEBUG_ERROR, "TRB failed with %r\n", Status));\r | |
2867 | SdMmcPrintTrb (DEBUG_ERROR, Trb);\r | |
2868 | } else {\r | |
2869 | DEBUG ((DEBUG_VERBOSE, "TRB success\n"));\r | |
2870 | SdMmcPrintTrb (DEBUG_VERBOSE, Trb);\r | |
2871 | }\r | |
48555339 FT |
2872 | }\r |
2873 | \r | |
2874 | return Status;\r | |
2875 | }\r | |
2876 | \r | |
2877 | /**\r | |
2878 | Wait for the TRB execution result.\r | |
2879 | \r | |
2880 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2881 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2882 | \r | |
2883 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
2884 | @retval Others Some erros happen when executing this request.\r | |
2885 | \r | |
2886 | **/\r | |
2887 | EFI_STATUS\r | |
2888 | SdMmcWaitTrbResult (\r | |
1436aea4 MK |
2889 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
2890 | IN SD_MMC_HC_TRB *Trb\r | |
48555339 FT |
2891 | )\r |
2892 | {\r | |
1436aea4 MK |
2893 | EFI_STATUS Status;\r |
2894 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2895 | UINT64 Timeout;\r | |
2896 | BOOLEAN InfiniteWait;\r | |
48555339 FT |
2897 | \r |
2898 | Packet = Trb->Packet;\r | |
2899 | //\r | |
2900 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
2901 | //\r | |
2902 | Timeout = Packet->Timeout;\r | |
2903 | if (Timeout == 0) {\r | |
2904 | InfiniteWait = TRUE;\r | |
2905 | } else {\r | |
2906 | InfiniteWait = FALSE;\r | |
2907 | }\r | |
2908 | \r | |
2909 | while (InfiniteWait || (Timeout > 0)) {\r | |
2910 | //\r | |
2911 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2912 | //\r | |
2913 | Status = SdMmcCheckTrbResult (Private, Trb);\r | |
2914 | if (Status != EFI_NOT_READY) {\r | |
2915 | return Status;\r | |
2916 | }\r | |
1436aea4 | 2917 | \r |
48555339 FT |
2918 | //\r |
2919 | // Stall for 1 microsecond.\r | |
2920 | //\r | |
2921 | gBS->Stall (1);\r | |
2922 | \r | |
2923 | Timeout--;\r | |
2924 | }\r | |
2925 | \r | |
2926 | return EFI_TIMEOUT;\r | |
2927 | }\r |