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48555339 FT |
1 | /** @file\r |
2 | This driver is used to manage SD/MMC PCI host controllers which are compliance\r | |
48190274 HW |
3 | with SD Host Controller Simplified Specification version 3.00 plus the 64-bit\r |
4 | System Addressing support in SD Host Controller Simplified Specification version\r | |
5 | 4.20.\r | |
48555339 FT |
6 | \r |
7 | It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r | |
8 | \r | |
690d60c0 | 9 | Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r |
48190274 | 10 | Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r |
48555339 FT |
11 | This program and the accompanying materials\r |
12 | are licensed and made available under the terms and conditions of the BSD License\r | |
13 | which accompanies this distribution. The full text of the license may be found at\r | |
14 | http://opensource.org/licenses/bsd-license.php\r | |
15 | \r | |
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
17 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
18 | \r | |
19 | **/\r | |
20 | \r | |
21 | #include "SdMmcPciHcDxe.h"\r | |
22 | \r | |
23 | /**\r | |
24 | Dump the content of SD/MMC host controller's Capability Register.\r | |
25 | \r | |
26 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
27 | @param[in] Capability The buffer to store the capability data.\r | |
28 | \r | |
29 | **/\r | |
30 | VOID\r | |
31 | DumpCapabilityReg (\r | |
32 | IN UINT8 Slot,\r | |
33 | IN SD_MMC_HC_SLOT_CAP *Capability\r | |
34 | )\r | |
35 | {\r | |
36 | //\r | |
37 | // Dump Capability Data\r | |
38 | //\r | |
e27ccaba FT |
39 | DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));\r |
40 | DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));\r | |
41 | DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));\r | |
42 | DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));\r | |
43 | DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));\r | |
44 | DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));\r | |
45 | DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));\r | |
46 | DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));\r | |
47 | DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));\r | |
48 | DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r | |
49 | DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r | |
50 | DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r | |
b5547b9c AS |
51 | DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));\r |
52 | DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));\r | |
e27ccaba FT |
53 | DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r |
54 | DEBUG ((DEBUG_INFO, " SlotType "));\r | |
48555339 | 55 | if (Capability->SlotType == 0x00) {\r |
e27ccaba | 56 | DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));\r |
48555339 | 57 | } else if (Capability->SlotType == 0x01) {\r |
e27ccaba | 58 | DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));\r |
48555339 | 59 | } else if (Capability->SlotType == 0x02) {\r |
e27ccaba | 60 | DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));\r |
48555339 | 61 | } else {\r |
e27ccaba | 62 | DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));\r |
48555339 | 63 | }\r |
e27ccaba FT |
64 | DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));\r |
65 | DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));\r | |
66 | DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));\r | |
67 | DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));\r | |
68 | DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));\r | |
69 | DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));\r | |
70 | DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));\r | |
48555339 | 71 | if (Capability->TimerCount == 0) {\r |
e27ccaba | 72 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));\r |
48555339 | 73 | } else {\r |
e27ccaba | 74 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));\r |
48555339 | 75 | }\r |
e27ccaba FT |
76 | DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));\r |
77 | DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));\r | |
78 | DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));\r | |
79 | DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));\r | |
48555339 FT |
80 | return;\r |
81 | }\r | |
82 | \r | |
83 | /**\r | |
84 | Read SlotInfo register from SD/MMC host controller pci config space.\r | |
85 | \r | |
86 | @param[in] PciIo The PCI IO protocol instance.\r | |
87 | @param[out] FirstBar The buffer to store the first BAR value.\r | |
88 | @param[out] SlotNum The buffer to store the supported slot number.\r | |
89 | \r | |
90 | @retval EFI_SUCCESS The operation succeeds.\r | |
91 | @retval Others The operation fails.\r | |
92 | \r | |
93 | **/\r | |
94 | EFI_STATUS\r | |
95 | EFIAPI\r | |
96 | SdMmcHcGetSlotInfo (\r | |
97 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
98 | OUT UINT8 *FirstBar,\r | |
99 | OUT UINT8 *SlotNum\r | |
100 | )\r | |
101 | {\r | |
102 | EFI_STATUS Status;\r | |
103 | SD_MMC_HC_SLOT_INFO SlotInfo;\r | |
104 | \r | |
105 | Status = PciIo->Pci.Read (\r | |
106 | PciIo,\r | |
107 | EfiPciIoWidthUint8,\r | |
108 | SD_MMC_HC_SLOT_OFFSET,\r | |
109 | sizeof (SlotInfo),\r | |
110 | &SlotInfo\r | |
111 | );\r | |
112 | if (EFI_ERROR (Status)) {\r | |
113 | return Status;\r | |
114 | }\r | |
115 | \r | |
116 | *FirstBar = SlotInfo.FirstBar;\r | |
117 | *SlotNum = SlotInfo.SlotNum + 1;\r | |
118 | ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);\r | |
119 | return EFI_SUCCESS;\r | |
120 | }\r | |
121 | \r | |
122 | /**\r | |
123 | Read/Write specified SD/MMC host controller mmio register.\r | |
124 | \r | |
125 | @param[in] PciIo The PCI IO protocol instance.\r | |
126 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
127 | header to use as the base address for the memory\r | |
128 | operation to perform.\r | |
129 | @param[in] Offset The offset within the selected BAR to start the\r | |
130 | memory operation.\r | |
131 | @param[in] Read A boolean to indicate it's read or write operation.\r | |
132 | @param[in] Count The width of the mmio register in bytes.\r | |
133 | Must be 1, 2 , 4 or 8 bytes.\r | |
134 | @param[in, out] Data For read operations, the destination buffer to store\r | |
135 | the results. For write operations, the source buffer\r | |
136 | to write data from. The caller is responsible for\r | |
137 | having ownership of the data buffer and ensuring its\r | |
138 | size not less than Count bytes.\r | |
139 | \r | |
140 | @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r | |
141 | @retval EFI_SUCCESS The read/write operation succeeds.\r | |
142 | @retval Others The read/write operation fails.\r | |
143 | \r | |
144 | **/\r | |
145 | EFI_STATUS\r | |
146 | EFIAPI\r | |
147 | SdMmcHcRwMmio (\r | |
148 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
149 | IN UINT8 BarIndex,\r | |
150 | IN UINT32 Offset,\r | |
151 | IN BOOLEAN Read,\r | |
152 | IN UINT8 Count,\r | |
153 | IN OUT VOID *Data\r | |
154 | )\r | |
155 | {\r | |
156 | EFI_STATUS Status;\r | |
f168816c | 157 | EFI_PCI_IO_PROTOCOL_WIDTH Width;\r |
48555339 FT |
158 | \r |
159 | if ((PciIo == NULL) || (Data == NULL)) {\r | |
160 | return EFI_INVALID_PARAMETER;\r | |
161 | }\r | |
162 | \r | |
f168816c EH |
163 | switch (Count) {\r |
164 | case 1:\r | |
165 | Width = EfiPciIoWidthUint8;\r | |
166 | break;\r | |
167 | case 2:\r | |
168 | Width = EfiPciIoWidthUint16;\r | |
169 | Count = 1;\r | |
170 | break;\r | |
171 | case 4:\r | |
172 | Width = EfiPciIoWidthUint32;\r | |
173 | Count = 1;\r | |
174 | break;\r | |
175 | case 8:\r | |
176 | Width = EfiPciIoWidthUint32;\r | |
177 | Count = 2;\r | |
178 | break;\r | |
179 | default:\r | |
180 | return EFI_INVALID_PARAMETER;\r | |
48555339 FT |
181 | }\r |
182 | \r | |
183 | if (Read) {\r | |
184 | Status = PciIo->Mem.Read (\r | |
185 | PciIo,\r | |
f168816c | 186 | Width,\r |
48555339 FT |
187 | BarIndex,\r |
188 | (UINT64) Offset,\r | |
189 | Count,\r | |
190 | Data\r | |
191 | );\r | |
192 | } else {\r | |
193 | Status = PciIo->Mem.Write (\r | |
194 | PciIo,\r | |
f168816c | 195 | Width,\r |
48555339 FT |
196 | BarIndex,\r |
197 | (UINT64) Offset,\r | |
198 | Count,\r | |
199 | Data\r | |
200 | );\r | |
201 | }\r | |
202 | \r | |
203 | return Status;\r | |
204 | }\r | |
205 | \r | |
206 | /**\r | |
207 | Do OR operation with the value of the specified SD/MMC host controller mmio register.\r | |
208 | \r | |
209 | @param[in] PciIo The PCI IO protocol instance.\r | |
210 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
211 | header to use as the base address for the memory\r | |
212 | operation to perform.\r | |
213 | @param[in] Offset The offset within the selected BAR to start the\r | |
214 | memory operation.\r | |
215 | @param[in] Count The width of the mmio register in bytes.\r | |
216 | Must be 1, 2 , 4 or 8 bytes.\r | |
217 | @param[in] OrData The pointer to the data used to do OR operation.\r | |
218 | The caller is responsible for having ownership of\r | |
219 | the data buffer and ensuring its size not less than\r | |
220 | Count bytes.\r | |
221 | \r | |
222 | @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r | |
223 | @retval EFI_SUCCESS The OR operation succeeds.\r | |
224 | @retval Others The OR operation fails.\r | |
225 | \r | |
226 | **/\r | |
227 | EFI_STATUS\r | |
228 | EFIAPI\r | |
229 | SdMmcHcOrMmio (\r | |
230 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
231 | IN UINT8 BarIndex,\r | |
232 | IN UINT32 Offset,\r | |
233 | IN UINT8 Count,\r | |
234 | IN VOID *OrData\r | |
235 | )\r | |
236 | {\r | |
237 | EFI_STATUS Status;\r | |
238 | UINT64 Data;\r | |
239 | UINT64 Or;\r | |
240 | \r | |
241 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
242 | if (EFI_ERROR (Status)) {\r | |
243 | return Status;\r | |
244 | }\r | |
245 | \r | |
246 | if (Count == 1) {\r | |
247 | Or = *(UINT8*) OrData;\r | |
248 | } else if (Count == 2) {\r | |
249 | Or = *(UINT16*) OrData;\r | |
250 | } else if (Count == 4) {\r | |
251 | Or = *(UINT32*) OrData;\r | |
252 | } else if (Count == 8) {\r | |
253 | Or = *(UINT64*) OrData;\r | |
254 | } else {\r | |
255 | return EFI_INVALID_PARAMETER;\r | |
256 | }\r | |
257 | \r | |
258 | Data |= Or;\r | |
259 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
260 | \r | |
261 | return Status;\r | |
262 | }\r | |
263 | \r | |
264 | /**\r | |
265 | Do AND operation with the value of the specified SD/MMC host controller mmio register.\r | |
266 | \r | |
267 | @param[in] PciIo The PCI IO protocol instance.\r | |
268 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
269 | header to use as the base address for the memory\r | |
270 | operation to perform.\r | |
271 | @param[in] Offset The offset within the selected BAR to start the\r | |
272 | memory operation.\r | |
273 | @param[in] Count The width of the mmio register in bytes.\r | |
274 | Must be 1, 2 , 4 or 8 bytes.\r | |
275 | @param[in] AndData The pointer to the data used to do AND operation.\r | |
276 | The caller is responsible for having ownership of\r | |
277 | the data buffer and ensuring its size not less than\r | |
278 | Count bytes.\r | |
279 | \r | |
280 | @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r | |
281 | @retval EFI_SUCCESS The AND operation succeeds.\r | |
282 | @retval Others The AND operation fails.\r | |
283 | \r | |
284 | **/\r | |
285 | EFI_STATUS\r | |
286 | EFIAPI\r | |
287 | SdMmcHcAndMmio (\r | |
288 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
289 | IN UINT8 BarIndex,\r | |
290 | IN UINT32 Offset,\r | |
291 | IN UINT8 Count,\r | |
292 | IN VOID *AndData\r | |
293 | )\r | |
294 | {\r | |
295 | EFI_STATUS Status;\r | |
296 | UINT64 Data;\r | |
297 | UINT64 And;\r | |
298 | \r | |
299 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
300 | if (EFI_ERROR (Status)) {\r | |
301 | return Status;\r | |
302 | }\r | |
303 | \r | |
304 | if (Count == 1) {\r | |
305 | And = *(UINT8*) AndData;\r | |
306 | } else if (Count == 2) {\r | |
307 | And = *(UINT16*) AndData;\r | |
308 | } else if (Count == 4) {\r | |
309 | And = *(UINT32*) AndData;\r | |
310 | } else if (Count == 8) {\r | |
311 | And = *(UINT64*) AndData;\r | |
312 | } else {\r | |
313 | return EFI_INVALID_PARAMETER;\r | |
314 | }\r | |
315 | \r | |
316 | Data &= And;\r | |
317 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
318 | \r | |
319 | return Status;\r | |
320 | }\r | |
321 | \r | |
322 | /**\r | |
323 | Wait for the value of the specified MMIO register set to the test value.\r | |
324 | \r | |
325 | @param[in] PciIo The PCI IO protocol instance.\r | |
326 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
327 | header to use as the base address for the memory\r | |
328 | operation to perform.\r | |
329 | @param[in] Offset The offset within the selected BAR to start the\r | |
330 | memory operation.\r | |
331 | @param[in] Count The width of the mmio register in bytes.\r | |
332 | Must be 1, 2, 4 or 8 bytes.\r | |
333 | @param[in] MaskValue The mask value of memory.\r | |
334 | @param[in] TestValue The test value of memory.\r | |
335 | \r | |
336 | @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r | |
337 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
338 | @retval Others The MMIO operation fails.\r | |
339 | \r | |
340 | **/\r | |
341 | EFI_STATUS\r | |
342 | EFIAPI\r | |
343 | SdMmcHcCheckMmioSet (\r | |
344 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
345 | IN UINT8 BarIndex,\r | |
346 | IN UINT32 Offset,\r | |
347 | IN UINT8 Count,\r | |
348 | IN UINT64 MaskValue,\r | |
349 | IN UINT64 TestValue\r | |
350 | )\r | |
351 | {\r | |
352 | EFI_STATUS Status;\r | |
353 | UINT64 Value;\r | |
354 | \r | |
355 | //\r | |
356 | // Access PCI MMIO space to see if the value is the tested one.\r | |
357 | //\r | |
358 | Value = 0;\r | |
359 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);\r | |
360 | if (EFI_ERROR (Status)) {\r | |
361 | return Status;\r | |
362 | }\r | |
363 | \r | |
364 | Value &= MaskValue;\r | |
365 | \r | |
366 | if (Value == TestValue) {\r | |
367 | return EFI_SUCCESS;\r | |
368 | }\r | |
369 | \r | |
370 | return EFI_NOT_READY;\r | |
371 | }\r | |
372 | \r | |
373 | /**\r | |
374 | Wait for the value of the specified MMIO register set to the test value.\r | |
375 | \r | |
376 | @param[in] PciIo The PCI IO protocol instance.\r | |
377 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
378 | header to use as the base address for the memory\r | |
379 | operation to perform.\r | |
380 | @param[in] Offset The offset within the selected BAR to start the\r | |
381 | memory operation.\r | |
382 | @param[in] Count The width of the mmio register in bytes.\r | |
383 | Must be 1, 2, 4 or 8 bytes.\r | |
384 | @param[in] MaskValue The mask value of memory.\r | |
385 | @param[in] TestValue The test value of memory.\r | |
386 | @param[in] Timeout The time out value for wait memory set, uses 1\r | |
387 | microsecond as a unit.\r | |
388 | \r | |
389 | @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r | |
390 | range.\r | |
391 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
392 | @retval Others The MMIO operation fails.\r | |
393 | \r | |
394 | **/\r | |
395 | EFI_STATUS\r | |
396 | EFIAPI\r | |
397 | SdMmcHcWaitMmioSet (\r | |
398 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
399 | IN UINT8 BarIndex,\r | |
400 | IN UINT32 Offset,\r | |
401 | IN UINT8 Count,\r | |
402 | IN UINT64 MaskValue,\r | |
403 | IN UINT64 TestValue,\r | |
404 | IN UINT64 Timeout\r | |
405 | )\r | |
406 | {\r | |
407 | EFI_STATUS Status;\r | |
408 | BOOLEAN InfiniteWait;\r | |
409 | \r | |
410 | if (Timeout == 0) {\r | |
411 | InfiniteWait = TRUE;\r | |
412 | } else {\r | |
413 | InfiniteWait = FALSE;\r | |
414 | }\r | |
415 | \r | |
416 | while (InfiniteWait || (Timeout > 0)) {\r | |
417 | Status = SdMmcHcCheckMmioSet (\r | |
418 | PciIo,\r | |
419 | BarIndex,\r | |
420 | Offset,\r | |
421 | Count,\r | |
422 | MaskValue,\r | |
423 | TestValue\r | |
424 | );\r | |
425 | if (Status != EFI_NOT_READY) {\r | |
426 | return Status;\r | |
427 | }\r | |
428 | \r | |
429 | //\r | |
430 | // Stall for 1 microsecond.\r | |
431 | //\r | |
432 | gBS->Stall (1);\r | |
433 | \r | |
434 | Timeout--;\r | |
435 | }\r | |
436 | \r | |
437 | return EFI_TIMEOUT;\r | |
438 | }\r | |
439 | \r | |
b5547b9c AS |
440 | /**\r |
441 | Get the controller version information from the specified slot.\r | |
442 | \r | |
443 | @param[in] PciIo The PCI IO protocol instance.\r | |
444 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
445 | @param[out] Version The buffer to store the version information.\r | |
446 | \r | |
447 | @retval EFI_SUCCESS The operation executes successfully.\r | |
448 | @retval Others The operation fails.\r | |
449 | \r | |
450 | **/\r | |
451 | EFI_STATUS\r | |
452 | SdMmcHcGetControllerVersion (\r | |
453 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
454 | IN UINT8 Slot,\r | |
455 | OUT UINT16 *Version\r | |
456 | )\r | |
457 | {\r | |
458 | EFI_STATUS Status;\r | |
459 | \r | |
460 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);\r | |
461 | if (EFI_ERROR (Status)) {\r | |
462 | return Status;\r | |
463 | }\r | |
464 | \r | |
465 | *Version &= 0xFF;\r | |
466 | \r | |
467 | return EFI_SUCCESS;\r | |
468 | }\r | |
469 | \r | |
48555339 FT |
470 | /**\r |
471 | Software reset the specified SD/MMC host controller and enable all interrupts.\r | |
472 | \r | |
b23fc39c | 473 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 FT |
474 | @param[in] Slot The slot number of the SD card to send the command to.\r |
475 | \r | |
476 | @retval EFI_SUCCESS The software reset executes successfully.\r | |
477 | @retval Others The software reset fails.\r | |
478 | \r | |
479 | **/\r | |
480 | EFI_STATUS\r | |
481 | SdMmcHcReset (\r | |
b23fc39c | 482 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
48555339 FT |
483 | IN UINT8 Slot\r |
484 | )\r | |
485 | {\r | |
486 | EFI_STATUS Status;\r | |
487 | UINT8 SwReset;\r | |
b23fc39c | 488 | EFI_PCI_IO_PROTOCOL *PciIo;\r |
48555339 | 489 | \r |
b23fc39c AB |
490 | //\r |
491 | // Notify the SD/MMC override protocol that we are about to reset\r | |
492 | // the SD/MMC host controller.\r | |
493 | //\r | |
494 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
495 | Status = mOverride->NotifyPhase (\r | |
496 | Private->ControllerHandle,\r | |
497 | Slot,\r | |
49c99534 MW |
498 | EdkiiSdMmcResetPre,\r |
499 | NULL);\r | |
b23fc39c AB |
500 | if (EFI_ERROR (Status)) {\r |
501 | DEBUG ((DEBUG_WARN,\r | |
502 | "%a: SD/MMC pre reset notifier callback failed - %r\n",\r | |
503 | __FUNCTION__, Status));\r | |
504 | return Status;\r | |
505 | }\r | |
506 | }\r | |
507 | \r | |
508 | PciIo = Private->PciIo;\r | |
064d301f TM |
509 | SwReset = BIT0;\r |
510 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);\r | |
48555339 FT |
511 | \r |
512 | if (EFI_ERROR (Status)) {\r | |
064d301f | 513 | DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));\r |
48555339 FT |
514 | return Status;\r |
515 | }\r | |
516 | \r | |
517 | Status = SdMmcHcWaitMmioSet (\r | |
518 | PciIo,\r | |
519 | Slot,\r | |
520 | SD_MMC_HC_SW_RST,\r | |
521 | sizeof (SwReset),\r | |
064d301f | 522 | BIT0,\r |
48555339 FT |
523 | 0x00,\r |
524 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
525 | );\r | |
526 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 527 | DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r |
48555339 FT |
528 | return Status;\r |
529 | }\r | |
b23fc39c | 530 | \r |
48555339 FT |
531 | //\r |
532 | // Enable all interrupt after reset all.\r | |
533 | //\r | |
534 | Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r | |
b23fc39c AB |
535 | if (EFI_ERROR (Status)) {\r |
536 | DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",\r | |
537 | Status));\r | |
538 | return Status;\r | |
539 | }\r | |
540 | \r | |
541 | //\r | |
542 | // Notify the SD/MMC override protocol that we have just reset\r | |
543 | // the SD/MMC host controller.\r | |
544 | //\r | |
545 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
546 | Status = mOverride->NotifyPhase (\r | |
547 | Private->ControllerHandle,\r | |
548 | Slot,\r | |
49c99534 MW |
549 | EdkiiSdMmcResetPost,\r |
550 | NULL);\r | |
b23fc39c AB |
551 | if (EFI_ERROR (Status)) {\r |
552 | DEBUG ((DEBUG_WARN,\r | |
553 | "%a: SD/MMC post reset notifier callback failed - %r\n",\r | |
554 | __FUNCTION__, Status));\r | |
555 | }\r | |
556 | }\r | |
48555339 FT |
557 | \r |
558 | return Status;\r | |
559 | }\r | |
560 | \r | |
561 | /**\r | |
562 | Set all interrupt status bits in Normal and Error Interrupt Status Enable\r | |
563 | register.\r | |
564 | \r | |
565 | @param[in] PciIo The PCI IO protocol instance.\r | |
566 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
567 | \r | |
568 | @retval EFI_SUCCESS The operation executes successfully.\r | |
569 | @retval Others The operation fails.\r | |
570 | \r | |
571 | **/\r | |
572 | EFI_STATUS\r | |
573 | SdMmcHcEnableInterrupt (\r | |
574 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
575 | IN UINT8 Slot\r | |
576 | )\r | |
577 | {\r | |
578 | EFI_STATUS Status;\r | |
579 | UINT16 IntStatus;\r | |
580 | \r | |
581 | //\r | |
582 | // Enable all bits in Error Interrupt Status Enable Register\r | |
583 | //\r | |
584 | IntStatus = 0xFFFF;\r | |
585 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
586 | if (EFI_ERROR (Status)) {\r | |
587 | return Status;\r | |
588 | }\r | |
589 | //\r | |
590 | // Enable all bits in Normal Interrupt Status Enable Register\r | |
591 | //\r | |
592 | IntStatus = 0xFFFF;\r | |
593 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
594 | \r | |
595 | return Status;\r | |
596 | }\r | |
597 | \r | |
598 | /**\r | |
599 | Get the capability data from the specified slot.\r | |
600 | \r | |
601 | @param[in] PciIo The PCI IO protocol instance.\r | |
602 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
603 | @param[out] Capability The buffer to store the capability data.\r | |
604 | \r | |
605 | @retval EFI_SUCCESS The operation executes successfully.\r | |
606 | @retval Others The operation fails.\r | |
607 | \r | |
608 | **/\r | |
609 | EFI_STATUS\r | |
610 | SdMmcHcGetCapability (\r | |
611 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
612 | IN UINT8 Slot,\r | |
613 | OUT SD_MMC_HC_SLOT_CAP *Capability\r | |
614 | )\r | |
615 | {\r | |
616 | EFI_STATUS Status;\r | |
617 | UINT64 Cap;\r | |
618 | \r | |
619 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r | |
620 | if (EFI_ERROR (Status)) {\r | |
621 | return Status;\r | |
622 | }\r | |
623 | \r | |
624 | CopyMem (Capability, &Cap, sizeof (Cap));\r | |
625 | \r | |
626 | return EFI_SUCCESS;\r | |
627 | }\r | |
628 | \r | |
629 | /**\r | |
630 | Get the maximum current capability data from the specified slot.\r | |
631 | \r | |
632 | @param[in] PciIo The PCI IO protocol instance.\r | |
633 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
634 | @param[out] MaxCurrent The buffer to store the maximum current capability data.\r | |
635 | \r | |
636 | @retval EFI_SUCCESS The operation executes successfully.\r | |
637 | @retval Others The operation fails.\r | |
638 | \r | |
639 | **/\r | |
640 | EFI_STATUS\r | |
641 | SdMmcHcGetMaxCurrent (\r | |
642 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
643 | IN UINT8 Slot,\r | |
644 | OUT UINT64 *MaxCurrent\r | |
645 | )\r | |
646 | {\r | |
647 | EFI_STATUS Status;\r | |
648 | \r | |
649 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);\r | |
650 | \r | |
651 | return Status;\r | |
652 | }\r | |
653 | \r | |
654 | /**\r | |
655 | Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r | |
656 | slot.\r | |
657 | \r | |
658 | Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r | |
659 | \r | |
660 | @param[in] PciIo The PCI IO protocol instance.\r | |
661 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
662 | @param[out] MediaPresent The pointer to the media present boolean value.\r | |
663 | \r | |
664 | @retval EFI_SUCCESS There is no media change happened.\r | |
665 | @retval EFI_MEDIA_CHANGED There is media change happened.\r | |
666 | @retval Others The detection fails.\r | |
667 | \r | |
668 | **/\r | |
669 | EFI_STATUS\r | |
670 | SdMmcHcCardDetect (\r | |
671 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
672 | IN UINT8 Slot,\r | |
673 | OUT BOOLEAN *MediaPresent\r | |
674 | )\r | |
675 | {\r | |
676 | EFI_STATUS Status;\r | |
677 | UINT16 Data;\r | |
678 | UINT32 PresentState;\r | |
679 | \r | |
2e9107b8 FT |
680 | //\r |
681 | // Check Present State Register to see if there is a card presented.\r | |
682 | //\r | |
683 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r | |
684 | if (EFI_ERROR (Status)) {\r | |
685 | return Status;\r | |
686 | }\r | |
687 | \r | |
688 | if ((PresentState & BIT16) != 0) {\r | |
689 | *MediaPresent = TRUE;\r | |
690 | } else {\r | |
691 | *MediaPresent = FALSE;\r | |
692 | }\r | |
693 | \r | |
48555339 FT |
694 | //\r |
695 | // Check Normal Interrupt Status Register\r | |
696 | //\r | |
697 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r | |
698 | if (EFI_ERROR (Status)) {\r | |
699 | return Status;\r | |
700 | }\r | |
701 | \r | |
702 | if ((Data & (BIT6 | BIT7)) != 0) {\r | |
703 | //\r | |
704 | // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r | |
705 | //\r | |
706 | Data &= BIT6 | BIT7;\r | |
707 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r | |
708 | if (EFI_ERROR (Status)) {\r | |
709 | return Status;\r | |
710 | }\r | |
711 | \r | |
48555339 FT |
712 | return EFI_MEDIA_CHANGED;\r |
713 | }\r | |
714 | \r | |
715 | return EFI_SUCCESS;\r | |
716 | }\r | |
717 | \r | |
718 | /**\r | |
719 | Stop SD/MMC card clock.\r | |
720 | \r | |
721 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r | |
722 | \r | |
723 | @param[in] PciIo The PCI IO protocol instance.\r | |
724 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
725 | \r | |
726 | @retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r | |
727 | @retval Others Fail to stop SD/MMC clock.\r | |
728 | \r | |
729 | **/\r | |
730 | EFI_STATUS\r | |
731 | SdMmcHcStopClock (\r | |
732 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
733 | IN UINT8 Slot\r | |
734 | )\r | |
735 | {\r | |
736 | EFI_STATUS Status;\r | |
737 | UINT32 PresentState;\r | |
738 | UINT16 ClockCtrl;\r | |
739 | \r | |
740 | //\r | |
741 | // Ensure no SD transactions are occurring on the SD Bus by\r | |
742 | // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r | |
743 | // in the Present State register to be 0.\r | |
744 | //\r | |
745 | Status = SdMmcHcWaitMmioSet (\r | |
746 | PciIo,\r | |
747 | Slot,\r | |
748 | SD_MMC_HC_PRESENT_STATE,\r | |
749 | sizeof (PresentState),\r | |
750 | BIT0 | BIT1,\r | |
751 | 0,\r | |
752 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
753 | );\r | |
754 | if (EFI_ERROR (Status)) {\r | |
755 | return Status;\r | |
756 | }\r | |
757 | \r | |
758 | //\r | |
759 | // Set SD Clock Enable in the Clock Control register to 0\r | |
760 | //\r | |
761 | ClockCtrl = (UINT16)~BIT2;\r | |
762 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
763 | \r | |
764 | return Status;\r | |
765 | }\r | |
766 | \r | |
767 | /**\r | |
768 | SD/MMC card clock supply.\r | |
769 | \r | |
770 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r | |
771 | \r | |
772 | @param[in] PciIo The PCI IO protocol instance.\r | |
773 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
774 | @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r | |
7f3b0bad | 775 | @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r |
b5547b9c | 776 | @param[in] ControllerVer The version of host controller.\r |
48555339 FT |
777 | \r |
778 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
779 | @retval Others The clock isn't supplied successfully.\r | |
780 | \r | |
781 | **/\r | |
782 | EFI_STATUS\r | |
783 | SdMmcHcClockSupply (\r | |
784 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
785 | IN UINT8 Slot,\r | |
786 | IN UINT64 ClockFreq,\r | |
b5547b9c AS |
787 | IN UINT32 BaseClkFreq,\r |
788 | IN UINT16 ControllerVer\r | |
48555339 FT |
789 | )\r |
790 | {\r | |
791 | EFI_STATUS Status;\r | |
48555339 FT |
792 | UINT32 SettingFreq;\r |
793 | UINT32 Divisor;\r | |
794 | UINT32 Remainder;\r | |
48555339 FT |
795 | UINT16 ClockCtrl;\r |
796 | \r | |
797 | //\r | |
798 | // Calculate a divisor for SD clock frequency\r | |
799 | //\r | |
7f3b0bad | 800 | ASSERT (BaseClkFreq != 0);\r |
48555339 | 801 | \r |
cb9cb9e2 | 802 | if (ClockFreq == 0) {\r |
48555339 FT |
803 | return EFI_INVALID_PARAMETER;\r |
804 | }\r | |
cb9cb9e2 FT |
805 | \r |
806 | if (ClockFreq > (BaseClkFreq * 1000)) {\r | |
807 | ClockFreq = BaseClkFreq * 1000;\r | |
808 | }\r | |
809 | \r | |
48555339 FT |
810 | //\r |
811 | // Calculate the divisor of base frequency.\r | |
812 | //\r | |
813 | Divisor = 0;\r | |
814 | SettingFreq = BaseClkFreq * 1000;\r | |
815 | while (ClockFreq < SettingFreq) {\r | |
816 | Divisor++;\r | |
817 | \r | |
818 | SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r | |
819 | Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r | |
820 | if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r | |
821 | break;\r | |
822 | }\r | |
823 | if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r | |
824 | SettingFreq ++;\r | |
825 | }\r | |
826 | }\r | |
827 | \r | |
e27ccaba | 828 | DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r |
48555339 | 829 | \r |
48555339 FT |
830 | //\r |
831 | // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r | |
832 | //\r | |
b5547b9c AS |
833 | if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&\r |
834 | (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {\r | |
48555339 FT |
835 | ASSERT (Divisor <= 0x3FF);\r |
836 | ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r | |
b5547b9c AS |
837 | } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||\r |
838 | (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {\r | |
48555339 FT |
839 | //\r |
840 | // Only the most significant bit can be used as divisor.\r | |
841 | //\r | |
842 | if (((Divisor - 1) & Divisor) != 0) {\r | |
843 | Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r | |
844 | }\r | |
845 | ASSERT (Divisor <= 0x80);\r | |
846 | ClockCtrl = (Divisor & 0xFF) << 8;\r | |
847 | } else {\r | |
e27ccaba | 848 | DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r |
48555339 FT |
849 | return EFI_UNSUPPORTED;\r |
850 | }\r | |
851 | \r | |
852 | //\r | |
853 | // Stop bus clock at first\r | |
854 | //\r | |
855 | Status = SdMmcHcStopClock (PciIo, Slot);\r | |
856 | if (EFI_ERROR (Status)) {\r | |
857 | return Status;\r | |
858 | }\r | |
859 | \r | |
860 | //\r | |
861 | // Supply clock frequency with specified divisor\r | |
862 | //\r | |
863 | ClockCtrl |= BIT0;\r | |
864 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r | |
865 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 866 | DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r |
48555339 FT |
867 | return Status;\r |
868 | }\r | |
869 | \r | |
870 | //\r | |
871 | // Wait Internal Clock Stable in the Clock Control register to be 1\r | |
872 | //\r | |
873 | Status = SdMmcHcWaitMmioSet (\r | |
874 | PciIo,\r | |
875 | Slot,\r | |
876 | SD_MMC_HC_CLOCK_CTRL,\r | |
877 | sizeof (ClockCtrl),\r | |
878 | BIT1,\r | |
879 | BIT1,\r | |
880 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
881 | );\r | |
882 | if (EFI_ERROR (Status)) {\r | |
883 | return Status;\r | |
884 | }\r | |
885 | \r | |
886 | //\r | |
887 | // Set SD Clock Enable in the Clock Control register to 1\r | |
888 | //\r | |
889 | ClockCtrl = BIT2;\r | |
890 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
891 | \r | |
892 | return Status;\r | |
893 | }\r | |
894 | \r | |
895 | /**\r | |
896 | SD/MMC bus power control.\r | |
897 | \r | |
898 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
899 | \r | |
900 | @param[in] PciIo The PCI IO protocol instance.\r | |
901 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
902 | @param[in] PowerCtrl The value setting to the power control register.\r | |
903 | \r | |
904 | @retval TRUE There is a SD/MMC card attached.\r | |
905 | @retval FALSE There is no a SD/MMC card attached.\r | |
906 | \r | |
907 | **/\r | |
908 | EFI_STATUS\r | |
909 | SdMmcHcPowerControl (\r | |
910 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
911 | IN UINT8 Slot,\r | |
912 | IN UINT8 PowerCtrl\r | |
913 | )\r | |
914 | {\r | |
915 | EFI_STATUS Status;\r | |
916 | \r | |
917 | //\r | |
918 | // Clr SD Bus Power\r | |
919 | //\r | |
920 | PowerCtrl &= (UINT8)~BIT0;\r | |
921 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
922 | if (EFI_ERROR (Status)) {\r | |
923 | return Status;\r | |
924 | }\r | |
925 | \r | |
926 | //\r | |
927 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
928 | //\r | |
929 | PowerCtrl |= BIT0;\r | |
930 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
931 | \r | |
932 | return Status;\r | |
933 | }\r | |
934 | \r | |
935 | /**\r | |
936 | Set the SD/MMC bus width.\r | |
937 | \r | |
938 | Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r | |
939 | \r | |
940 | @param[in] PciIo The PCI IO protocol instance.\r | |
941 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
942 | @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r | |
943 | \r | |
944 | @retval EFI_SUCCESS The bus width is set successfully.\r | |
945 | @retval Others The bus width isn't set successfully.\r | |
946 | \r | |
947 | **/\r | |
948 | EFI_STATUS\r | |
949 | SdMmcHcSetBusWidth (\r | |
950 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
951 | IN UINT8 Slot,\r | |
952 | IN UINT16 BusWidth\r | |
953 | )\r | |
954 | {\r | |
955 | EFI_STATUS Status;\r | |
956 | UINT8 HostCtrl1;\r | |
957 | \r | |
958 | if (BusWidth == 1) {\r | |
959 | HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r | |
960 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
961 | } else if (BusWidth == 4) {\r | |
962 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
963 | if (EFI_ERROR (Status)) {\r | |
964 | return Status;\r | |
965 | }\r | |
966 | HostCtrl1 |= BIT1;\r | |
967 | HostCtrl1 &= (UINT8)~BIT5;\r | |
968 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
969 | } else if (BusWidth == 8) {\r | |
970 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
971 | if (EFI_ERROR (Status)) {\r | |
972 | return Status;\r | |
973 | }\r | |
974 | HostCtrl1 &= (UINT8)~BIT1;\r | |
975 | HostCtrl1 |= BIT5;\r | |
976 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
977 | } else {\r | |
978 | ASSERT (FALSE);\r | |
979 | return EFI_INVALID_PARAMETER;\r | |
980 | }\r | |
981 | \r | |
982 | return Status;\r | |
983 | }\r | |
984 | \r | |
b5547b9c AS |
985 | /**\r |
986 | Configure V4 controller enhancements at initialization.\r | |
987 | \r | |
988 | @param[in] PciIo The PCI IO protocol instance.\r | |
989 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
990 | @param[in] Capability The capability of the slot.\r | |
991 | @param[in] ControllerVer The version of host controller.\r | |
992 | \r | |
993 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
994 | \r | |
995 | **/\r | |
996 | EFI_STATUS\r | |
997 | SdMmcHcInitV4Enhancements (\r | |
998 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
999 | IN UINT8 Slot,\r | |
1000 | IN SD_MMC_HC_SLOT_CAP Capability,\r | |
1001 | IN UINT16 ControllerVer\r | |
1002 | )\r | |
1003 | {\r | |
1004 | EFI_STATUS Status;\r | |
1005 | UINT16 HostCtrl2;\r | |
1006 | \r | |
1007 | //\r | |
1008 | // Check if controller version V4 or higher\r | |
1009 | //\r | |
1010 | if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r | |
1011 | HostCtrl2 = SD_MMC_HC_V4_EN;\r | |
1012 | //\r | |
690d60c0 | 1013 | // Check if controller version V4.0\r |
b5547b9c | 1014 | //\r |
690d60c0 AS |
1015 | if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {\r |
1016 | //\r | |
1017 | // Check if 64bit support is available\r | |
1018 | //\r | |
1019 | if (Capability.SysBus64V3 != 0) {\r | |
1020 | HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r | |
1021 | DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r | |
1022 | }\r | |
b5547b9c AS |
1023 | }\r |
1024 | //\r | |
1025 | // Check if controller version V4.10 or higher\r | |
1026 | //\r | |
690d60c0 AS |
1027 | else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {\r |
1028 | //\r | |
1029 | // Check if 64bit support is available\r | |
1030 | //\r | |
1031 | if (Capability.SysBus64V4 != 0) {\r | |
1032 | HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r | |
1033 | DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r | |
1034 | }\r | |
b5547b9c AS |
1035 | HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;\r |
1036 | DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));\r | |
1037 | }\r | |
1038 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1039 | if (EFI_ERROR (Status)) {\r | |
1040 | return Status;\r | |
1041 | }\r | |
1042 | }\r | |
1043 | \r | |
1044 | return EFI_SUCCESS;\r | |
1045 | }\r | |
1046 | \r | |
48555339 FT |
1047 | /**\r |
1048 | Supply SD/MMC card with lowest clock frequency at initialization.\r | |
1049 | \r | |
1050 | @param[in] PciIo The PCI IO protocol instance.\r | |
1051 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
7f3b0bad | 1052 | @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r |
b5547b9c | 1053 | @param[in] ControllerVer The version of host controller.\r |
48555339 FT |
1054 | \r |
1055 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
1056 | @retval Others The clock isn't supplied successfully.\r | |
1057 | \r | |
1058 | **/\r | |
1059 | EFI_STATUS\r | |
1060 | SdMmcHcInitClockFreq (\r | |
1061 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1062 | IN UINT8 Slot,\r | |
b5547b9c AS |
1063 | IN UINT32 BaseClkFreq,\r |
1064 | IN UINT16 ControllerVer\r | |
48555339 FT |
1065 | )\r |
1066 | {\r | |
1067 | EFI_STATUS Status;\r | |
1068 | UINT32 InitFreq;\r | |
1069 | \r | |
1070 | //\r | |
7f3b0bad MW |
1071 | // According to SDHCI specification ver. 4.2, BaseClkFreq field value of\r |
1072 | // the Capability Register 1 can be zero, which means a need for obtaining\r | |
1073 | // the clock frequency via another method. Fail in case it is not updated\r | |
1074 | // by SW at this point.\r | |
48555339 | 1075 | //\r |
7f3b0bad | 1076 | if (BaseClkFreq == 0) {\r |
48555339 FT |
1077 | //\r |
1078 | // Don't support get Base Clock Frequency information via another method\r | |
1079 | //\r | |
1080 | return EFI_UNSUPPORTED;\r | |
1081 | }\r | |
1082 | //\r | |
1083 | // Supply 400KHz clock frequency at initialization phase.\r | |
1084 | //\r | |
1085 | InitFreq = 400;\r | |
b5547b9c | 1086 | Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);\r |
48555339 FT |
1087 | return Status;\r |
1088 | }\r | |
1089 | \r | |
1090 | /**\r | |
1091 | Supply SD/MMC card with maximum voltage at initialization.\r | |
1092 | \r | |
1093 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
1094 | \r | |
1095 | @param[in] PciIo The PCI IO protocol instance.\r | |
1096 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1097 | @param[in] Capability The capability of the slot.\r | |
1098 | \r | |
1099 | @retval EFI_SUCCESS The voltage is supplied successfully.\r | |
1100 | @retval Others The voltage isn't supplied successfully.\r | |
1101 | \r | |
1102 | **/\r | |
1103 | EFI_STATUS\r | |
1104 | SdMmcHcInitPowerVoltage (\r | |
1105 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1106 | IN UINT8 Slot,\r | |
1107 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
1108 | )\r | |
1109 | {\r | |
1110 | EFI_STATUS Status;\r | |
1111 | UINT8 MaxVoltage;\r | |
1112 | UINT8 HostCtrl2;\r | |
1113 | \r | |
1114 | //\r | |
1115 | // Calculate supported maximum voltage according to SD Bus Voltage Select\r | |
1116 | //\r | |
1117 | if (Capability.Voltage33 != 0) {\r | |
1118 | //\r | |
1119 | // Support 3.3V\r | |
1120 | //\r | |
1121 | MaxVoltage = 0x0E;\r | |
1122 | } else if (Capability.Voltage30 != 0) {\r | |
1123 | //\r | |
1124 | // Support 3.0V\r | |
1125 | //\r | |
1126 | MaxVoltage = 0x0C;\r | |
1127 | } else if (Capability.Voltage18 != 0) {\r | |
1128 | //\r | |
1129 | // Support 1.8V\r | |
1130 | //\r | |
1131 | MaxVoltage = 0x0A;\r | |
1132 | HostCtrl2 = BIT3;\r | |
1133 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1134 | gBS->Stall (5000);\r | |
1135 | if (EFI_ERROR (Status)) {\r | |
1136 | return Status;\r | |
1137 | }\r | |
1138 | } else {\r | |
1139 | ASSERT (FALSE);\r | |
1140 | return EFI_DEVICE_ERROR;\r | |
1141 | }\r | |
1142 | \r | |
1143 | //\r | |
1144 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
1145 | //\r | |
1146 | Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);\r | |
1147 | \r | |
1148 | return Status;\r | |
1149 | }\r | |
1150 | \r | |
1151 | /**\r | |
1152 | Initialize the Timeout Control register with most conservative value at initialization.\r | |
1153 | \r | |
1154 | Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r | |
1155 | \r | |
1156 | @param[in] PciIo The PCI IO protocol instance.\r | |
1157 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1158 | \r | |
1159 | @retval EFI_SUCCESS The timeout control register is configured successfully.\r | |
1160 | @retval Others The timeout control register isn't configured successfully.\r | |
1161 | \r | |
1162 | **/\r | |
1163 | EFI_STATUS\r | |
1164 | SdMmcHcInitTimeoutCtrl (\r | |
1165 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1166 | IN UINT8 Slot\r | |
1167 | )\r | |
1168 | {\r | |
1169 | EFI_STATUS Status;\r | |
1170 | UINT8 Timeout;\r | |
1171 | \r | |
1172 | Timeout = 0x0E;\r | |
1173 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r | |
1174 | \r | |
1175 | return Status;\r | |
1176 | }\r | |
1177 | \r | |
1178 | /**\r | |
1179 | Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r | |
1180 | at initialization.\r | |
1181 | \r | |
b23fc39c | 1182 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 | 1183 | @param[in] Slot The slot number of the SD card to send the command to.\r |
48555339 FT |
1184 | \r |
1185 | @retval EFI_SUCCESS The host controller is initialized successfully.\r | |
1186 | @retval Others The host controller isn't initialized successfully.\r | |
1187 | \r | |
1188 | **/\r | |
1189 | EFI_STATUS\r | |
1190 | SdMmcHcInitHost (\r | |
b23fc39c AB |
1191 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
1192 | IN UINT8 Slot\r | |
48555339 FT |
1193 | )\r |
1194 | {\r | |
b23fc39c AB |
1195 | EFI_STATUS Status;\r |
1196 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1197 | SD_MMC_HC_SLOT_CAP Capability;\r | |
1198 | \r | |
1199 | //\r | |
1200 | // Notify the SD/MMC override protocol that we are about to initialize\r | |
1201 | // the SD/MMC host controller.\r | |
1202 | //\r | |
1203 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1204 | Status = mOverride->NotifyPhase (\r | |
1205 | Private->ControllerHandle,\r | |
1206 | Slot,\r | |
49c99534 MW |
1207 | EdkiiSdMmcInitHostPre,\r |
1208 | NULL);\r | |
b23fc39c AB |
1209 | if (EFI_ERROR (Status)) {\r |
1210 | DEBUG ((DEBUG_WARN,\r | |
1211 | "%a: SD/MMC pre init notifier callback failed - %r\n",\r | |
1212 | __FUNCTION__, Status));\r | |
1213 | return Status;\r | |
1214 | }\r | |
1215 | }\r | |
1216 | \r | |
1217 | PciIo = Private->PciIo;\r | |
1218 | Capability = Private->Capability[Slot];\r | |
48555339 | 1219 | \r |
b5547b9c AS |
1220 | Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);\r |
1221 | if (EFI_ERROR (Status)) {\r | |
1222 | return Status;\r | |
1223 | }\r | |
1224 | \r | |
1225 | Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);\r | |
48555339 FT |
1226 | if (EFI_ERROR (Status)) {\r |
1227 | return Status;\r | |
1228 | }\r | |
1229 | \r | |
1230 | Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);\r | |
1231 | if (EFI_ERROR (Status)) {\r | |
1232 | return Status;\r | |
1233 | }\r | |
1234 | \r | |
1235 | Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r | |
b23fc39c AB |
1236 | if (EFI_ERROR (Status)) {\r |
1237 | return Status;\r | |
1238 | }\r | |
1239 | \r | |
1240 | //\r | |
1241 | // Notify the SD/MMC override protocol that we are have just initialized\r | |
1242 | // the SD/MMC host controller.\r | |
1243 | //\r | |
1244 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1245 | Status = mOverride->NotifyPhase (\r | |
1246 | Private->ControllerHandle,\r | |
1247 | Slot,\r | |
49c99534 MW |
1248 | EdkiiSdMmcInitHostPost,\r |
1249 | NULL);\r | |
b23fc39c AB |
1250 | if (EFI_ERROR (Status)) {\r |
1251 | DEBUG ((DEBUG_WARN,\r | |
1252 | "%a: SD/MMC post init notifier callback failed - %r\n",\r | |
1253 | __FUNCTION__, Status));\r | |
1254 | }\r | |
1255 | }\r | |
48555339 FT |
1256 | return Status;\r |
1257 | }\r | |
1258 | \r | |
a4708009 TM |
1259 | /**\r |
1260 | Set SD Host Controler control 2 registry according to selected speed.\r | |
1261 | \r | |
1262 | @param[in] ControllerHandle The handle of the controller.\r | |
1263 | @param[in] PciIo The PCI IO protocol instance.\r | |
1264 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1265 | @param[in] Timing The timing to select.\r | |
1266 | \r | |
1267 | @retval EFI_SUCCESS The timing is set successfully.\r | |
1268 | @retval Others The timing isn't set successfully.\r | |
1269 | **/\r | |
1270 | EFI_STATUS\r | |
1271 | SdMmcHcUhsSignaling (\r | |
1272 | IN EFI_HANDLE ControllerHandle,\r | |
1273 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1274 | IN UINT8 Slot,\r | |
1275 | IN SD_MMC_BUS_MODE Timing\r | |
1276 | )\r | |
1277 | {\r | |
1278 | EFI_STATUS Status;\r | |
1279 | UINT8 HostCtrl2;\r | |
1280 | \r | |
1281 | HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;\r | |
1282 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1283 | if (EFI_ERROR (Status)) {\r | |
1284 | return Status;\r | |
1285 | }\r | |
1286 | \r | |
1287 | switch (Timing) {\r | |
1288 | case SdMmcUhsSdr12:\r | |
1289 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;\r | |
1290 | break;\r | |
1291 | case SdMmcUhsSdr25:\r | |
1292 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;\r | |
1293 | break;\r | |
1294 | case SdMmcUhsSdr50:\r | |
1295 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;\r | |
1296 | break;\r | |
1297 | case SdMmcUhsSdr104:\r | |
1298 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;\r | |
1299 | break;\r | |
1300 | case SdMmcUhsDdr50:\r | |
1301 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;\r | |
1302 | break;\r | |
1303 | case SdMmcMmcLegacy:\r | |
1304 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;\r | |
1305 | break;\r | |
1306 | case SdMmcMmcHsSdr:\r | |
1307 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;\r | |
1308 | break;\r | |
1309 | case SdMmcMmcHsDdr:\r | |
1310 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;\r | |
1311 | break;\r | |
1312 | case SdMmcMmcHs200:\r | |
1313 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;\r | |
1314 | break;\r | |
1315 | case SdMmcMmcHs400:\r | |
1316 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;\r | |
1317 | break;\r | |
1318 | default:\r | |
1319 | HostCtrl2 = 0;\r | |
1320 | break;\r | |
1321 | }\r | |
1322 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1323 | if (EFI_ERROR (Status)) {\r | |
1324 | return Status;\r | |
1325 | }\r | |
1326 | \r | |
1327 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1328 | Status = mOverride->NotifyPhase (\r | |
1329 | ControllerHandle,\r | |
1330 | Slot,\r | |
1331 | EdkiiSdMmcUhsSignaling,\r | |
1332 | &Timing\r | |
1333 | );\r | |
1334 | if (EFI_ERROR (Status)) {\r | |
1335 | DEBUG ((\r | |
1336 | DEBUG_ERROR,\r | |
1337 | "%a: SD/MMC uhs signaling notifier callback failed - %r\n",\r | |
1338 | __FUNCTION__,\r | |
1339 | Status\r | |
1340 | ));\r | |
1341 | return Status;\r | |
1342 | }\r | |
1343 | }\r | |
1344 | \r | |
1345 | return EFI_SUCCESS;\r | |
1346 | }\r | |
1347 | \r | |
48555339 FT |
1348 | /**\r |
1349 | Turn on/off LED.\r | |
1350 | \r | |
1351 | @param[in] PciIo The PCI IO protocol instance.\r | |
1352 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1353 | @param[in] On The boolean to turn on/off LED.\r | |
1354 | \r | |
1355 | @retval EFI_SUCCESS The LED is turned on/off successfully.\r | |
1356 | @retval Others The LED isn't turned on/off successfully.\r | |
1357 | \r | |
1358 | **/\r | |
1359 | EFI_STATUS\r | |
1360 | SdMmcHcLedOnOff (\r | |
1361 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1362 | IN UINT8 Slot,\r | |
1363 | IN BOOLEAN On\r | |
1364 | )\r | |
1365 | {\r | |
1366 | EFI_STATUS Status;\r | |
1367 | UINT8 HostCtrl1;\r | |
1368 | \r | |
1369 | if (On) {\r | |
1370 | HostCtrl1 = BIT0;\r | |
1371 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1372 | } else {\r | |
1373 | HostCtrl1 = (UINT8)~BIT0;\r | |
1374 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1375 | }\r | |
1376 | \r | |
1377 | return Status;\r | |
1378 | }\r | |
1379 | \r | |
1380 | /**\r | |
1381 | Build ADMA descriptor table for transfer.\r | |
1382 | \r | |
b5547b9c | 1383 | Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.\r |
48555339 FT |
1384 | \r |
1385 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
b5547b9c | 1386 | @param[in] ControllerVer The version of host controller.\r |
48555339 FT |
1387 | \r |
1388 | @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r | |
1389 | @retval Others The ADMA descriptor table isn't created successfully.\r | |
1390 | \r | |
1391 | **/\r | |
1392 | EFI_STATUS\r | |
1393 | BuildAdmaDescTable (\r | |
b5547b9c AS |
1394 | IN SD_MMC_HC_TRB *Trb,\r |
1395 | IN UINT16 ControllerVer\r | |
48555339 FT |
1396 | )\r |
1397 | {\r | |
1398 | EFI_PHYSICAL_ADDRESS Data;\r | |
1399 | UINT64 DataLen;\r | |
1400 | UINT64 Entries;\r | |
1401 | UINT32 Index;\r | |
1402 | UINT64 Remaining;\r | |
b5547b9c | 1403 | UINT64 Address;\r |
48555339 FT |
1404 | UINTN TableSize;\r |
1405 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1406 | EFI_STATUS Status;\r | |
1407 | UINTN Bytes;\r | |
b5547b9c AS |
1408 | UINT32 AdmaMaxDataPerLine;\r |
1409 | UINT32 DescSize;\r | |
1410 | VOID *AdmaDesc;\r | |
1411 | \r | |
b5547b9c AS |
1412 | AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;\r |
1413 | DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);\r | |
1414 | AdmaDesc = NULL;\r | |
48555339 FT |
1415 | \r |
1416 | Data = Trb->DataPhy;\r | |
1417 | DataLen = Trb->DataLen;\r | |
1418 | PciIo = Trb->Private->PciIo;\r | |
b5547b9c | 1419 | \r |
b5547b9c AS |
1420 | //\r |
1421 | // Check for valid ranges in 32bit ADMA Descriptor Table\r | |
1422 | //\r | |
690d60c0 | 1423 | if ((Trb->Mode == SdMmcAdma32bMode) &&\r |
b5547b9c | 1424 | ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {\r |
48555339 FT |
1425 | return EFI_INVALID_PARAMETER;\r |
1426 | }\r | |
1427 | //\r | |
b5547b9c | 1428 | // Check address field alignment\r |
48555339 | 1429 | //\r |
690d60c0 | 1430 | if (Trb->Mode != SdMmcAdma32bMode) {\r |
b5547b9c AS |
1431 | //\r |
1432 | // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)\r | |
1433 | //\r | |
1434 | if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {\r | |
1435 | DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));\r | |
1436 | }\r | |
1437 | } else {\r | |
1438 | //\r | |
1439 | // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r | |
1440 | //\r | |
1441 | if ((Data & (BIT0 | BIT1)) != 0) {\r | |
1442 | DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r | |
1443 | }\r | |
1444 | }\r | |
690d60c0 AS |
1445 | \r |
1446 | //\r | |
1447 | // Configure 64b ADMA.\r | |
b5547b9c | 1448 | //\r |
690d60c0 AS |
1449 | if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1450 | DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);\r | |
1451 | }else if (Trb->Mode == SdMmcAdma64bV4Mode) {\r | |
1452 | DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);\r | |
1453 | }\r | |
b5547b9c | 1454 | //\r |
690d60c0 AS |
1455 | // Configure 26b data length.\r |
1456 | //\r | |
1457 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
b5547b9c | 1458 | AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;\r |
48555339 FT |
1459 | }\r |
1460 | \r | |
b5547b9c AS |
1461 | Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);\r |
1462 | TableSize = (UINTN)MultU64x32 (Entries, DescSize);\r | |
48555339 FT |
1463 | Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r |
1464 | Status = PciIo->AllocateBuffer (\r | |
1465 | PciIo,\r | |
1466 | AllocateAnyPages,\r | |
1467 | EfiBootServicesData,\r | |
1468 | EFI_SIZE_TO_PAGES (TableSize),\r | |
b5547b9c | 1469 | (VOID **)&AdmaDesc,\r |
48555339 FT |
1470 | 0\r |
1471 | );\r | |
1472 | if (EFI_ERROR (Status)) {\r | |
1473 | return EFI_OUT_OF_RESOURCES;\r | |
1474 | }\r | |
b5547b9c | 1475 | ZeroMem (AdmaDesc, TableSize);\r |
48555339 FT |
1476 | Bytes = TableSize;\r |
1477 | Status = PciIo->Map (\r | |
1478 | PciIo,\r | |
1479 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
b5547b9c | 1480 | AdmaDesc,\r |
48555339 FT |
1481 | &Bytes,\r |
1482 | &Trb->AdmaDescPhy,\r | |
1483 | &Trb->AdmaMap\r | |
1484 | );\r | |
1485 | \r | |
1486 | if (EFI_ERROR (Status) || (Bytes != TableSize)) {\r | |
1487 | //\r | |
1488 | // Map error or unable to map the whole RFis buffer into a contiguous region.\r | |
1489 | //\r | |
1490 | PciIo->FreeBuffer (\r | |
1491 | PciIo,\r | |
1492 | EFI_SIZE_TO_PAGES (TableSize),\r | |
b5547b9c | 1493 | AdmaDesc\r |
48555339 FT |
1494 | );\r |
1495 | return EFI_OUT_OF_RESOURCES;\r | |
1496 | }\r | |
1497 | \r | |
690d60c0 | 1498 | if ((Trb->Mode == SdMmcAdma32bMode) &&\r |
b5547b9c | 1499 | (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r |
48555339 FT |
1500 | //\r |
1501 | // The ADMA doesn't support 64bit addressing.\r | |
1502 | //\r | |
1503 | PciIo->Unmap (\r | |
1504 | PciIo,\r | |
1505 | Trb->AdmaMap\r | |
1506 | );\r | |
1507 | PciIo->FreeBuffer (\r | |
1508 | PciIo,\r | |
1509 | EFI_SIZE_TO_PAGES (TableSize),\r | |
b5547b9c | 1510 | AdmaDesc\r |
48555339 FT |
1511 | );\r |
1512 | return EFI_DEVICE_ERROR;\r | |
1513 | }\r | |
1514 | \r | |
1515 | Remaining = DataLen;\r | |
b5547b9c | 1516 | Address = Data;\r |
690d60c0 | 1517 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
b5547b9c | 1518 | Trb->Adma32Desc = AdmaDesc;\r |
690d60c0 AS |
1519 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1520 | Trb->Adma64V3Desc = AdmaDesc;\r | |
b5547b9c | 1521 | } else {\r |
690d60c0 | 1522 | Trb->Adma64V4Desc = AdmaDesc;\r |
b5547b9c | 1523 | }\r |
690d60c0 | 1524 | \r |
48555339 | 1525 | for (Index = 0; Index < Entries; Index++) {\r |
690d60c0 | 1526 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
b5547b9c AS |
1527 | if (Remaining <= AdmaMaxDataPerLine) {\r |
1528 | Trb->Adma32Desc[Index].Valid = 1;\r | |
1529 | Trb->Adma32Desc[Index].Act = 2;\r | |
690d60c0 | 1530 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r |
46f4c967 | 1531 | Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r |
b5547b9c AS |
1532 | }\r |
1533 | Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r | |
1534 | Trb->Adma32Desc[Index].Address = (UINT32)Address;\r | |
1535 | break;\r | |
1536 | } else {\r | |
1537 | Trb->Adma32Desc[Index].Valid = 1;\r | |
1538 | Trb->Adma32Desc[Index].Act = 2;\r | |
690d60c0 | 1539 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r |
b5547b9c AS |
1540 | Trb->Adma32Desc[Index].UpperLength = 0;\r |
1541 | }\r | |
1542 | Trb->Adma32Desc[Index].LowerLength = 0;\r | |
1543 | Trb->Adma32Desc[Index].Address = (UINT32)Address;\r | |
1544 | }\r | |
690d60c0 AS |
1545 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1546 | if (Remaining <= AdmaMaxDataPerLine) {\r | |
1547 | Trb->Adma64V3Desc[Index].Valid = 1;\r | |
1548 | Trb->Adma64V3Desc[Index].Act = 2;\r | |
1549 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1550 | Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r | |
1551 | }\r | |
1552 | Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r | |
1553 | Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r | |
1554 | Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
1555 | break;\r | |
1556 | } else {\r | |
1557 | Trb->Adma64V3Desc[Index].Valid = 1;\r | |
1558 | Trb->Adma64V3Desc[Index].Act = 2;\r | |
1559 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1560 | Trb->Adma64V3Desc[Index].UpperLength = 0;\r | |
1561 | }\r | |
1562 | Trb->Adma64V3Desc[Index].LowerLength = 0;\r | |
1563 | Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r | |
1564 | Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
1565 | }\r | |
48555339 | 1566 | } else {\r |
b5547b9c | 1567 | if (Remaining <= AdmaMaxDataPerLine) {\r |
690d60c0 AS |
1568 | Trb->Adma64V4Desc[Index].Valid = 1;\r |
1569 | Trb->Adma64V4Desc[Index].Act = 2;\r | |
1570 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1571 | Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r | |
b5547b9c | 1572 | }\r |
690d60c0 AS |
1573 | Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r |
1574 | Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r | |
1575 | Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
b5547b9c AS |
1576 | break;\r |
1577 | } else {\r | |
690d60c0 AS |
1578 | Trb->Adma64V4Desc[Index].Valid = 1;\r |
1579 | Trb->Adma64V4Desc[Index].Act = 2;\r | |
1580 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1581 | Trb->Adma64V4Desc[Index].UpperLength = 0;\r | |
b5547b9c | 1582 | }\r |
690d60c0 AS |
1583 | Trb->Adma64V4Desc[Index].LowerLength = 0;\r |
1584 | Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r | |
1585 | Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
b5547b9c | 1586 | }\r |
48555339 FT |
1587 | }\r |
1588 | \r | |
b5547b9c AS |
1589 | Remaining -= AdmaMaxDataPerLine;\r |
1590 | Address += AdmaMaxDataPerLine;\r | |
48555339 FT |
1591 | }\r |
1592 | \r | |
1593 | //\r | |
1594 | // Set the last descriptor line as end of descriptor table\r | |
1595 | //\r | |
690d60c0 AS |
1596 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
1597 | Trb->Adma32Desc[Index].End = 1;\r | |
1598 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r | |
1599 | Trb->Adma64V3Desc[Index].End = 1;\r | |
1600 | } else {\r | |
1601 | Trb->Adma64V4Desc[Index].End = 1;\r | |
1602 | }\r | |
48555339 FT |
1603 | return EFI_SUCCESS;\r |
1604 | }\r | |
1605 | \r | |
1606 | /**\r | |
1607 | Create a new TRB for the SD/MMC cmd request.\r | |
1608 | \r | |
1609 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1610 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1611 | @param[in] Packet A pointer to the SD command data structure.\r | |
1612 | @param[in] Event If Event is NULL, blocking I/O is performed. If Event is\r | |
1613 | not NULL, then nonblocking I/O is performed, and Event\r | |
1614 | will be signaled when the Packet completes.\r | |
1615 | \r | |
1616 | @return Created Trb or NULL.\r | |
1617 | \r | |
1618 | **/\r | |
1619 | SD_MMC_HC_TRB *\r | |
1620 | SdMmcCreateTrb (\r | |
1621 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1622 | IN UINT8 Slot,\r | |
1623 | IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r | |
1624 | IN EFI_EVENT Event\r | |
1625 | )\r | |
1626 | {\r | |
1627 | SD_MMC_HC_TRB *Trb;\r | |
1628 | EFI_STATUS Status;\r | |
1629 | EFI_TPL OldTpl;\r | |
1630 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r | |
1631 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1632 | UINTN MapLength;\r | |
1633 | \r | |
1634 | Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));\r | |
1635 | if (Trb == NULL) {\r | |
1636 | return NULL;\r | |
1637 | }\r | |
1638 | \r | |
1639 | Trb->Signature = SD_MMC_HC_TRB_SIG;\r | |
1640 | Trb->Slot = Slot;\r | |
1641 | Trb->BlockSize = 0x200;\r | |
1642 | Trb->Packet = Packet;\r | |
1643 | Trb->Event = Event;\r | |
1644 | Trb->Started = FALSE;\r | |
1645 | Trb->Timeout = Packet->Timeout;\r | |
1646 | Trb->Private = Private;\r | |
1647 | \r | |
1648 | if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r | |
1649 | Trb->Data = Packet->InDataBuffer;\r | |
1650 | Trb->DataLen = Packet->InTransferLength;\r | |
1651 | Trb->Read = TRUE;\r | |
1652 | } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r | |
1653 | Trb->Data = Packet->OutDataBuffer;\r | |
1654 | Trb->DataLen = Packet->OutTransferLength;\r | |
1655 | Trb->Read = FALSE;\r | |
1656 | } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r | |
1657 | Trb->Data = NULL;\r | |
1658 | Trb->DataLen = 0;\r | |
1659 | } else {\r | |
1660 | goto Error;\r | |
1661 | }\r | |
1662 | \r | |
54228046 | 1663 | if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r |
e7e89b08 FT |
1664 | Trb->BlockSize = (UINT16)Trb->DataLen;\r |
1665 | }\r | |
1666 | \r | |
1667 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
1668 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
1669 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
1670 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
1671 | Trb->Mode = SdMmcPioMode;\r | |
48555339 | 1672 | } else {\r |
e7e89b08 FT |
1673 | if (Trb->Read) {\r |
1674 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
1675 | } else {\r | |
1676 | Flag = EfiPciIoOperationBusMasterRead;\r | |
48555339 | 1677 | }\r |
48555339 | 1678 | \r |
e7e89b08 FT |
1679 | PciIo = Private->PciIo;\r |
1680 | if (Trb->DataLen != 0) {\r | |
1681 | MapLength = Trb->DataLen;\r | |
1682 | Status = PciIo->Map (\r | |
1683 | PciIo,\r | |
1684 | Flag,\r | |
1685 | Trb->Data,\r | |
1686 | &MapLength,\r | |
1687 | &Trb->DataPhy,\r | |
1688 | &Trb->DataMap\r | |
1689 | );\r | |
1690 | if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {\r | |
1691 | Status = EFI_BAD_BUFFER_SIZE;\r | |
1692 | goto Error;\r | |
1693 | }\r | |
48555339 | 1694 | }\r |
48555339 | 1695 | \r |
e7e89b08 FT |
1696 | if (Trb->DataLen == 0) {\r |
1697 | Trb->Mode = SdMmcNoData;\r | |
1698 | } else if (Private->Capability[Slot].Adma2 != 0) {\r | |
690d60c0 AS |
1699 | Trb->Mode = SdMmcAdma32bMode;\r |
1700 | Trb->AdmaLengthMode = SdMmcAdmaLen16b;\r | |
1701 | if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&\r | |
1702 | (Private->Capability[Slot].SysBus64V3 == 1)) {\r | |
1703 | Trb->Mode = SdMmcAdma64bV3Mode;\r | |
1704 | } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&\r | |
1705 | (Private->Capability[Slot].SysBus64V3 == 1)) ||\r | |
1706 | ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&\r | |
1707 | (Private->Capability[Slot].SysBus64V4 == 1))) {\r | |
1708 | Trb->Mode = SdMmcAdma64bV4Mode;\r | |
1709 | }\r | |
1710 | if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {\r | |
1711 | Trb->AdmaLengthMode = SdMmcAdmaLen26b;\r | |
1712 | }\r | |
b5547b9c | 1713 | Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);\r |
e7e89b08 FT |
1714 | if (EFI_ERROR (Status)) {\r |
1715 | PciIo->Unmap (PciIo, Trb->DataMap);\r | |
1716 | goto Error;\r | |
1717 | }\r | |
1718 | } else if (Private->Capability[Slot].Sdma != 0) {\r | |
1719 | Trb->Mode = SdMmcSdmaMode;\r | |
1720 | } else {\r | |
1721 | Trb->Mode = SdMmcPioMode;\r | |
48555339 | 1722 | }\r |
48555339 FT |
1723 | }\r |
1724 | \r | |
1725 | if (Event != NULL) {\r | |
3b1d8241 | 1726 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r |
48555339 FT |
1727 | InsertTailList (&Private->Queue, &Trb->TrbList);\r |
1728 | gBS->RestoreTPL (OldTpl);\r | |
1729 | }\r | |
1730 | \r | |
1731 | return Trb;\r | |
1732 | \r | |
1733 | Error:\r | |
1734 | SdMmcFreeTrb (Trb);\r | |
1735 | return NULL;\r | |
1736 | }\r | |
1737 | \r | |
1738 | /**\r | |
1739 | Free the resource used by the TRB.\r | |
1740 | \r | |
1741 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1742 | \r | |
1743 | **/\r | |
1744 | VOID\r | |
1745 | SdMmcFreeTrb (\r | |
1746 | IN SD_MMC_HC_TRB *Trb\r | |
1747 | )\r | |
1748 | {\r | |
1749 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1750 | \r | |
1751 | PciIo = Trb->Private->PciIo;\r | |
1752 | \r | |
1753 | if (Trb->AdmaMap != NULL) {\r | |
1754 | PciIo->Unmap (\r | |
1755 | PciIo,\r | |
1756 | Trb->AdmaMap\r | |
1757 | );\r | |
1758 | }\r | |
b5547b9c AS |
1759 | if (Trb->Adma32Desc != NULL) {\r |
1760 | PciIo->FreeBuffer (\r | |
1761 | PciIo,\r | |
1762 | Trb->AdmaPages,\r | |
1763 | Trb->Adma32Desc\r | |
1764 | );\r | |
1765 | }\r | |
690d60c0 | 1766 | if (Trb->Adma64V3Desc != NULL) {\r |
48555339 FT |
1767 | PciIo->FreeBuffer (\r |
1768 | PciIo,\r | |
1769 | Trb->AdmaPages,\r | |
690d60c0 AS |
1770 | Trb->Adma64V3Desc\r |
1771 | );\r | |
1772 | }\r | |
1773 | if (Trb->Adma64V4Desc != NULL) {\r | |
1774 | PciIo->FreeBuffer (\r | |
1775 | PciIo,\r | |
1776 | Trb->AdmaPages,\r | |
1777 | Trb->Adma64V4Desc\r | |
48555339 FT |
1778 | );\r |
1779 | }\r | |
1780 | if (Trb->DataMap != NULL) {\r | |
1781 | PciIo->Unmap (\r | |
1782 | PciIo,\r | |
1783 | Trb->DataMap\r | |
1784 | );\r | |
1785 | }\r | |
1786 | FreePool (Trb);\r | |
1787 | return;\r | |
1788 | }\r | |
1789 | \r | |
1790 | /**\r | |
1791 | Check if the env is ready for execute specified TRB.\r | |
1792 | \r | |
1793 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1794 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1795 | \r | |
1796 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
1797 | @retval EFI_NOT_READY The env is not ready for TRB execution.\r | |
1798 | @retval Others Some erros happen.\r | |
1799 | \r | |
1800 | **/\r | |
1801 | EFI_STATUS\r | |
1802 | SdMmcCheckTrbEnv (\r | |
1803 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1804 | IN SD_MMC_HC_TRB *Trb\r | |
1805 | )\r | |
1806 | {\r | |
1807 | EFI_STATUS Status;\r | |
1808 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1809 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1810 | UINT32 PresentState;\r | |
1811 | \r | |
1812 | Packet = Trb->Packet;\r | |
1813 | \r | |
1814 | if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r | |
1815 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r | |
1816 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {\r | |
1817 | //\r | |
1818 | // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r | |
1819 | // the Present State register to be 0\r | |
1820 | //\r | |
1821 | PresentState = BIT0 | BIT1;\r | |
48555339 FT |
1822 | } else {\r |
1823 | //\r | |
1824 | // Wait Command Inhibit (CMD) in the Present State register\r | |
1825 | // to be 0\r | |
1826 | //\r | |
1827 | PresentState = BIT0;\r | |
1828 | }\r | |
1829 | \r | |
1830 | PciIo = Private->PciIo;\r | |
1831 | Status = SdMmcHcCheckMmioSet (\r | |
1832 | PciIo,\r | |
1833 | Trb->Slot,\r | |
1834 | SD_MMC_HC_PRESENT_STATE,\r | |
1835 | sizeof (PresentState),\r | |
1836 | PresentState,\r | |
1837 | 0\r | |
1838 | );\r | |
1839 | \r | |
1840 | return Status;\r | |
1841 | }\r | |
1842 | \r | |
1843 | /**\r | |
1844 | Wait for the env to be ready for execute specified TRB.\r | |
1845 | \r | |
1846 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1847 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1848 | \r | |
1849 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
1850 | @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r | |
1851 | @retval Others Some erros happen.\r | |
1852 | \r | |
1853 | **/\r | |
1854 | EFI_STATUS\r | |
1855 | SdMmcWaitTrbEnv (\r | |
1856 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1857 | IN SD_MMC_HC_TRB *Trb\r | |
1858 | )\r | |
1859 | {\r | |
1860 | EFI_STATUS Status;\r | |
1861 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1862 | UINT64 Timeout;\r | |
1863 | BOOLEAN InfiniteWait;\r | |
1864 | \r | |
1865 | //\r | |
1866 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
1867 | //\r | |
1868 | Packet = Trb->Packet;\r | |
1869 | Timeout = Packet->Timeout;\r | |
1870 | if (Timeout == 0) {\r | |
1871 | InfiniteWait = TRUE;\r | |
1872 | } else {\r | |
1873 | InfiniteWait = FALSE;\r | |
1874 | }\r | |
1875 | \r | |
1876 | while (InfiniteWait || (Timeout > 0)) {\r | |
1877 | //\r | |
1878 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
1879 | //\r | |
1880 | Status = SdMmcCheckTrbEnv (Private, Trb);\r | |
1881 | if (Status != EFI_NOT_READY) {\r | |
1882 | return Status;\r | |
1883 | }\r | |
1884 | //\r | |
1885 | // Stall for 1 microsecond.\r | |
1886 | //\r | |
1887 | gBS->Stall (1);\r | |
1888 | \r | |
1889 | Timeout--;\r | |
1890 | }\r | |
1891 | \r | |
1892 | return EFI_TIMEOUT;\r | |
1893 | }\r | |
1894 | \r | |
1895 | /**\r | |
1896 | Execute the specified TRB.\r | |
1897 | \r | |
1898 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1899 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1900 | \r | |
1901 | @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r | |
1902 | @retval Others Some erros happen when sending this request to the host controller.\r | |
1903 | \r | |
1904 | **/\r | |
1905 | EFI_STATUS\r | |
1906 | SdMmcExecTrb (\r | |
1907 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1908 | IN SD_MMC_HC_TRB *Trb\r | |
1909 | )\r | |
1910 | {\r | |
1911 | EFI_STATUS Status;\r | |
1912 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1913 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1914 | UINT16 Cmd;\r | |
1915 | UINT16 IntStatus;\r | |
1916 | UINT32 Argument;\r | |
b5547b9c | 1917 | UINT32 BlkCount;\r |
48555339 FT |
1918 | UINT16 BlkSize;\r |
1919 | UINT16 TransMode;\r | |
1920 | UINT8 HostCtrl1;\r | |
b5547b9c | 1921 | UINT64 SdmaAddr;\r |
48555339 | 1922 | UINT64 AdmaAddr;\r |
b5547b9c AS |
1923 | BOOLEAN AddressingMode64;\r |
1924 | \r | |
1925 | AddressingMode64 = FALSE;\r | |
48555339 FT |
1926 | \r |
1927 | Packet = Trb->Packet;\r | |
1928 | PciIo = Trb->Private->PciIo;\r | |
1929 | //\r | |
1930 | // Clear all bits in Error Interrupt Status Register\r | |
1931 | //\r | |
1932 | IntStatus = 0xFFFF;\r | |
1933 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
1934 | if (EFI_ERROR (Status)) {\r | |
1935 | return Status;\r | |
1936 | }\r | |
1937 | //\r | |
1938 | // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.\r | |
1939 | //\r | |
1940 | IntStatus = 0xFF3F;\r | |
1941 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
1942 | if (EFI_ERROR (Status)) {\r | |
1943 | return Status;\r | |
1944 | }\r | |
690d60c0 AS |
1945 | \r |
1946 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
1947 | Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r | |
1948 | SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);\r | |
1949 | if (!EFI_ERROR (Status)) {\r | |
1950 | AddressingMode64 = TRUE;\r | |
1951 | }\r | |
1952 | }\r | |
1953 | \r | |
48555339 FT |
1954 | //\r |
1955 | // Set Host Control 1 register DMA Select field\r | |
1956 | //\r | |
690d60c0 AS |
1957 | if ((Trb->Mode == SdMmcAdma32bMode) ||\r |
1958 | (Trb->Mode == SdMmcAdma64bV4Mode)) {\r | |
48555339 FT |
1959 | HostCtrl1 = BIT4;\r |
1960 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1961 | if (EFI_ERROR (Status)) {\r | |
1962 | return Status;\r | |
1963 | }\r | |
690d60c0 AS |
1964 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1965 | HostCtrl1 = BIT4|BIT3;\r | |
1966 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1967 | if (EFI_ERROR (Status)) {\r | |
1968 | return Status;\r | |
1969 | }\r | |
48555339 FT |
1970 | }\r |
1971 | \r | |
1972 | SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r | |
1973 | \r | |
1974 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
b5547b9c AS |
1975 | if ((!AddressingMode64) &&\r |
1976 | ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {\r | |
48555339 FT |
1977 | return EFI_INVALID_PARAMETER;\r |
1978 | }\r | |
1979 | \r | |
b5547b9c AS |
1980 | SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;\r |
1981 | \r | |
1982 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
1983 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);\r | |
1984 | } else {\r | |
1985 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);\r | |
1986 | }\r | |
1987 | \r | |
48555339 FT |
1988 | if (EFI_ERROR (Status)) {\r |
1989 | return Status;\r | |
1990 | }\r | |
690d60c0 AS |
1991 | } else if ((Trb->Mode == SdMmcAdma32bMode) ||\r |
1992 | (Trb->Mode == SdMmcAdma64bV3Mode) ||\r | |
1993 | (Trb->Mode == SdMmcAdma64bV4Mode)) {\r | |
48555339 FT |
1994 | AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;\r |
1995 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r | |
1996 | if (EFI_ERROR (Status)) {\r | |
1997 | return Status;\r | |
1998 | }\r | |
1999 | }\r | |
2000 | \r | |
2001 | BlkSize = Trb->BlockSize;\r | |
2002 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
2003 | //\r | |
2004 | // Set SDMA boundary to be 512K bytes.\r | |
2005 | //\r | |
2006 | BlkSize |= 0x7000;\r | |
2007 | }\r | |
2008 | \r | |
2009 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r | |
2010 | if (EFI_ERROR (Status)) {\r | |
2011 | return Status;\r | |
2012 | }\r | |
2013 | \r | |
e7e89b08 FT |
2014 | BlkCount = 0;\r |
2015 | if (Trb->Mode != SdMmcNoData) {\r | |
2016 | //\r | |
2017 | // Calcuate Block Count.\r | |
2018 | //\r | |
b5547b9c AS |
2019 | BlkCount = (Trb->DataLen / Trb->BlockSize);\r |
2020 | }\r | |
2021 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {\r | |
2022 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);\r | |
2023 | } else {\r | |
2024 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);\r | |
e7e89b08 | 2025 | }\r |
48555339 FT |
2026 | if (EFI_ERROR (Status)) {\r |
2027 | return Status;\r | |
2028 | }\r | |
2029 | \r | |
2030 | Argument = Packet->SdMmcCmdBlk->CommandArgument;\r | |
2031 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r | |
2032 | if (EFI_ERROR (Status)) {\r | |
2033 | return Status;\r | |
2034 | }\r | |
2035 | \r | |
2036 | TransMode = 0;\r | |
2037 | if (Trb->Mode != SdMmcNoData) {\r | |
2038 | if (Trb->Mode != SdMmcPioMode) {\r | |
2039 | TransMode |= BIT0;\r | |
2040 | }\r | |
2041 | if (Trb->Read) {\r | |
2042 | TransMode |= BIT4;\r | |
2043 | }\r | |
e7e89b08 | 2044 | if (BlkCount > 1) {\r |
48555339 FT |
2045 | TransMode |= BIT5 | BIT1;\r |
2046 | }\r | |
2047 | //\r | |
2048 | // Only SD memory card needs to use AUTO CMD12 feature.\r | |
2049 | //\r | |
2050 | if (Private->Slot[Trb->Slot].CardType == SdCardType) {\r | |
2051 | if (BlkCount > 1) {\r | |
2052 | TransMode |= BIT2;\r | |
2053 | }\r | |
2054 | }\r | |
2055 | }\r | |
2056 | \r | |
2057 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r | |
2058 | if (EFI_ERROR (Status)) {\r | |
2059 | return Status;\r | |
2060 | }\r | |
2061 | \r | |
2062 | Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);\r | |
2063 | if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {\r | |
2064 | Cmd |= BIT5;\r | |
2065 | }\r | |
2066 | //\r | |
2067 | // Convert ResponseType to value\r | |
2068 | //\r | |
2069 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
2070 | switch (Packet->SdMmcCmdBlk->ResponseType) {\r | |
2071 | case SdMmcResponseTypeR1:\r | |
2072 | case SdMmcResponseTypeR5:\r | |
2073 | case SdMmcResponseTypeR6:\r | |
2074 | case SdMmcResponseTypeR7:\r | |
2075 | Cmd |= (BIT1 | BIT3 | BIT4);\r | |
2076 | break;\r | |
2077 | case SdMmcResponseTypeR2:\r | |
2078 | Cmd |= (BIT0 | BIT3);\r | |
2079 | break;\r | |
2080 | case SdMmcResponseTypeR3:\r | |
2081 | case SdMmcResponseTypeR4:\r | |
2082 | Cmd |= BIT1;\r | |
2083 | break;\r | |
2084 | case SdMmcResponseTypeR1b:\r | |
2085 | case SdMmcResponseTypeR5b:\r | |
2086 | Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r | |
2087 | break;\r | |
2088 | default:\r | |
2089 | ASSERT (FALSE);\r | |
2090 | break;\r | |
2091 | }\r | |
2092 | }\r | |
2093 | //\r | |
2094 | // Execute cmd\r | |
2095 | //\r | |
2096 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r | |
2097 | return Status;\r | |
2098 | }\r | |
2099 | \r | |
2100 | /**\r | |
2101 | Check the TRB execution result.\r | |
2102 | \r | |
2103 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2104 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2105 | \r | |
2106 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
2107 | @retval EFI_NOT_READY The TRB is not completed for execution.\r | |
2108 | @retval Others Some erros happen when executing this request.\r | |
2109 | \r | |
2110 | **/\r | |
2111 | EFI_STATUS\r | |
2112 | SdMmcCheckTrbResult (\r | |
2113 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2114 | IN SD_MMC_HC_TRB *Trb\r | |
2115 | )\r | |
2116 | {\r | |
2117 | EFI_STATUS Status;\r | |
2118 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2119 | UINT16 IntStatus;\r | |
2120 | UINT32 Response[4];\r | |
b5547b9c | 2121 | UINT64 SdmaAddr;\r |
48555339 FT |
2122 | UINT8 Index;\r |
2123 | UINT8 SwReset;\r | |
e7e89b08 | 2124 | UINT32 PioLength;\r |
48555339 FT |
2125 | \r |
2126 | SwReset = 0;\r | |
2127 | Packet = Trb->Packet;\r | |
2128 | //\r | |
2129 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2130 | //\r | |
2131 | Status = SdMmcHcRwMmio (\r | |
2132 | Private->PciIo,\r | |
2133 | Trb->Slot,\r | |
2134 | SD_MMC_HC_NOR_INT_STS,\r | |
2135 | TRUE,\r | |
2136 | sizeof (IntStatus),\r | |
2137 | &IntStatus\r | |
2138 | );\r | |
2139 | if (EFI_ERROR (Status)) {\r | |
2140 | goto Done;\r | |
2141 | }\r | |
2142 | //\r | |
2143 | // Check Transfer Complete bit is set or not.\r | |
2144 | //\r | |
2145 | if ((IntStatus & BIT1) == BIT1) {\r | |
2146 | if ((IntStatus & BIT15) == BIT15) {\r | |
2147 | //\r | |
2148 | // Read Error Interrupt Status register to check if the error is\r | |
2149 | // Data Timeout Error.\r | |
2150 | // If yes, treat it as success as Transfer Complete has higher\r | |
2151 | // priority than Data Timeout Error.\r | |
2152 | //\r | |
2153 | Status = SdMmcHcRwMmio (\r | |
2154 | Private->PciIo,\r | |
2155 | Trb->Slot,\r | |
2156 | SD_MMC_HC_ERR_INT_STS,\r | |
2157 | TRUE,\r | |
2158 | sizeof (IntStatus),\r | |
2159 | &IntStatus\r | |
2160 | );\r | |
2161 | if (!EFI_ERROR (Status)) {\r | |
2162 | if ((IntStatus & BIT4) == BIT4) {\r | |
2163 | Status = EFI_SUCCESS;\r | |
2164 | } else {\r | |
2165 | Status = EFI_DEVICE_ERROR;\r | |
2166 | }\r | |
2167 | }\r | |
2168 | }\r | |
2169 | \r | |
2170 | goto Done;\r | |
2171 | }\r | |
2172 | //\r | |
2173 | // Check if there is a error happened during cmd execution.\r | |
2174 | // If yes, then do error recovery procedure to follow SD Host Controller\r | |
2175 | // Simplified Spec 3.0 section 3.10.1.\r | |
2176 | //\r | |
2177 | if ((IntStatus & BIT15) == BIT15) {\r | |
2178 | Status = SdMmcHcRwMmio (\r | |
2179 | Private->PciIo,\r | |
2180 | Trb->Slot,\r | |
2181 | SD_MMC_HC_ERR_INT_STS,\r | |
2182 | TRUE,\r | |
2183 | sizeof (IntStatus),\r | |
2184 | &IntStatus\r | |
2185 | );\r | |
2186 | if (EFI_ERROR (Status)) {\r | |
2187 | goto Done;\r | |
2188 | }\r | |
2189 | if ((IntStatus & 0x0F) != 0) {\r | |
2190 | SwReset |= BIT1;\r | |
2191 | }\r | |
2192 | if ((IntStatus & 0xF0) != 0) {\r | |
2193 | SwReset |= BIT2;\r | |
2194 | }\r | |
2195 | \r | |
2196 | Status = SdMmcHcRwMmio (\r | |
2197 | Private->PciIo,\r | |
2198 | Trb->Slot,\r | |
2199 | SD_MMC_HC_SW_RST,\r | |
2200 | FALSE,\r | |
2201 | sizeof (SwReset),\r | |
2202 | &SwReset\r | |
2203 | );\r | |
2204 | if (EFI_ERROR (Status)) {\r | |
2205 | goto Done;\r | |
2206 | }\r | |
2207 | Status = SdMmcHcWaitMmioSet (\r | |
2208 | Private->PciIo,\r | |
2209 | Trb->Slot,\r | |
2210 | SD_MMC_HC_SW_RST,\r | |
2211 | sizeof (SwReset),\r | |
2212 | 0xFF,\r | |
2213 | 0,\r | |
2214 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
2215 | );\r | |
2216 | if (EFI_ERROR (Status)) {\r | |
2217 | goto Done;\r | |
2218 | }\r | |
2219 | \r | |
2220 | Status = EFI_DEVICE_ERROR;\r | |
2221 | goto Done;\r | |
2222 | }\r | |
2223 | //\r | |
2224 | // Check if DMA interrupt is signalled for the SDMA transfer.\r | |
2225 | //\r | |
2226 | if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r | |
2227 | //\r | |
2228 | // Clear DMA interrupt bit.\r | |
2229 | //\r | |
2230 | IntStatus = BIT3;\r | |
2231 | Status = SdMmcHcRwMmio (\r | |
2232 | Private->PciIo,\r | |
2233 | Trb->Slot,\r | |
2234 | SD_MMC_HC_NOR_INT_STS,\r | |
2235 | FALSE,\r | |
2236 | sizeof (IntStatus),\r | |
2237 | &IntStatus\r | |
2238 | );\r | |
2239 | if (EFI_ERROR (Status)) {\r | |
2240 | goto Done;\r | |
2241 | }\r | |
2242 | //\r | |
2243 | // Update SDMA Address register.\r | |
2244 | //\r | |
b5547b9c AS |
2245 | SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r |
2246 | \r | |
2247 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
2248 | Status = SdMmcHcRwMmio (\r | |
2249 | Private->PciIo,\r | |
2250 | Trb->Slot,\r | |
2251 | SD_MMC_HC_ADMA_SYS_ADDR,\r | |
2252 | FALSE,\r | |
2253 | sizeof (UINT64),\r | |
2254 | &SdmaAddr\r | |
2255 | );\r | |
2256 | } else {\r | |
2257 | Status = SdMmcHcRwMmio (\r | |
48555339 FT |
2258 | Private->PciIo,\r |
2259 | Trb->Slot,\r | |
2260 | SD_MMC_HC_SDMA_ADDR,\r | |
2261 | FALSE,\r | |
2262 | sizeof (UINT32),\r | |
2263 | &SdmaAddr\r | |
2264 | );\r | |
b5547b9c AS |
2265 | }\r |
2266 | \r | |
48555339 FT |
2267 | if (EFI_ERROR (Status)) {\r |
2268 | goto Done;\r | |
2269 | }\r | |
b5547b9c | 2270 | Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;\r |
48555339 FT |
2271 | }\r |
2272 | \r | |
2273 | if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&\r | |
2274 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&\r | |
2275 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {\r | |
2276 | if ((IntStatus & BIT0) == BIT0) {\r | |
2277 | Status = EFI_SUCCESS;\r | |
2278 | goto Done;\r | |
2279 | }\r | |
2280 | }\r | |
2281 | \r | |
2282 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
2283 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
2284 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
2285 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
2286 | //\r | |
e7e89b08 FT |
2287 | // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,\r |
2288 | // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.\r | |
2289 | // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.\r | |
48555339 | 2290 | //\r |
e7e89b08 FT |
2291 | if ((IntStatus & BIT5) == BIT5) {\r |
2292 | //\r | |
2293 | // Clear Buffer Read Ready interrupt at first.\r | |
2294 | //\r | |
2295 | IntStatus = BIT5;\r | |
2296 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
2297 | //\r | |
2298 | // Read data out from Buffer Port register\r | |
2299 | //\r | |
2300 | for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {\r | |
2301 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);\r | |
2302 | }\r | |
2303 | Status = EFI_SUCCESS;\r | |
2304 | goto Done;\r | |
2305 | }\r | |
48555339 FT |
2306 | }\r |
2307 | \r | |
2308 | Status = EFI_NOT_READY;\r | |
2309 | Done:\r | |
2310 | //\r | |
2311 | // Get response data when the cmd is executed successfully.\r | |
2312 | //\r | |
2313 | if (!EFI_ERROR (Status)) {\r | |
2314 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
2315 | for (Index = 0; Index < 4; Index++) {\r | |
2316 | Status = SdMmcHcRwMmio (\r | |
2317 | Private->PciIo,\r | |
2318 | Trb->Slot,\r | |
2319 | SD_MMC_HC_RESPONSE + Index * 4,\r | |
2320 | TRUE,\r | |
2321 | sizeof (UINT32),\r | |
2322 | &Response[Index]\r | |
2323 | );\r | |
2324 | if (EFI_ERROR (Status)) {\r | |
2325 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
2326 | return Status;\r | |
2327 | }\r | |
2328 | }\r | |
2329 | CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));\r | |
2330 | }\r | |
2331 | }\r | |
2332 | \r | |
2333 | if (Status != EFI_NOT_READY) {\r | |
2334 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
2335 | }\r | |
2336 | \r | |
2337 | return Status;\r | |
2338 | }\r | |
2339 | \r | |
2340 | /**\r | |
2341 | Wait for the TRB execution result.\r | |
2342 | \r | |
2343 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2344 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2345 | \r | |
2346 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
2347 | @retval Others Some erros happen when executing this request.\r | |
2348 | \r | |
2349 | **/\r | |
2350 | EFI_STATUS\r | |
2351 | SdMmcWaitTrbResult (\r | |
2352 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2353 | IN SD_MMC_HC_TRB *Trb\r | |
2354 | )\r | |
2355 | {\r | |
2356 | EFI_STATUS Status;\r | |
2357 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2358 | UINT64 Timeout;\r | |
2359 | BOOLEAN InfiniteWait;\r | |
2360 | \r | |
2361 | Packet = Trb->Packet;\r | |
2362 | //\r | |
2363 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
2364 | //\r | |
2365 | Timeout = Packet->Timeout;\r | |
2366 | if (Timeout == 0) {\r | |
2367 | InfiniteWait = TRUE;\r | |
2368 | } else {\r | |
2369 | InfiniteWait = FALSE;\r | |
2370 | }\r | |
2371 | \r | |
2372 | while (InfiniteWait || (Timeout > 0)) {\r | |
2373 | //\r | |
2374 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2375 | //\r | |
2376 | Status = SdMmcCheckTrbResult (Private, Trb);\r | |
2377 | if (Status != EFI_NOT_READY) {\r | |
2378 | return Status;\r | |
2379 | }\r | |
2380 | //\r | |
2381 | // Stall for 1 microsecond.\r | |
2382 | //\r | |
2383 | gBS->Stall (1);\r | |
2384 | \r | |
2385 | Timeout--;\r | |
2386 | }\r | |
2387 | \r | |
2388 | return EFI_TIMEOUT;\r | |
2389 | }\r | |
2390 | \r |