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48555339 FT |
1 | /** @file\r |
2 | This driver is used to manage SD/MMC PCI host controllers which are compliance\r | |
3 | with SD Host Controller Simplified Specification version 3.00.\r | |
4 | \r | |
5 | It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r | |
6 | \r | |
54228046 | 7 | Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r |
48555339 FT |
8 | This program and the accompanying materials\r |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #include "SdMmcPciHcDxe.h"\r | |
19 | \r | |
20 | /**\r | |
21 | Dump the content of SD/MMC host controller's Capability Register.\r | |
22 | \r | |
23 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
24 | @param[in] Capability The buffer to store the capability data.\r | |
25 | \r | |
26 | **/\r | |
27 | VOID\r | |
28 | DumpCapabilityReg (\r | |
29 | IN UINT8 Slot,\r | |
30 | IN SD_MMC_HC_SLOT_CAP *Capability\r | |
31 | )\r | |
32 | {\r | |
33 | //\r | |
34 | // Dump Capability Data\r | |
35 | //\r | |
e27ccaba FT |
36 | DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));\r |
37 | DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));\r | |
38 | DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));\r | |
39 | DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));\r | |
40 | DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));\r | |
41 | DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));\r | |
42 | DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));\r | |
43 | DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));\r | |
44 | DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));\r | |
45 | DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r | |
46 | DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r | |
47 | DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r | |
48 | DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));\r | |
49 | DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r | |
50 | DEBUG ((DEBUG_INFO, " SlotType "));\r | |
48555339 | 51 | if (Capability->SlotType == 0x00) {\r |
e27ccaba | 52 | DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));\r |
48555339 | 53 | } else if (Capability->SlotType == 0x01) {\r |
e27ccaba | 54 | DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));\r |
48555339 | 55 | } else if (Capability->SlotType == 0x02) {\r |
e27ccaba | 56 | DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));\r |
48555339 | 57 | } else {\r |
e27ccaba | 58 | DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));\r |
48555339 | 59 | }\r |
e27ccaba FT |
60 | DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));\r |
61 | DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));\r | |
62 | DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));\r | |
63 | DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));\r | |
64 | DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));\r | |
65 | DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));\r | |
66 | DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));\r | |
48555339 | 67 | if (Capability->TimerCount == 0) {\r |
e27ccaba | 68 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));\r |
48555339 | 69 | } else {\r |
e27ccaba | 70 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));\r |
48555339 | 71 | }\r |
e27ccaba FT |
72 | DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));\r |
73 | DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));\r | |
74 | DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));\r | |
75 | DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));\r | |
48555339 FT |
76 | return;\r |
77 | }\r | |
78 | \r | |
79 | /**\r | |
80 | Read SlotInfo register from SD/MMC host controller pci config space.\r | |
81 | \r | |
82 | @param[in] PciIo The PCI IO protocol instance.\r | |
83 | @param[out] FirstBar The buffer to store the first BAR value.\r | |
84 | @param[out] SlotNum The buffer to store the supported slot number.\r | |
85 | \r | |
86 | @retval EFI_SUCCESS The operation succeeds.\r | |
87 | @retval Others The operation fails.\r | |
88 | \r | |
89 | **/\r | |
90 | EFI_STATUS\r | |
91 | EFIAPI\r | |
92 | SdMmcHcGetSlotInfo (\r | |
93 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
94 | OUT UINT8 *FirstBar,\r | |
95 | OUT UINT8 *SlotNum\r | |
96 | )\r | |
97 | {\r | |
98 | EFI_STATUS Status;\r | |
99 | SD_MMC_HC_SLOT_INFO SlotInfo;\r | |
100 | \r | |
101 | Status = PciIo->Pci.Read (\r | |
102 | PciIo,\r | |
103 | EfiPciIoWidthUint8,\r | |
104 | SD_MMC_HC_SLOT_OFFSET,\r | |
105 | sizeof (SlotInfo),\r | |
106 | &SlotInfo\r | |
107 | );\r | |
108 | if (EFI_ERROR (Status)) {\r | |
109 | return Status;\r | |
110 | }\r | |
111 | \r | |
112 | *FirstBar = SlotInfo.FirstBar;\r | |
113 | *SlotNum = SlotInfo.SlotNum + 1;\r | |
114 | ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);\r | |
115 | return EFI_SUCCESS;\r | |
116 | }\r | |
117 | \r | |
118 | /**\r | |
119 | Read/Write specified SD/MMC host controller mmio register.\r | |
120 | \r | |
121 | @param[in] PciIo The PCI IO protocol instance.\r | |
122 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
123 | header to use as the base address for the memory\r | |
124 | operation to perform.\r | |
125 | @param[in] Offset The offset within the selected BAR to start the\r | |
126 | memory operation.\r | |
127 | @param[in] Read A boolean to indicate it's read or write operation.\r | |
128 | @param[in] Count The width of the mmio register in bytes.\r | |
129 | Must be 1, 2 , 4 or 8 bytes.\r | |
130 | @param[in, out] Data For read operations, the destination buffer to store\r | |
131 | the results. For write operations, the source buffer\r | |
132 | to write data from. The caller is responsible for\r | |
133 | having ownership of the data buffer and ensuring its\r | |
134 | size not less than Count bytes.\r | |
135 | \r | |
136 | @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r | |
137 | @retval EFI_SUCCESS The read/write operation succeeds.\r | |
138 | @retval Others The read/write operation fails.\r | |
139 | \r | |
140 | **/\r | |
141 | EFI_STATUS\r | |
142 | EFIAPI\r | |
143 | SdMmcHcRwMmio (\r | |
144 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
145 | IN UINT8 BarIndex,\r | |
146 | IN UINT32 Offset,\r | |
147 | IN BOOLEAN Read,\r | |
148 | IN UINT8 Count,\r | |
149 | IN OUT VOID *Data\r | |
150 | )\r | |
151 | {\r | |
152 | EFI_STATUS Status;\r | |
153 | \r | |
154 | if ((PciIo == NULL) || (Data == NULL)) {\r | |
155 | return EFI_INVALID_PARAMETER;\r | |
156 | }\r | |
157 | \r | |
158 | if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {\r | |
159 | return EFI_INVALID_PARAMETER;\r | |
160 | }\r | |
161 | \r | |
162 | if (Read) {\r | |
163 | Status = PciIo->Mem.Read (\r | |
164 | PciIo,\r | |
165 | EfiPciIoWidthUint8,\r | |
166 | BarIndex,\r | |
167 | (UINT64) Offset,\r | |
168 | Count,\r | |
169 | Data\r | |
170 | );\r | |
171 | } else {\r | |
172 | Status = PciIo->Mem.Write (\r | |
173 | PciIo,\r | |
174 | EfiPciIoWidthUint8,\r | |
175 | BarIndex,\r | |
176 | (UINT64) Offset,\r | |
177 | Count,\r | |
178 | Data\r | |
179 | );\r | |
180 | }\r | |
181 | \r | |
182 | return Status;\r | |
183 | }\r | |
184 | \r | |
185 | /**\r | |
186 | Do OR operation with the value of the specified SD/MMC host controller mmio register.\r | |
187 | \r | |
188 | @param[in] PciIo The PCI IO protocol instance.\r | |
189 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
190 | header to use as the base address for the memory\r | |
191 | operation to perform.\r | |
192 | @param[in] Offset The offset within the selected BAR to start the\r | |
193 | memory operation.\r | |
194 | @param[in] Count The width of the mmio register in bytes.\r | |
195 | Must be 1, 2 , 4 or 8 bytes.\r | |
196 | @param[in] OrData The pointer to the data used to do OR operation.\r | |
197 | The caller is responsible for having ownership of\r | |
198 | the data buffer and ensuring its size not less than\r | |
199 | Count bytes.\r | |
200 | \r | |
201 | @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r | |
202 | @retval EFI_SUCCESS The OR operation succeeds.\r | |
203 | @retval Others The OR operation fails.\r | |
204 | \r | |
205 | **/\r | |
206 | EFI_STATUS\r | |
207 | EFIAPI\r | |
208 | SdMmcHcOrMmio (\r | |
209 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
210 | IN UINT8 BarIndex,\r | |
211 | IN UINT32 Offset,\r | |
212 | IN UINT8 Count,\r | |
213 | IN VOID *OrData\r | |
214 | )\r | |
215 | {\r | |
216 | EFI_STATUS Status;\r | |
217 | UINT64 Data;\r | |
218 | UINT64 Or;\r | |
219 | \r | |
220 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
221 | if (EFI_ERROR (Status)) {\r | |
222 | return Status;\r | |
223 | }\r | |
224 | \r | |
225 | if (Count == 1) {\r | |
226 | Or = *(UINT8*) OrData;\r | |
227 | } else if (Count == 2) {\r | |
228 | Or = *(UINT16*) OrData;\r | |
229 | } else if (Count == 4) {\r | |
230 | Or = *(UINT32*) OrData;\r | |
231 | } else if (Count == 8) {\r | |
232 | Or = *(UINT64*) OrData;\r | |
233 | } else {\r | |
234 | return EFI_INVALID_PARAMETER;\r | |
235 | }\r | |
236 | \r | |
237 | Data |= Or;\r | |
238 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
239 | \r | |
240 | return Status;\r | |
241 | }\r | |
242 | \r | |
243 | /**\r | |
244 | Do AND operation with the value of the specified SD/MMC host controller mmio register.\r | |
245 | \r | |
246 | @param[in] PciIo The PCI IO protocol instance.\r | |
247 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
248 | header to use as the base address for the memory\r | |
249 | operation to perform.\r | |
250 | @param[in] Offset The offset within the selected BAR to start the\r | |
251 | memory operation.\r | |
252 | @param[in] Count The width of the mmio register in bytes.\r | |
253 | Must be 1, 2 , 4 or 8 bytes.\r | |
254 | @param[in] AndData The pointer to the data used to do AND operation.\r | |
255 | The caller is responsible for having ownership of\r | |
256 | the data buffer and ensuring its size not less than\r | |
257 | Count bytes.\r | |
258 | \r | |
259 | @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r | |
260 | @retval EFI_SUCCESS The AND operation succeeds.\r | |
261 | @retval Others The AND operation fails.\r | |
262 | \r | |
263 | **/\r | |
264 | EFI_STATUS\r | |
265 | EFIAPI\r | |
266 | SdMmcHcAndMmio (\r | |
267 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
268 | IN UINT8 BarIndex,\r | |
269 | IN UINT32 Offset,\r | |
270 | IN UINT8 Count,\r | |
271 | IN VOID *AndData\r | |
272 | )\r | |
273 | {\r | |
274 | EFI_STATUS Status;\r | |
275 | UINT64 Data;\r | |
276 | UINT64 And;\r | |
277 | \r | |
278 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
279 | if (EFI_ERROR (Status)) {\r | |
280 | return Status;\r | |
281 | }\r | |
282 | \r | |
283 | if (Count == 1) {\r | |
284 | And = *(UINT8*) AndData;\r | |
285 | } else if (Count == 2) {\r | |
286 | And = *(UINT16*) AndData;\r | |
287 | } else if (Count == 4) {\r | |
288 | And = *(UINT32*) AndData;\r | |
289 | } else if (Count == 8) {\r | |
290 | And = *(UINT64*) AndData;\r | |
291 | } else {\r | |
292 | return EFI_INVALID_PARAMETER;\r | |
293 | }\r | |
294 | \r | |
295 | Data &= And;\r | |
296 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
297 | \r | |
298 | return Status;\r | |
299 | }\r | |
300 | \r | |
301 | /**\r | |
302 | Wait for the value of the specified MMIO register set to the test value.\r | |
303 | \r | |
304 | @param[in] PciIo The PCI IO protocol instance.\r | |
305 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
306 | header to use as the base address for the memory\r | |
307 | operation to perform.\r | |
308 | @param[in] Offset The offset within the selected BAR to start the\r | |
309 | memory operation.\r | |
310 | @param[in] Count The width of the mmio register in bytes.\r | |
311 | Must be 1, 2, 4 or 8 bytes.\r | |
312 | @param[in] MaskValue The mask value of memory.\r | |
313 | @param[in] TestValue The test value of memory.\r | |
314 | \r | |
315 | @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r | |
316 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
317 | @retval Others The MMIO operation fails.\r | |
318 | \r | |
319 | **/\r | |
320 | EFI_STATUS\r | |
321 | EFIAPI\r | |
322 | SdMmcHcCheckMmioSet (\r | |
323 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
324 | IN UINT8 BarIndex,\r | |
325 | IN UINT32 Offset,\r | |
326 | IN UINT8 Count,\r | |
327 | IN UINT64 MaskValue,\r | |
328 | IN UINT64 TestValue\r | |
329 | )\r | |
330 | {\r | |
331 | EFI_STATUS Status;\r | |
332 | UINT64 Value;\r | |
333 | \r | |
334 | //\r | |
335 | // Access PCI MMIO space to see if the value is the tested one.\r | |
336 | //\r | |
337 | Value = 0;\r | |
338 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);\r | |
339 | if (EFI_ERROR (Status)) {\r | |
340 | return Status;\r | |
341 | }\r | |
342 | \r | |
343 | Value &= MaskValue;\r | |
344 | \r | |
345 | if (Value == TestValue) {\r | |
346 | return EFI_SUCCESS;\r | |
347 | }\r | |
348 | \r | |
349 | return EFI_NOT_READY;\r | |
350 | }\r | |
351 | \r | |
352 | /**\r | |
353 | Wait for the value of the specified MMIO register set to the test value.\r | |
354 | \r | |
355 | @param[in] PciIo The PCI IO protocol instance.\r | |
356 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
357 | header to use as the base address for the memory\r | |
358 | operation to perform.\r | |
359 | @param[in] Offset The offset within the selected BAR to start the\r | |
360 | memory operation.\r | |
361 | @param[in] Count The width of the mmio register in bytes.\r | |
362 | Must be 1, 2, 4 or 8 bytes.\r | |
363 | @param[in] MaskValue The mask value of memory.\r | |
364 | @param[in] TestValue The test value of memory.\r | |
365 | @param[in] Timeout The time out value for wait memory set, uses 1\r | |
366 | microsecond as a unit.\r | |
367 | \r | |
368 | @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r | |
369 | range.\r | |
370 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
371 | @retval Others The MMIO operation fails.\r | |
372 | \r | |
373 | **/\r | |
374 | EFI_STATUS\r | |
375 | EFIAPI\r | |
376 | SdMmcHcWaitMmioSet (\r | |
377 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
378 | IN UINT8 BarIndex,\r | |
379 | IN UINT32 Offset,\r | |
380 | IN UINT8 Count,\r | |
381 | IN UINT64 MaskValue,\r | |
382 | IN UINT64 TestValue,\r | |
383 | IN UINT64 Timeout\r | |
384 | )\r | |
385 | {\r | |
386 | EFI_STATUS Status;\r | |
387 | BOOLEAN InfiniteWait;\r | |
388 | \r | |
389 | if (Timeout == 0) {\r | |
390 | InfiniteWait = TRUE;\r | |
391 | } else {\r | |
392 | InfiniteWait = FALSE;\r | |
393 | }\r | |
394 | \r | |
395 | while (InfiniteWait || (Timeout > 0)) {\r | |
396 | Status = SdMmcHcCheckMmioSet (\r | |
397 | PciIo,\r | |
398 | BarIndex,\r | |
399 | Offset,\r | |
400 | Count,\r | |
401 | MaskValue,\r | |
402 | TestValue\r | |
403 | );\r | |
404 | if (Status != EFI_NOT_READY) {\r | |
405 | return Status;\r | |
406 | }\r | |
407 | \r | |
408 | //\r | |
409 | // Stall for 1 microsecond.\r | |
410 | //\r | |
411 | gBS->Stall (1);\r | |
412 | \r | |
413 | Timeout--;\r | |
414 | }\r | |
415 | \r | |
416 | return EFI_TIMEOUT;\r | |
417 | }\r | |
418 | \r | |
419 | /**\r | |
420 | Software reset the specified SD/MMC host controller and enable all interrupts.\r | |
421 | \r | |
b23fc39c | 422 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 FT |
423 | @param[in] Slot The slot number of the SD card to send the command to.\r |
424 | \r | |
425 | @retval EFI_SUCCESS The software reset executes successfully.\r | |
426 | @retval Others The software reset fails.\r | |
427 | \r | |
428 | **/\r | |
429 | EFI_STATUS\r | |
430 | SdMmcHcReset (\r | |
b23fc39c | 431 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
48555339 FT |
432 | IN UINT8 Slot\r |
433 | )\r | |
434 | {\r | |
435 | EFI_STATUS Status;\r | |
436 | UINT8 SwReset;\r | |
b23fc39c | 437 | EFI_PCI_IO_PROTOCOL *PciIo;\r |
48555339 | 438 | \r |
b23fc39c AB |
439 | //\r |
440 | // Notify the SD/MMC override protocol that we are about to reset\r | |
441 | // the SD/MMC host controller.\r | |
442 | //\r | |
443 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
444 | Status = mOverride->NotifyPhase (\r | |
445 | Private->ControllerHandle,\r | |
446 | Slot,\r | |
49c99534 MW |
447 | EdkiiSdMmcResetPre,\r |
448 | NULL);\r | |
b23fc39c AB |
449 | if (EFI_ERROR (Status)) {\r |
450 | DEBUG ((DEBUG_WARN,\r | |
451 | "%a: SD/MMC pre reset notifier callback failed - %r\n",\r | |
452 | __FUNCTION__, Status));\r | |
453 | return Status;\r | |
454 | }\r | |
455 | }\r | |
456 | \r | |
457 | PciIo = Private->PciIo;\r | |
064d301f TM |
458 | SwReset = BIT0;\r |
459 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);\r | |
48555339 FT |
460 | \r |
461 | if (EFI_ERROR (Status)) {\r | |
064d301f | 462 | DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));\r |
48555339 FT |
463 | return Status;\r |
464 | }\r | |
465 | \r | |
466 | Status = SdMmcHcWaitMmioSet (\r | |
467 | PciIo,\r | |
468 | Slot,\r | |
469 | SD_MMC_HC_SW_RST,\r | |
470 | sizeof (SwReset),\r | |
064d301f | 471 | BIT0,\r |
48555339 FT |
472 | 0x00,\r |
473 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
474 | );\r | |
475 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 476 | DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r |
48555339 FT |
477 | return Status;\r |
478 | }\r | |
b23fc39c | 479 | \r |
48555339 FT |
480 | //\r |
481 | // Enable all interrupt after reset all.\r | |
482 | //\r | |
483 | Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r | |
b23fc39c AB |
484 | if (EFI_ERROR (Status)) {\r |
485 | DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",\r | |
486 | Status));\r | |
487 | return Status;\r | |
488 | }\r | |
489 | \r | |
490 | //\r | |
491 | // Notify the SD/MMC override protocol that we have just reset\r | |
492 | // the SD/MMC host controller.\r | |
493 | //\r | |
494 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
495 | Status = mOverride->NotifyPhase (\r | |
496 | Private->ControllerHandle,\r | |
497 | Slot,\r | |
49c99534 MW |
498 | EdkiiSdMmcResetPost,\r |
499 | NULL);\r | |
b23fc39c AB |
500 | if (EFI_ERROR (Status)) {\r |
501 | DEBUG ((DEBUG_WARN,\r | |
502 | "%a: SD/MMC post reset notifier callback failed - %r\n",\r | |
503 | __FUNCTION__, Status));\r | |
504 | }\r | |
505 | }\r | |
48555339 FT |
506 | \r |
507 | return Status;\r | |
508 | }\r | |
509 | \r | |
510 | /**\r | |
511 | Set all interrupt status bits in Normal and Error Interrupt Status Enable\r | |
512 | register.\r | |
513 | \r | |
514 | @param[in] PciIo The PCI IO protocol instance.\r | |
515 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
516 | \r | |
517 | @retval EFI_SUCCESS The operation executes successfully.\r | |
518 | @retval Others The operation fails.\r | |
519 | \r | |
520 | **/\r | |
521 | EFI_STATUS\r | |
522 | SdMmcHcEnableInterrupt (\r | |
523 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
524 | IN UINT8 Slot\r | |
525 | )\r | |
526 | {\r | |
527 | EFI_STATUS Status;\r | |
528 | UINT16 IntStatus;\r | |
529 | \r | |
530 | //\r | |
531 | // Enable all bits in Error Interrupt Status Enable Register\r | |
532 | //\r | |
533 | IntStatus = 0xFFFF;\r | |
534 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
535 | if (EFI_ERROR (Status)) {\r | |
536 | return Status;\r | |
537 | }\r | |
538 | //\r | |
539 | // Enable all bits in Normal Interrupt Status Enable Register\r | |
540 | //\r | |
541 | IntStatus = 0xFFFF;\r | |
542 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
543 | \r | |
544 | return Status;\r | |
545 | }\r | |
546 | \r | |
547 | /**\r | |
548 | Get the capability data from the specified slot.\r | |
549 | \r | |
550 | @param[in] PciIo The PCI IO protocol instance.\r | |
551 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
552 | @param[out] Capability The buffer to store the capability data.\r | |
553 | \r | |
554 | @retval EFI_SUCCESS The operation executes successfully.\r | |
555 | @retval Others The operation fails.\r | |
556 | \r | |
557 | **/\r | |
558 | EFI_STATUS\r | |
559 | SdMmcHcGetCapability (\r | |
560 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
561 | IN UINT8 Slot,\r | |
562 | OUT SD_MMC_HC_SLOT_CAP *Capability\r | |
563 | )\r | |
564 | {\r | |
565 | EFI_STATUS Status;\r | |
566 | UINT64 Cap;\r | |
567 | \r | |
568 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r | |
569 | if (EFI_ERROR (Status)) {\r | |
570 | return Status;\r | |
571 | }\r | |
572 | \r | |
573 | CopyMem (Capability, &Cap, sizeof (Cap));\r | |
574 | \r | |
575 | return EFI_SUCCESS;\r | |
576 | }\r | |
577 | \r | |
578 | /**\r | |
579 | Get the maximum current capability data from the specified slot.\r | |
580 | \r | |
581 | @param[in] PciIo The PCI IO protocol instance.\r | |
582 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
583 | @param[out] MaxCurrent The buffer to store the maximum current capability data.\r | |
584 | \r | |
585 | @retval EFI_SUCCESS The operation executes successfully.\r | |
586 | @retval Others The operation fails.\r | |
587 | \r | |
588 | **/\r | |
589 | EFI_STATUS\r | |
590 | SdMmcHcGetMaxCurrent (\r | |
591 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
592 | IN UINT8 Slot,\r | |
593 | OUT UINT64 *MaxCurrent\r | |
594 | )\r | |
595 | {\r | |
596 | EFI_STATUS Status;\r | |
597 | \r | |
598 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);\r | |
599 | \r | |
600 | return Status;\r | |
601 | }\r | |
602 | \r | |
603 | /**\r | |
604 | Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r | |
605 | slot.\r | |
606 | \r | |
607 | Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r | |
608 | \r | |
609 | @param[in] PciIo The PCI IO protocol instance.\r | |
610 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
611 | @param[out] MediaPresent The pointer to the media present boolean value.\r | |
612 | \r | |
613 | @retval EFI_SUCCESS There is no media change happened.\r | |
614 | @retval EFI_MEDIA_CHANGED There is media change happened.\r | |
615 | @retval Others The detection fails.\r | |
616 | \r | |
617 | **/\r | |
618 | EFI_STATUS\r | |
619 | SdMmcHcCardDetect (\r | |
620 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
621 | IN UINT8 Slot,\r | |
622 | OUT BOOLEAN *MediaPresent\r | |
623 | )\r | |
624 | {\r | |
625 | EFI_STATUS Status;\r | |
626 | UINT16 Data;\r | |
627 | UINT32 PresentState;\r | |
628 | \r | |
2e9107b8 FT |
629 | //\r |
630 | // Check Present State Register to see if there is a card presented.\r | |
631 | //\r | |
632 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r | |
633 | if (EFI_ERROR (Status)) {\r | |
634 | return Status;\r | |
635 | }\r | |
636 | \r | |
637 | if ((PresentState & BIT16) != 0) {\r | |
638 | *MediaPresent = TRUE;\r | |
639 | } else {\r | |
640 | *MediaPresent = FALSE;\r | |
641 | }\r | |
642 | \r | |
48555339 FT |
643 | //\r |
644 | // Check Normal Interrupt Status Register\r | |
645 | //\r | |
646 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r | |
647 | if (EFI_ERROR (Status)) {\r | |
648 | return Status;\r | |
649 | }\r | |
650 | \r | |
651 | if ((Data & (BIT6 | BIT7)) != 0) {\r | |
652 | //\r | |
653 | // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r | |
654 | //\r | |
655 | Data &= BIT6 | BIT7;\r | |
656 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r | |
657 | if (EFI_ERROR (Status)) {\r | |
658 | return Status;\r | |
659 | }\r | |
660 | \r | |
48555339 FT |
661 | return EFI_MEDIA_CHANGED;\r |
662 | }\r | |
663 | \r | |
664 | return EFI_SUCCESS;\r | |
665 | }\r | |
666 | \r | |
667 | /**\r | |
668 | Stop SD/MMC card clock.\r | |
669 | \r | |
670 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r | |
671 | \r | |
672 | @param[in] PciIo The PCI IO protocol instance.\r | |
673 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
674 | \r | |
675 | @retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r | |
676 | @retval Others Fail to stop SD/MMC clock.\r | |
677 | \r | |
678 | **/\r | |
679 | EFI_STATUS\r | |
680 | SdMmcHcStopClock (\r | |
681 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
682 | IN UINT8 Slot\r | |
683 | )\r | |
684 | {\r | |
685 | EFI_STATUS Status;\r | |
686 | UINT32 PresentState;\r | |
687 | UINT16 ClockCtrl;\r | |
688 | \r | |
689 | //\r | |
690 | // Ensure no SD transactions are occurring on the SD Bus by\r | |
691 | // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r | |
692 | // in the Present State register to be 0.\r | |
693 | //\r | |
694 | Status = SdMmcHcWaitMmioSet (\r | |
695 | PciIo,\r | |
696 | Slot,\r | |
697 | SD_MMC_HC_PRESENT_STATE,\r | |
698 | sizeof (PresentState),\r | |
699 | BIT0 | BIT1,\r | |
700 | 0,\r | |
701 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
702 | );\r | |
703 | if (EFI_ERROR (Status)) {\r | |
704 | return Status;\r | |
705 | }\r | |
706 | \r | |
707 | //\r | |
708 | // Set SD Clock Enable in the Clock Control register to 0\r | |
709 | //\r | |
710 | ClockCtrl = (UINT16)~BIT2;\r | |
711 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
712 | \r | |
713 | return Status;\r | |
714 | }\r | |
715 | \r | |
716 | /**\r | |
717 | SD/MMC card clock supply.\r | |
718 | \r | |
719 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r | |
720 | \r | |
721 | @param[in] PciIo The PCI IO protocol instance.\r | |
722 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
723 | @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r | |
7f3b0bad | 724 | @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r |
48555339 FT |
725 | \r |
726 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
727 | @retval Others The clock isn't supplied successfully.\r | |
728 | \r | |
729 | **/\r | |
730 | EFI_STATUS\r | |
731 | SdMmcHcClockSupply (\r | |
732 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
733 | IN UINT8 Slot,\r | |
734 | IN UINT64 ClockFreq,\r | |
7f3b0bad | 735 | IN UINT32 BaseClkFreq\r |
48555339 FT |
736 | )\r |
737 | {\r | |
738 | EFI_STATUS Status;\r | |
48555339 FT |
739 | UINT32 SettingFreq;\r |
740 | UINT32 Divisor;\r | |
741 | UINT32 Remainder;\r | |
742 | UINT16 ControllerVer;\r | |
743 | UINT16 ClockCtrl;\r | |
744 | \r | |
745 | //\r | |
746 | // Calculate a divisor for SD clock frequency\r | |
747 | //\r | |
7f3b0bad | 748 | ASSERT (BaseClkFreq != 0);\r |
48555339 | 749 | \r |
cb9cb9e2 | 750 | if (ClockFreq == 0) {\r |
48555339 FT |
751 | return EFI_INVALID_PARAMETER;\r |
752 | }\r | |
cb9cb9e2 FT |
753 | \r |
754 | if (ClockFreq > (BaseClkFreq * 1000)) {\r | |
755 | ClockFreq = BaseClkFreq * 1000;\r | |
756 | }\r | |
757 | \r | |
48555339 FT |
758 | //\r |
759 | // Calculate the divisor of base frequency.\r | |
760 | //\r | |
761 | Divisor = 0;\r | |
762 | SettingFreq = BaseClkFreq * 1000;\r | |
763 | while (ClockFreq < SettingFreq) {\r | |
764 | Divisor++;\r | |
765 | \r | |
766 | SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r | |
767 | Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r | |
768 | if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r | |
769 | break;\r | |
770 | }\r | |
771 | if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r | |
772 | SettingFreq ++;\r | |
773 | }\r | |
774 | }\r | |
775 | \r | |
e27ccaba | 776 | DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r |
48555339 FT |
777 | \r |
778 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);\r | |
779 | if (EFI_ERROR (Status)) {\r | |
780 | return Status;\r | |
781 | }\r | |
782 | //\r | |
783 | // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r | |
784 | //\r | |
bbce0015 JB |
785 | if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&\r |
786 | ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {\r | |
48555339 FT |
787 | ASSERT (Divisor <= 0x3FF);\r |
788 | ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r | |
789 | } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r | |
790 | //\r | |
791 | // Only the most significant bit can be used as divisor.\r | |
792 | //\r | |
793 | if (((Divisor - 1) & Divisor) != 0) {\r | |
794 | Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r | |
795 | }\r | |
796 | ASSERT (Divisor <= 0x80);\r | |
797 | ClockCtrl = (Divisor & 0xFF) << 8;\r | |
798 | } else {\r | |
e27ccaba | 799 | DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r |
48555339 FT |
800 | return EFI_UNSUPPORTED;\r |
801 | }\r | |
802 | \r | |
803 | //\r | |
804 | // Stop bus clock at first\r | |
805 | //\r | |
806 | Status = SdMmcHcStopClock (PciIo, Slot);\r | |
807 | if (EFI_ERROR (Status)) {\r | |
808 | return Status;\r | |
809 | }\r | |
810 | \r | |
811 | //\r | |
812 | // Supply clock frequency with specified divisor\r | |
813 | //\r | |
814 | ClockCtrl |= BIT0;\r | |
815 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r | |
816 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 817 | DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r |
48555339 FT |
818 | return Status;\r |
819 | }\r | |
820 | \r | |
821 | //\r | |
822 | // Wait Internal Clock Stable in the Clock Control register to be 1\r | |
823 | //\r | |
824 | Status = SdMmcHcWaitMmioSet (\r | |
825 | PciIo,\r | |
826 | Slot,\r | |
827 | SD_MMC_HC_CLOCK_CTRL,\r | |
828 | sizeof (ClockCtrl),\r | |
829 | BIT1,\r | |
830 | BIT1,\r | |
831 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
832 | );\r | |
833 | if (EFI_ERROR (Status)) {\r | |
834 | return Status;\r | |
835 | }\r | |
836 | \r | |
837 | //\r | |
838 | // Set SD Clock Enable in the Clock Control register to 1\r | |
839 | //\r | |
840 | ClockCtrl = BIT2;\r | |
841 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
842 | \r | |
843 | return Status;\r | |
844 | }\r | |
845 | \r | |
846 | /**\r | |
847 | SD/MMC bus power control.\r | |
848 | \r | |
849 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
850 | \r | |
851 | @param[in] PciIo The PCI IO protocol instance.\r | |
852 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
853 | @param[in] PowerCtrl The value setting to the power control register.\r | |
854 | \r | |
855 | @retval TRUE There is a SD/MMC card attached.\r | |
856 | @retval FALSE There is no a SD/MMC card attached.\r | |
857 | \r | |
858 | **/\r | |
859 | EFI_STATUS\r | |
860 | SdMmcHcPowerControl (\r | |
861 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
862 | IN UINT8 Slot,\r | |
863 | IN UINT8 PowerCtrl\r | |
864 | )\r | |
865 | {\r | |
866 | EFI_STATUS Status;\r | |
867 | \r | |
868 | //\r | |
869 | // Clr SD Bus Power\r | |
870 | //\r | |
871 | PowerCtrl &= (UINT8)~BIT0;\r | |
872 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
873 | if (EFI_ERROR (Status)) {\r | |
874 | return Status;\r | |
875 | }\r | |
876 | \r | |
877 | //\r | |
878 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
879 | //\r | |
880 | PowerCtrl |= BIT0;\r | |
881 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
882 | \r | |
883 | return Status;\r | |
884 | }\r | |
885 | \r | |
886 | /**\r | |
887 | Set the SD/MMC bus width.\r | |
888 | \r | |
889 | Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r | |
890 | \r | |
891 | @param[in] PciIo The PCI IO protocol instance.\r | |
892 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
893 | @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r | |
894 | \r | |
895 | @retval EFI_SUCCESS The bus width is set successfully.\r | |
896 | @retval Others The bus width isn't set successfully.\r | |
897 | \r | |
898 | **/\r | |
899 | EFI_STATUS\r | |
900 | SdMmcHcSetBusWidth (\r | |
901 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
902 | IN UINT8 Slot,\r | |
903 | IN UINT16 BusWidth\r | |
904 | )\r | |
905 | {\r | |
906 | EFI_STATUS Status;\r | |
907 | UINT8 HostCtrl1;\r | |
908 | \r | |
909 | if (BusWidth == 1) {\r | |
910 | HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r | |
911 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
912 | } else if (BusWidth == 4) {\r | |
913 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
914 | if (EFI_ERROR (Status)) {\r | |
915 | return Status;\r | |
916 | }\r | |
917 | HostCtrl1 |= BIT1;\r | |
918 | HostCtrl1 &= (UINT8)~BIT5;\r | |
919 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
920 | } else if (BusWidth == 8) {\r | |
921 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
922 | if (EFI_ERROR (Status)) {\r | |
923 | return Status;\r | |
924 | }\r | |
925 | HostCtrl1 &= (UINT8)~BIT1;\r | |
926 | HostCtrl1 |= BIT5;\r | |
927 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
928 | } else {\r | |
929 | ASSERT (FALSE);\r | |
930 | return EFI_INVALID_PARAMETER;\r | |
931 | }\r | |
932 | \r | |
933 | return Status;\r | |
934 | }\r | |
935 | \r | |
936 | /**\r | |
937 | Supply SD/MMC card with lowest clock frequency at initialization.\r | |
938 | \r | |
939 | @param[in] PciIo The PCI IO protocol instance.\r | |
940 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
7f3b0bad | 941 | @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r |
48555339 FT |
942 | \r |
943 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
944 | @retval Others The clock isn't supplied successfully.\r | |
945 | \r | |
946 | **/\r | |
947 | EFI_STATUS\r | |
948 | SdMmcHcInitClockFreq (\r | |
949 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
950 | IN UINT8 Slot,\r | |
7f3b0bad | 951 | IN UINT32 BaseClkFreq\r |
48555339 FT |
952 | )\r |
953 | {\r | |
954 | EFI_STATUS Status;\r | |
955 | UINT32 InitFreq;\r | |
956 | \r | |
957 | //\r | |
7f3b0bad MW |
958 | // According to SDHCI specification ver. 4.2, BaseClkFreq field value of\r |
959 | // the Capability Register 1 can be zero, which means a need for obtaining\r | |
960 | // the clock frequency via another method. Fail in case it is not updated\r | |
961 | // by SW at this point.\r | |
48555339 | 962 | //\r |
7f3b0bad | 963 | if (BaseClkFreq == 0) {\r |
48555339 FT |
964 | //\r |
965 | // Don't support get Base Clock Frequency information via another method\r | |
966 | //\r | |
967 | return EFI_UNSUPPORTED;\r | |
968 | }\r | |
969 | //\r | |
970 | // Supply 400KHz clock frequency at initialization phase.\r | |
971 | //\r | |
972 | InitFreq = 400;\r | |
7f3b0bad | 973 | Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);\r |
48555339 FT |
974 | return Status;\r |
975 | }\r | |
976 | \r | |
977 | /**\r | |
978 | Supply SD/MMC card with maximum voltage at initialization.\r | |
979 | \r | |
980 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
981 | \r | |
982 | @param[in] PciIo The PCI IO protocol instance.\r | |
983 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
984 | @param[in] Capability The capability of the slot.\r | |
985 | \r | |
986 | @retval EFI_SUCCESS The voltage is supplied successfully.\r | |
987 | @retval Others The voltage isn't supplied successfully.\r | |
988 | \r | |
989 | **/\r | |
990 | EFI_STATUS\r | |
991 | SdMmcHcInitPowerVoltage (\r | |
992 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
993 | IN UINT8 Slot,\r | |
994 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
995 | )\r | |
996 | {\r | |
997 | EFI_STATUS Status;\r | |
998 | UINT8 MaxVoltage;\r | |
999 | UINT8 HostCtrl2;\r | |
1000 | \r | |
1001 | //\r | |
1002 | // Calculate supported maximum voltage according to SD Bus Voltage Select\r | |
1003 | //\r | |
1004 | if (Capability.Voltage33 != 0) {\r | |
1005 | //\r | |
1006 | // Support 3.3V\r | |
1007 | //\r | |
1008 | MaxVoltage = 0x0E;\r | |
1009 | } else if (Capability.Voltage30 != 0) {\r | |
1010 | //\r | |
1011 | // Support 3.0V\r | |
1012 | //\r | |
1013 | MaxVoltage = 0x0C;\r | |
1014 | } else if (Capability.Voltage18 != 0) {\r | |
1015 | //\r | |
1016 | // Support 1.8V\r | |
1017 | //\r | |
1018 | MaxVoltage = 0x0A;\r | |
1019 | HostCtrl2 = BIT3;\r | |
1020 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1021 | gBS->Stall (5000);\r | |
1022 | if (EFI_ERROR (Status)) {\r | |
1023 | return Status;\r | |
1024 | }\r | |
1025 | } else {\r | |
1026 | ASSERT (FALSE);\r | |
1027 | return EFI_DEVICE_ERROR;\r | |
1028 | }\r | |
1029 | \r | |
1030 | //\r | |
1031 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
1032 | //\r | |
1033 | Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);\r | |
1034 | \r | |
1035 | return Status;\r | |
1036 | }\r | |
1037 | \r | |
1038 | /**\r | |
1039 | Initialize the Timeout Control register with most conservative value at initialization.\r | |
1040 | \r | |
1041 | Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r | |
1042 | \r | |
1043 | @param[in] PciIo The PCI IO protocol instance.\r | |
1044 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1045 | \r | |
1046 | @retval EFI_SUCCESS The timeout control register is configured successfully.\r | |
1047 | @retval Others The timeout control register isn't configured successfully.\r | |
1048 | \r | |
1049 | **/\r | |
1050 | EFI_STATUS\r | |
1051 | SdMmcHcInitTimeoutCtrl (\r | |
1052 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1053 | IN UINT8 Slot\r | |
1054 | )\r | |
1055 | {\r | |
1056 | EFI_STATUS Status;\r | |
1057 | UINT8 Timeout;\r | |
1058 | \r | |
1059 | Timeout = 0x0E;\r | |
1060 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r | |
1061 | \r | |
1062 | return Status;\r | |
1063 | }\r | |
1064 | \r | |
1065 | /**\r | |
1066 | Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r | |
1067 | at initialization.\r | |
1068 | \r | |
b23fc39c | 1069 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 | 1070 | @param[in] Slot The slot number of the SD card to send the command to.\r |
48555339 FT |
1071 | \r |
1072 | @retval EFI_SUCCESS The host controller is initialized successfully.\r | |
1073 | @retval Others The host controller isn't initialized successfully.\r | |
1074 | \r | |
1075 | **/\r | |
1076 | EFI_STATUS\r | |
1077 | SdMmcHcInitHost (\r | |
b23fc39c AB |
1078 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
1079 | IN UINT8 Slot\r | |
48555339 FT |
1080 | )\r |
1081 | {\r | |
b23fc39c AB |
1082 | EFI_STATUS Status;\r |
1083 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1084 | SD_MMC_HC_SLOT_CAP Capability;\r | |
1085 | \r | |
1086 | //\r | |
1087 | // Notify the SD/MMC override protocol that we are about to initialize\r | |
1088 | // the SD/MMC host controller.\r | |
1089 | //\r | |
1090 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1091 | Status = mOverride->NotifyPhase (\r | |
1092 | Private->ControllerHandle,\r | |
1093 | Slot,\r | |
49c99534 MW |
1094 | EdkiiSdMmcInitHostPre,\r |
1095 | NULL);\r | |
b23fc39c AB |
1096 | if (EFI_ERROR (Status)) {\r |
1097 | DEBUG ((DEBUG_WARN,\r | |
1098 | "%a: SD/MMC pre init notifier callback failed - %r\n",\r | |
1099 | __FUNCTION__, Status));\r | |
1100 | return Status;\r | |
1101 | }\r | |
1102 | }\r | |
1103 | \r | |
1104 | PciIo = Private->PciIo;\r | |
1105 | Capability = Private->Capability[Slot];\r | |
48555339 | 1106 | \r |
7f3b0bad | 1107 | Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);\r |
48555339 FT |
1108 | if (EFI_ERROR (Status)) {\r |
1109 | return Status;\r | |
1110 | }\r | |
1111 | \r | |
1112 | Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);\r | |
1113 | if (EFI_ERROR (Status)) {\r | |
1114 | return Status;\r | |
1115 | }\r | |
1116 | \r | |
1117 | Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r | |
b23fc39c AB |
1118 | if (EFI_ERROR (Status)) {\r |
1119 | return Status;\r | |
1120 | }\r | |
1121 | \r | |
1122 | //\r | |
1123 | // Notify the SD/MMC override protocol that we are have just initialized\r | |
1124 | // the SD/MMC host controller.\r | |
1125 | //\r | |
1126 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1127 | Status = mOverride->NotifyPhase (\r | |
1128 | Private->ControllerHandle,\r | |
1129 | Slot,\r | |
49c99534 MW |
1130 | EdkiiSdMmcInitHostPost,\r |
1131 | NULL);\r | |
b23fc39c AB |
1132 | if (EFI_ERROR (Status)) {\r |
1133 | DEBUG ((DEBUG_WARN,\r | |
1134 | "%a: SD/MMC post init notifier callback failed - %r\n",\r | |
1135 | __FUNCTION__, Status));\r | |
1136 | }\r | |
1137 | }\r | |
48555339 FT |
1138 | return Status;\r |
1139 | }\r | |
1140 | \r | |
a4708009 TM |
1141 | /**\r |
1142 | Set SD Host Controler control 2 registry according to selected speed.\r | |
1143 | \r | |
1144 | @param[in] ControllerHandle The handle of the controller.\r | |
1145 | @param[in] PciIo The PCI IO protocol instance.\r | |
1146 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1147 | @param[in] Timing The timing to select.\r | |
1148 | \r | |
1149 | @retval EFI_SUCCESS The timing is set successfully.\r | |
1150 | @retval Others The timing isn't set successfully.\r | |
1151 | **/\r | |
1152 | EFI_STATUS\r | |
1153 | SdMmcHcUhsSignaling (\r | |
1154 | IN EFI_HANDLE ControllerHandle,\r | |
1155 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1156 | IN UINT8 Slot,\r | |
1157 | IN SD_MMC_BUS_MODE Timing\r | |
1158 | )\r | |
1159 | {\r | |
1160 | EFI_STATUS Status;\r | |
1161 | UINT8 HostCtrl2;\r | |
1162 | \r | |
1163 | HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;\r | |
1164 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1165 | if (EFI_ERROR (Status)) {\r | |
1166 | return Status;\r | |
1167 | }\r | |
1168 | \r | |
1169 | switch (Timing) {\r | |
1170 | case SdMmcUhsSdr12:\r | |
1171 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;\r | |
1172 | break;\r | |
1173 | case SdMmcUhsSdr25:\r | |
1174 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;\r | |
1175 | break;\r | |
1176 | case SdMmcUhsSdr50:\r | |
1177 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;\r | |
1178 | break;\r | |
1179 | case SdMmcUhsSdr104:\r | |
1180 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;\r | |
1181 | break;\r | |
1182 | case SdMmcUhsDdr50:\r | |
1183 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;\r | |
1184 | break;\r | |
1185 | case SdMmcMmcLegacy:\r | |
1186 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;\r | |
1187 | break;\r | |
1188 | case SdMmcMmcHsSdr:\r | |
1189 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;\r | |
1190 | break;\r | |
1191 | case SdMmcMmcHsDdr:\r | |
1192 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;\r | |
1193 | break;\r | |
1194 | case SdMmcMmcHs200:\r | |
1195 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;\r | |
1196 | break;\r | |
1197 | case SdMmcMmcHs400:\r | |
1198 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;\r | |
1199 | break;\r | |
1200 | default:\r | |
1201 | HostCtrl2 = 0;\r | |
1202 | break;\r | |
1203 | }\r | |
1204 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1205 | if (EFI_ERROR (Status)) {\r | |
1206 | return Status;\r | |
1207 | }\r | |
1208 | \r | |
1209 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1210 | Status = mOverride->NotifyPhase (\r | |
1211 | ControllerHandle,\r | |
1212 | Slot,\r | |
1213 | EdkiiSdMmcUhsSignaling,\r | |
1214 | &Timing\r | |
1215 | );\r | |
1216 | if (EFI_ERROR (Status)) {\r | |
1217 | DEBUG ((\r | |
1218 | DEBUG_ERROR,\r | |
1219 | "%a: SD/MMC uhs signaling notifier callback failed - %r\n",\r | |
1220 | __FUNCTION__,\r | |
1221 | Status\r | |
1222 | ));\r | |
1223 | return Status;\r | |
1224 | }\r | |
1225 | }\r | |
1226 | \r | |
1227 | return EFI_SUCCESS;\r | |
1228 | }\r | |
1229 | \r | |
48555339 FT |
1230 | /**\r |
1231 | Turn on/off LED.\r | |
1232 | \r | |
1233 | @param[in] PciIo The PCI IO protocol instance.\r | |
1234 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1235 | @param[in] On The boolean to turn on/off LED.\r | |
1236 | \r | |
1237 | @retval EFI_SUCCESS The LED is turned on/off successfully.\r | |
1238 | @retval Others The LED isn't turned on/off successfully.\r | |
1239 | \r | |
1240 | **/\r | |
1241 | EFI_STATUS\r | |
1242 | SdMmcHcLedOnOff (\r | |
1243 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1244 | IN UINT8 Slot,\r | |
1245 | IN BOOLEAN On\r | |
1246 | )\r | |
1247 | {\r | |
1248 | EFI_STATUS Status;\r | |
1249 | UINT8 HostCtrl1;\r | |
1250 | \r | |
1251 | if (On) {\r | |
1252 | HostCtrl1 = BIT0;\r | |
1253 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1254 | } else {\r | |
1255 | HostCtrl1 = (UINT8)~BIT0;\r | |
1256 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1257 | }\r | |
1258 | \r | |
1259 | return Status;\r | |
1260 | }\r | |
1261 | \r | |
1262 | /**\r | |
1263 | Build ADMA descriptor table for transfer.\r | |
1264 | \r | |
1265 | Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.\r | |
1266 | \r | |
1267 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1268 | \r | |
1269 | @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r | |
1270 | @retval Others The ADMA descriptor table isn't created successfully.\r | |
1271 | \r | |
1272 | **/\r | |
1273 | EFI_STATUS\r | |
1274 | BuildAdmaDescTable (\r | |
1275 | IN SD_MMC_HC_TRB *Trb\r | |
1276 | )\r | |
1277 | {\r | |
1278 | EFI_PHYSICAL_ADDRESS Data;\r | |
1279 | UINT64 DataLen;\r | |
1280 | UINT64 Entries;\r | |
1281 | UINT32 Index;\r | |
1282 | UINT64 Remaining;\r | |
1283 | UINT32 Address;\r | |
1284 | UINTN TableSize;\r | |
1285 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1286 | EFI_STATUS Status;\r | |
1287 | UINTN Bytes;\r | |
1288 | \r | |
1289 | Data = Trb->DataPhy;\r | |
1290 | DataLen = Trb->DataLen;\r | |
1291 | PciIo = Trb->Private->PciIo;\r | |
1292 | //\r | |
1293 | // Only support 32bit ADMA Descriptor Table\r | |
1294 | //\r | |
1295 | if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {\r | |
1296 | return EFI_INVALID_PARAMETER;\r | |
1297 | }\r | |
1298 | //\r | |
1299 | // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r | |
1300 | // for 32-bit address descriptor table.\r | |
1301 | //\r | |
1302 | if ((Data & (BIT0 | BIT1)) != 0) {\r | |
e27ccaba | 1303 | DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r |
48555339 FT |
1304 | }\r |
1305 | \r | |
1306 | Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);\r | |
1307 | TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));\r | |
1308 | Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r | |
1309 | Status = PciIo->AllocateBuffer (\r | |
1310 | PciIo,\r | |
1311 | AllocateAnyPages,\r | |
1312 | EfiBootServicesData,\r | |
1313 | EFI_SIZE_TO_PAGES (TableSize),\r | |
1314 | (VOID **)&Trb->AdmaDesc,\r | |
1315 | 0\r | |
1316 | );\r | |
1317 | if (EFI_ERROR (Status)) {\r | |
1318 | return EFI_OUT_OF_RESOURCES;\r | |
1319 | }\r | |
1320 | ZeroMem (Trb->AdmaDesc, TableSize);\r | |
1321 | Bytes = TableSize;\r | |
1322 | Status = PciIo->Map (\r | |
1323 | PciIo,\r | |
1324 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
1325 | Trb->AdmaDesc,\r | |
1326 | &Bytes,\r | |
1327 | &Trb->AdmaDescPhy,\r | |
1328 | &Trb->AdmaMap\r | |
1329 | );\r | |
1330 | \r | |
1331 | if (EFI_ERROR (Status) || (Bytes != TableSize)) {\r | |
1332 | //\r | |
1333 | // Map error or unable to map the whole RFis buffer into a contiguous region.\r | |
1334 | //\r | |
1335 | PciIo->FreeBuffer (\r | |
1336 | PciIo,\r | |
1337 | EFI_SIZE_TO_PAGES (TableSize),\r | |
1338 | Trb->AdmaDesc\r | |
1339 | );\r | |
1340 | return EFI_OUT_OF_RESOURCES;\r | |
1341 | }\r | |
1342 | \r | |
1343 | if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r | |
1344 | //\r | |
1345 | // The ADMA doesn't support 64bit addressing.\r | |
1346 | //\r | |
1347 | PciIo->Unmap (\r | |
1348 | PciIo,\r | |
1349 | Trb->AdmaMap\r | |
1350 | );\r | |
1351 | PciIo->FreeBuffer (\r | |
1352 | PciIo,\r | |
1353 | EFI_SIZE_TO_PAGES (TableSize),\r | |
1354 | Trb->AdmaDesc\r | |
1355 | );\r | |
1356 | return EFI_DEVICE_ERROR;\r | |
1357 | }\r | |
1358 | \r | |
1359 | Remaining = DataLen;\r | |
1360 | Address = (UINT32)Data;\r | |
1361 | for (Index = 0; Index < Entries; Index++) {\r | |
1362 | if (Remaining <= ADMA_MAX_DATA_PER_LINE) {\r | |
1363 | Trb->AdmaDesc[Index].Valid = 1;\r | |
1364 | Trb->AdmaDesc[Index].Act = 2;\r | |
1365 | Trb->AdmaDesc[Index].Length = (UINT16)Remaining;\r | |
1366 | Trb->AdmaDesc[Index].Address = Address;\r | |
1367 | break;\r | |
1368 | } else {\r | |
1369 | Trb->AdmaDesc[Index].Valid = 1;\r | |
1370 | Trb->AdmaDesc[Index].Act = 2;\r | |
1371 | Trb->AdmaDesc[Index].Length = 0;\r | |
1372 | Trb->AdmaDesc[Index].Address = Address;\r | |
1373 | }\r | |
1374 | \r | |
1375 | Remaining -= ADMA_MAX_DATA_PER_LINE;\r | |
1376 | Address += ADMA_MAX_DATA_PER_LINE;\r | |
1377 | }\r | |
1378 | \r | |
1379 | //\r | |
1380 | // Set the last descriptor line as end of descriptor table\r | |
1381 | //\r | |
1382 | Trb->AdmaDesc[Index].End = 1;\r | |
1383 | return EFI_SUCCESS;\r | |
1384 | }\r | |
1385 | \r | |
1386 | /**\r | |
1387 | Create a new TRB for the SD/MMC cmd request.\r | |
1388 | \r | |
1389 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1390 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1391 | @param[in] Packet A pointer to the SD command data structure.\r | |
1392 | @param[in] Event If Event is NULL, blocking I/O is performed. If Event is\r | |
1393 | not NULL, then nonblocking I/O is performed, and Event\r | |
1394 | will be signaled when the Packet completes.\r | |
1395 | \r | |
1396 | @return Created Trb or NULL.\r | |
1397 | \r | |
1398 | **/\r | |
1399 | SD_MMC_HC_TRB *\r | |
1400 | SdMmcCreateTrb (\r | |
1401 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1402 | IN UINT8 Slot,\r | |
1403 | IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r | |
1404 | IN EFI_EVENT Event\r | |
1405 | )\r | |
1406 | {\r | |
1407 | SD_MMC_HC_TRB *Trb;\r | |
1408 | EFI_STATUS Status;\r | |
1409 | EFI_TPL OldTpl;\r | |
1410 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r | |
1411 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1412 | UINTN MapLength;\r | |
1413 | \r | |
1414 | Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));\r | |
1415 | if (Trb == NULL) {\r | |
1416 | return NULL;\r | |
1417 | }\r | |
1418 | \r | |
1419 | Trb->Signature = SD_MMC_HC_TRB_SIG;\r | |
1420 | Trb->Slot = Slot;\r | |
1421 | Trb->BlockSize = 0x200;\r | |
1422 | Trb->Packet = Packet;\r | |
1423 | Trb->Event = Event;\r | |
1424 | Trb->Started = FALSE;\r | |
1425 | Trb->Timeout = Packet->Timeout;\r | |
1426 | Trb->Private = Private;\r | |
1427 | \r | |
1428 | if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r | |
1429 | Trb->Data = Packet->InDataBuffer;\r | |
1430 | Trb->DataLen = Packet->InTransferLength;\r | |
1431 | Trb->Read = TRUE;\r | |
1432 | } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r | |
1433 | Trb->Data = Packet->OutDataBuffer;\r | |
1434 | Trb->DataLen = Packet->OutTransferLength;\r | |
1435 | Trb->Read = FALSE;\r | |
1436 | } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r | |
1437 | Trb->Data = NULL;\r | |
1438 | Trb->DataLen = 0;\r | |
1439 | } else {\r | |
1440 | goto Error;\r | |
1441 | }\r | |
1442 | \r | |
54228046 | 1443 | if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r |
e7e89b08 FT |
1444 | Trb->BlockSize = (UINT16)Trb->DataLen;\r |
1445 | }\r | |
1446 | \r | |
1447 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
1448 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
1449 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
1450 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
1451 | Trb->Mode = SdMmcPioMode;\r | |
48555339 | 1452 | } else {\r |
e7e89b08 FT |
1453 | if (Trb->Read) {\r |
1454 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
1455 | } else {\r | |
1456 | Flag = EfiPciIoOperationBusMasterRead;\r | |
48555339 | 1457 | }\r |
48555339 | 1458 | \r |
e7e89b08 FT |
1459 | PciIo = Private->PciIo;\r |
1460 | if (Trb->DataLen != 0) {\r | |
1461 | MapLength = Trb->DataLen;\r | |
1462 | Status = PciIo->Map (\r | |
1463 | PciIo,\r | |
1464 | Flag,\r | |
1465 | Trb->Data,\r | |
1466 | &MapLength,\r | |
1467 | &Trb->DataPhy,\r | |
1468 | &Trb->DataMap\r | |
1469 | );\r | |
1470 | if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {\r | |
1471 | Status = EFI_BAD_BUFFER_SIZE;\r | |
1472 | goto Error;\r | |
1473 | }\r | |
48555339 | 1474 | }\r |
48555339 | 1475 | \r |
e7e89b08 FT |
1476 | if (Trb->DataLen == 0) {\r |
1477 | Trb->Mode = SdMmcNoData;\r | |
1478 | } else if (Private->Capability[Slot].Adma2 != 0) {\r | |
1479 | Trb->Mode = SdMmcAdmaMode;\r | |
1480 | Status = BuildAdmaDescTable (Trb);\r | |
1481 | if (EFI_ERROR (Status)) {\r | |
1482 | PciIo->Unmap (PciIo, Trb->DataMap);\r | |
1483 | goto Error;\r | |
1484 | }\r | |
1485 | } else if (Private->Capability[Slot].Sdma != 0) {\r | |
1486 | Trb->Mode = SdMmcSdmaMode;\r | |
1487 | } else {\r | |
1488 | Trb->Mode = SdMmcPioMode;\r | |
48555339 | 1489 | }\r |
48555339 FT |
1490 | }\r |
1491 | \r | |
1492 | if (Event != NULL) {\r | |
3b1d8241 | 1493 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r |
48555339 FT |
1494 | InsertTailList (&Private->Queue, &Trb->TrbList);\r |
1495 | gBS->RestoreTPL (OldTpl);\r | |
1496 | }\r | |
1497 | \r | |
1498 | return Trb;\r | |
1499 | \r | |
1500 | Error:\r | |
1501 | SdMmcFreeTrb (Trb);\r | |
1502 | return NULL;\r | |
1503 | }\r | |
1504 | \r | |
1505 | /**\r | |
1506 | Free the resource used by the TRB.\r | |
1507 | \r | |
1508 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1509 | \r | |
1510 | **/\r | |
1511 | VOID\r | |
1512 | SdMmcFreeTrb (\r | |
1513 | IN SD_MMC_HC_TRB *Trb\r | |
1514 | )\r | |
1515 | {\r | |
1516 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1517 | \r | |
1518 | PciIo = Trb->Private->PciIo;\r | |
1519 | \r | |
1520 | if (Trb->AdmaMap != NULL) {\r | |
1521 | PciIo->Unmap (\r | |
1522 | PciIo,\r | |
1523 | Trb->AdmaMap\r | |
1524 | );\r | |
1525 | }\r | |
1526 | if (Trb->AdmaDesc != NULL) {\r | |
1527 | PciIo->FreeBuffer (\r | |
1528 | PciIo,\r | |
1529 | Trb->AdmaPages,\r | |
1530 | Trb->AdmaDesc\r | |
1531 | );\r | |
1532 | }\r | |
1533 | if (Trb->DataMap != NULL) {\r | |
1534 | PciIo->Unmap (\r | |
1535 | PciIo,\r | |
1536 | Trb->DataMap\r | |
1537 | );\r | |
1538 | }\r | |
1539 | FreePool (Trb);\r | |
1540 | return;\r | |
1541 | }\r | |
1542 | \r | |
1543 | /**\r | |
1544 | Check if the env is ready for execute specified TRB.\r | |
1545 | \r | |
1546 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1547 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1548 | \r | |
1549 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
1550 | @retval EFI_NOT_READY The env is not ready for TRB execution.\r | |
1551 | @retval Others Some erros happen.\r | |
1552 | \r | |
1553 | **/\r | |
1554 | EFI_STATUS\r | |
1555 | SdMmcCheckTrbEnv (\r | |
1556 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1557 | IN SD_MMC_HC_TRB *Trb\r | |
1558 | )\r | |
1559 | {\r | |
1560 | EFI_STATUS Status;\r | |
1561 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1562 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1563 | UINT32 PresentState;\r | |
1564 | \r | |
1565 | Packet = Trb->Packet;\r | |
1566 | \r | |
1567 | if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r | |
1568 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r | |
1569 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {\r | |
1570 | //\r | |
1571 | // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r | |
1572 | // the Present State register to be 0\r | |
1573 | //\r | |
1574 | PresentState = BIT0 | BIT1;\r | |
48555339 FT |
1575 | } else {\r |
1576 | //\r | |
1577 | // Wait Command Inhibit (CMD) in the Present State register\r | |
1578 | // to be 0\r | |
1579 | //\r | |
1580 | PresentState = BIT0;\r | |
1581 | }\r | |
1582 | \r | |
1583 | PciIo = Private->PciIo;\r | |
1584 | Status = SdMmcHcCheckMmioSet (\r | |
1585 | PciIo,\r | |
1586 | Trb->Slot,\r | |
1587 | SD_MMC_HC_PRESENT_STATE,\r | |
1588 | sizeof (PresentState),\r | |
1589 | PresentState,\r | |
1590 | 0\r | |
1591 | );\r | |
1592 | \r | |
1593 | return Status;\r | |
1594 | }\r | |
1595 | \r | |
1596 | /**\r | |
1597 | Wait for the env to be ready for execute specified TRB.\r | |
1598 | \r | |
1599 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1600 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1601 | \r | |
1602 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
1603 | @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r | |
1604 | @retval Others Some erros happen.\r | |
1605 | \r | |
1606 | **/\r | |
1607 | EFI_STATUS\r | |
1608 | SdMmcWaitTrbEnv (\r | |
1609 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1610 | IN SD_MMC_HC_TRB *Trb\r | |
1611 | )\r | |
1612 | {\r | |
1613 | EFI_STATUS Status;\r | |
1614 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1615 | UINT64 Timeout;\r | |
1616 | BOOLEAN InfiniteWait;\r | |
1617 | \r | |
1618 | //\r | |
1619 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
1620 | //\r | |
1621 | Packet = Trb->Packet;\r | |
1622 | Timeout = Packet->Timeout;\r | |
1623 | if (Timeout == 0) {\r | |
1624 | InfiniteWait = TRUE;\r | |
1625 | } else {\r | |
1626 | InfiniteWait = FALSE;\r | |
1627 | }\r | |
1628 | \r | |
1629 | while (InfiniteWait || (Timeout > 0)) {\r | |
1630 | //\r | |
1631 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
1632 | //\r | |
1633 | Status = SdMmcCheckTrbEnv (Private, Trb);\r | |
1634 | if (Status != EFI_NOT_READY) {\r | |
1635 | return Status;\r | |
1636 | }\r | |
1637 | //\r | |
1638 | // Stall for 1 microsecond.\r | |
1639 | //\r | |
1640 | gBS->Stall (1);\r | |
1641 | \r | |
1642 | Timeout--;\r | |
1643 | }\r | |
1644 | \r | |
1645 | return EFI_TIMEOUT;\r | |
1646 | }\r | |
1647 | \r | |
1648 | /**\r | |
1649 | Execute the specified TRB.\r | |
1650 | \r | |
1651 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1652 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1653 | \r | |
1654 | @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r | |
1655 | @retval Others Some erros happen when sending this request to the host controller.\r | |
1656 | \r | |
1657 | **/\r | |
1658 | EFI_STATUS\r | |
1659 | SdMmcExecTrb (\r | |
1660 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1661 | IN SD_MMC_HC_TRB *Trb\r | |
1662 | )\r | |
1663 | {\r | |
1664 | EFI_STATUS Status;\r | |
1665 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1666 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1667 | UINT16 Cmd;\r | |
1668 | UINT16 IntStatus;\r | |
1669 | UINT32 Argument;\r | |
1670 | UINT16 BlkCount;\r | |
1671 | UINT16 BlkSize;\r | |
1672 | UINT16 TransMode;\r | |
1673 | UINT8 HostCtrl1;\r | |
1674 | UINT32 SdmaAddr;\r | |
1675 | UINT64 AdmaAddr;\r | |
1676 | \r | |
1677 | Packet = Trb->Packet;\r | |
1678 | PciIo = Trb->Private->PciIo;\r | |
1679 | //\r | |
1680 | // Clear all bits in Error Interrupt Status Register\r | |
1681 | //\r | |
1682 | IntStatus = 0xFFFF;\r | |
1683 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
1684 | if (EFI_ERROR (Status)) {\r | |
1685 | return Status;\r | |
1686 | }\r | |
1687 | //\r | |
1688 | // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.\r | |
1689 | //\r | |
1690 | IntStatus = 0xFF3F;\r | |
1691 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
1692 | if (EFI_ERROR (Status)) {\r | |
1693 | return Status;\r | |
1694 | }\r | |
1695 | //\r | |
1696 | // Set Host Control 1 register DMA Select field\r | |
1697 | //\r | |
1698 | if (Trb->Mode == SdMmcAdmaMode) {\r | |
1699 | HostCtrl1 = BIT4;\r | |
1700 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1701 | if (EFI_ERROR (Status)) {\r | |
1702 | return Status;\r | |
1703 | }\r | |
1704 | }\r | |
1705 | \r | |
1706 | SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r | |
1707 | \r | |
1708 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
1709 | if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {\r | |
1710 | return EFI_INVALID_PARAMETER;\r | |
1711 | }\r | |
1712 | \r | |
1713 | SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;\r | |
1714 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);\r | |
1715 | if (EFI_ERROR (Status)) {\r | |
1716 | return Status;\r | |
1717 | }\r | |
1718 | } else if (Trb->Mode == SdMmcAdmaMode) {\r | |
1719 | AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;\r | |
1720 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r | |
1721 | if (EFI_ERROR (Status)) {\r | |
1722 | return Status;\r | |
1723 | }\r | |
1724 | }\r | |
1725 | \r | |
1726 | BlkSize = Trb->BlockSize;\r | |
1727 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
1728 | //\r | |
1729 | // Set SDMA boundary to be 512K bytes.\r | |
1730 | //\r | |
1731 | BlkSize |= 0x7000;\r | |
1732 | }\r | |
1733 | \r | |
1734 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r | |
1735 | if (EFI_ERROR (Status)) {\r | |
1736 | return Status;\r | |
1737 | }\r | |
1738 | \r | |
e7e89b08 FT |
1739 | BlkCount = 0;\r |
1740 | if (Trb->Mode != SdMmcNoData) {\r | |
1741 | //\r | |
1742 | // Calcuate Block Count.\r | |
1743 | //\r | |
1744 | BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);\r | |
1745 | }\r | |
48555339 FT |
1746 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r |
1747 | if (EFI_ERROR (Status)) {\r | |
1748 | return Status;\r | |
1749 | }\r | |
1750 | \r | |
1751 | Argument = Packet->SdMmcCmdBlk->CommandArgument;\r | |
1752 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r | |
1753 | if (EFI_ERROR (Status)) {\r | |
1754 | return Status;\r | |
1755 | }\r | |
1756 | \r | |
1757 | TransMode = 0;\r | |
1758 | if (Trb->Mode != SdMmcNoData) {\r | |
1759 | if (Trb->Mode != SdMmcPioMode) {\r | |
1760 | TransMode |= BIT0;\r | |
1761 | }\r | |
1762 | if (Trb->Read) {\r | |
1763 | TransMode |= BIT4;\r | |
1764 | }\r | |
e7e89b08 | 1765 | if (BlkCount > 1) {\r |
48555339 FT |
1766 | TransMode |= BIT5 | BIT1;\r |
1767 | }\r | |
1768 | //\r | |
1769 | // Only SD memory card needs to use AUTO CMD12 feature.\r | |
1770 | //\r | |
1771 | if (Private->Slot[Trb->Slot].CardType == SdCardType) {\r | |
1772 | if (BlkCount > 1) {\r | |
1773 | TransMode |= BIT2;\r | |
1774 | }\r | |
1775 | }\r | |
1776 | }\r | |
1777 | \r | |
1778 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r | |
1779 | if (EFI_ERROR (Status)) {\r | |
1780 | return Status;\r | |
1781 | }\r | |
1782 | \r | |
1783 | Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);\r | |
1784 | if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {\r | |
1785 | Cmd |= BIT5;\r | |
1786 | }\r | |
1787 | //\r | |
1788 | // Convert ResponseType to value\r | |
1789 | //\r | |
1790 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
1791 | switch (Packet->SdMmcCmdBlk->ResponseType) {\r | |
1792 | case SdMmcResponseTypeR1:\r | |
1793 | case SdMmcResponseTypeR5:\r | |
1794 | case SdMmcResponseTypeR6:\r | |
1795 | case SdMmcResponseTypeR7:\r | |
1796 | Cmd |= (BIT1 | BIT3 | BIT4);\r | |
1797 | break;\r | |
1798 | case SdMmcResponseTypeR2:\r | |
1799 | Cmd |= (BIT0 | BIT3);\r | |
1800 | break;\r | |
1801 | case SdMmcResponseTypeR3:\r | |
1802 | case SdMmcResponseTypeR4:\r | |
1803 | Cmd |= BIT1;\r | |
1804 | break;\r | |
1805 | case SdMmcResponseTypeR1b:\r | |
1806 | case SdMmcResponseTypeR5b:\r | |
1807 | Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r | |
1808 | break;\r | |
1809 | default:\r | |
1810 | ASSERT (FALSE);\r | |
1811 | break;\r | |
1812 | }\r | |
1813 | }\r | |
1814 | //\r | |
1815 | // Execute cmd\r | |
1816 | //\r | |
1817 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r | |
1818 | return Status;\r | |
1819 | }\r | |
1820 | \r | |
1821 | /**\r | |
1822 | Check the TRB execution result.\r | |
1823 | \r | |
1824 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1825 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1826 | \r | |
1827 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
1828 | @retval EFI_NOT_READY The TRB is not completed for execution.\r | |
1829 | @retval Others Some erros happen when executing this request.\r | |
1830 | \r | |
1831 | **/\r | |
1832 | EFI_STATUS\r | |
1833 | SdMmcCheckTrbResult (\r | |
1834 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1835 | IN SD_MMC_HC_TRB *Trb\r | |
1836 | )\r | |
1837 | {\r | |
1838 | EFI_STATUS Status;\r | |
1839 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1840 | UINT16 IntStatus;\r | |
1841 | UINT32 Response[4];\r | |
1842 | UINT32 SdmaAddr;\r | |
1843 | UINT8 Index;\r | |
1844 | UINT8 SwReset;\r | |
e7e89b08 | 1845 | UINT32 PioLength;\r |
48555339 FT |
1846 | \r |
1847 | SwReset = 0;\r | |
1848 | Packet = Trb->Packet;\r | |
1849 | //\r | |
1850 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
1851 | //\r | |
1852 | Status = SdMmcHcRwMmio (\r | |
1853 | Private->PciIo,\r | |
1854 | Trb->Slot,\r | |
1855 | SD_MMC_HC_NOR_INT_STS,\r | |
1856 | TRUE,\r | |
1857 | sizeof (IntStatus),\r | |
1858 | &IntStatus\r | |
1859 | );\r | |
1860 | if (EFI_ERROR (Status)) {\r | |
1861 | goto Done;\r | |
1862 | }\r | |
1863 | //\r | |
1864 | // Check Transfer Complete bit is set or not.\r | |
1865 | //\r | |
1866 | if ((IntStatus & BIT1) == BIT1) {\r | |
1867 | if ((IntStatus & BIT15) == BIT15) {\r | |
1868 | //\r | |
1869 | // Read Error Interrupt Status register to check if the error is\r | |
1870 | // Data Timeout Error.\r | |
1871 | // If yes, treat it as success as Transfer Complete has higher\r | |
1872 | // priority than Data Timeout Error.\r | |
1873 | //\r | |
1874 | Status = SdMmcHcRwMmio (\r | |
1875 | Private->PciIo,\r | |
1876 | Trb->Slot,\r | |
1877 | SD_MMC_HC_ERR_INT_STS,\r | |
1878 | TRUE,\r | |
1879 | sizeof (IntStatus),\r | |
1880 | &IntStatus\r | |
1881 | );\r | |
1882 | if (!EFI_ERROR (Status)) {\r | |
1883 | if ((IntStatus & BIT4) == BIT4) {\r | |
1884 | Status = EFI_SUCCESS;\r | |
1885 | } else {\r | |
1886 | Status = EFI_DEVICE_ERROR;\r | |
1887 | }\r | |
1888 | }\r | |
1889 | }\r | |
1890 | \r | |
1891 | goto Done;\r | |
1892 | }\r | |
1893 | //\r | |
1894 | // Check if there is a error happened during cmd execution.\r | |
1895 | // If yes, then do error recovery procedure to follow SD Host Controller\r | |
1896 | // Simplified Spec 3.0 section 3.10.1.\r | |
1897 | //\r | |
1898 | if ((IntStatus & BIT15) == BIT15) {\r | |
1899 | Status = SdMmcHcRwMmio (\r | |
1900 | Private->PciIo,\r | |
1901 | Trb->Slot,\r | |
1902 | SD_MMC_HC_ERR_INT_STS,\r | |
1903 | TRUE,\r | |
1904 | sizeof (IntStatus),\r | |
1905 | &IntStatus\r | |
1906 | );\r | |
1907 | if (EFI_ERROR (Status)) {\r | |
1908 | goto Done;\r | |
1909 | }\r | |
1910 | if ((IntStatus & 0x0F) != 0) {\r | |
1911 | SwReset |= BIT1;\r | |
1912 | }\r | |
1913 | if ((IntStatus & 0xF0) != 0) {\r | |
1914 | SwReset |= BIT2;\r | |
1915 | }\r | |
1916 | \r | |
1917 | Status = SdMmcHcRwMmio (\r | |
1918 | Private->PciIo,\r | |
1919 | Trb->Slot,\r | |
1920 | SD_MMC_HC_SW_RST,\r | |
1921 | FALSE,\r | |
1922 | sizeof (SwReset),\r | |
1923 | &SwReset\r | |
1924 | );\r | |
1925 | if (EFI_ERROR (Status)) {\r | |
1926 | goto Done;\r | |
1927 | }\r | |
1928 | Status = SdMmcHcWaitMmioSet (\r | |
1929 | Private->PciIo,\r | |
1930 | Trb->Slot,\r | |
1931 | SD_MMC_HC_SW_RST,\r | |
1932 | sizeof (SwReset),\r | |
1933 | 0xFF,\r | |
1934 | 0,\r | |
1935 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
1936 | );\r | |
1937 | if (EFI_ERROR (Status)) {\r | |
1938 | goto Done;\r | |
1939 | }\r | |
1940 | \r | |
1941 | Status = EFI_DEVICE_ERROR;\r | |
1942 | goto Done;\r | |
1943 | }\r | |
1944 | //\r | |
1945 | // Check if DMA interrupt is signalled for the SDMA transfer.\r | |
1946 | //\r | |
1947 | if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r | |
1948 | //\r | |
1949 | // Clear DMA interrupt bit.\r | |
1950 | //\r | |
1951 | IntStatus = BIT3;\r | |
1952 | Status = SdMmcHcRwMmio (\r | |
1953 | Private->PciIo,\r | |
1954 | Trb->Slot,\r | |
1955 | SD_MMC_HC_NOR_INT_STS,\r | |
1956 | FALSE,\r | |
1957 | sizeof (IntStatus),\r | |
1958 | &IntStatus\r | |
1959 | );\r | |
1960 | if (EFI_ERROR (Status)) {\r | |
1961 | goto Done;\r | |
1962 | }\r | |
1963 | //\r | |
1964 | // Update SDMA Address register.\r | |
1965 | //\r | |
1966 | SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r | |
1967 | Status = SdMmcHcRwMmio (\r | |
1968 | Private->PciIo,\r | |
1969 | Trb->Slot,\r | |
1970 | SD_MMC_HC_SDMA_ADDR,\r | |
1971 | FALSE,\r | |
1972 | sizeof (UINT32),\r | |
1973 | &SdmaAddr\r | |
1974 | );\r | |
1975 | if (EFI_ERROR (Status)) {\r | |
1976 | goto Done;\r | |
1977 | }\r | |
1978 | Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;\r | |
1979 | }\r | |
1980 | \r | |
1981 | if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&\r | |
1982 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&\r | |
1983 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {\r | |
1984 | if ((IntStatus & BIT0) == BIT0) {\r | |
1985 | Status = EFI_SUCCESS;\r | |
1986 | goto Done;\r | |
1987 | }\r | |
1988 | }\r | |
1989 | \r | |
1990 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
1991 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
1992 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
1993 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
1994 | //\r | |
e7e89b08 FT |
1995 | // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,\r |
1996 | // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.\r | |
1997 | // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.\r | |
48555339 | 1998 | //\r |
e7e89b08 FT |
1999 | if ((IntStatus & BIT5) == BIT5) {\r |
2000 | //\r | |
2001 | // Clear Buffer Read Ready interrupt at first.\r | |
2002 | //\r | |
2003 | IntStatus = BIT5;\r | |
2004 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
2005 | //\r | |
2006 | // Read data out from Buffer Port register\r | |
2007 | //\r | |
2008 | for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {\r | |
2009 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);\r | |
2010 | }\r | |
2011 | Status = EFI_SUCCESS;\r | |
2012 | goto Done;\r | |
2013 | }\r | |
48555339 FT |
2014 | }\r |
2015 | \r | |
2016 | Status = EFI_NOT_READY;\r | |
2017 | Done:\r | |
2018 | //\r | |
2019 | // Get response data when the cmd is executed successfully.\r | |
2020 | //\r | |
2021 | if (!EFI_ERROR (Status)) {\r | |
2022 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
2023 | for (Index = 0; Index < 4; Index++) {\r | |
2024 | Status = SdMmcHcRwMmio (\r | |
2025 | Private->PciIo,\r | |
2026 | Trb->Slot,\r | |
2027 | SD_MMC_HC_RESPONSE + Index * 4,\r | |
2028 | TRUE,\r | |
2029 | sizeof (UINT32),\r | |
2030 | &Response[Index]\r | |
2031 | );\r | |
2032 | if (EFI_ERROR (Status)) {\r | |
2033 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
2034 | return Status;\r | |
2035 | }\r | |
2036 | }\r | |
2037 | CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));\r | |
2038 | }\r | |
2039 | }\r | |
2040 | \r | |
2041 | if (Status != EFI_NOT_READY) {\r | |
2042 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
2043 | }\r | |
2044 | \r | |
2045 | return Status;\r | |
2046 | }\r | |
2047 | \r | |
2048 | /**\r | |
2049 | Wait for the TRB execution result.\r | |
2050 | \r | |
2051 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2052 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2053 | \r | |
2054 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
2055 | @retval Others Some erros happen when executing this request.\r | |
2056 | \r | |
2057 | **/\r | |
2058 | EFI_STATUS\r | |
2059 | SdMmcWaitTrbResult (\r | |
2060 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2061 | IN SD_MMC_HC_TRB *Trb\r | |
2062 | )\r | |
2063 | {\r | |
2064 | EFI_STATUS Status;\r | |
2065 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2066 | UINT64 Timeout;\r | |
2067 | BOOLEAN InfiniteWait;\r | |
2068 | \r | |
2069 | Packet = Trb->Packet;\r | |
2070 | //\r | |
2071 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
2072 | //\r | |
2073 | Timeout = Packet->Timeout;\r | |
2074 | if (Timeout == 0) {\r | |
2075 | InfiniteWait = TRUE;\r | |
2076 | } else {\r | |
2077 | InfiniteWait = FALSE;\r | |
2078 | }\r | |
2079 | \r | |
2080 | while (InfiniteWait || (Timeout > 0)) {\r | |
2081 | //\r | |
2082 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2083 | //\r | |
2084 | Status = SdMmcCheckTrbResult (Private, Trb);\r | |
2085 | if (Status != EFI_NOT_READY) {\r | |
2086 | return Status;\r | |
2087 | }\r | |
2088 | //\r | |
2089 | // Stall for 1 microsecond.\r | |
2090 | //\r | |
2091 | gBS->Stall (1);\r | |
2092 | \r | |
2093 | Timeout--;\r | |
2094 | }\r | |
2095 | \r | |
2096 | return EFI_TIMEOUT;\r | |
2097 | }\r | |
2098 | \r |