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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
4
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
6
7 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "SdMmcPciHcDxe.h"
19
20 /**
21 Dump the content of SD/MMC host controller's Capability Register.
22
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
25
26 **/
27 VOID
28 DumpCapabilityReg (
29 IN UINT8 Slot,
30 IN SD_MMC_HC_SLOT_CAP *Capability
31 )
32 {
33 //
34 // Dump Capability Data
35 //
36 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
37 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
38 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
39 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
40 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " SlotType "));
51 if (Capability->SlotType == 0x00) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
53 } else if (Capability->SlotType == 0x01) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
55 } else if (Capability->SlotType == 0x02) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
57 } else {
58 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
59 }
60 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
67 if (Capability->TimerCount == 0) {
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
69 } else {
70 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
71 }
72 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
73 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
74 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
75 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
76 return;
77 }
78
79 /**
80 Read SlotInfo register from SD/MMC host controller pci config space.
81
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
85
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
88
89 **/
90 EFI_STATUS
91 EFIAPI
92 SdMmcHcGetSlotInfo (
93 IN EFI_PCI_IO_PROTOCOL *PciIo,
94 OUT UINT8 *FirstBar,
95 OUT UINT8 *SlotNum
96 )
97 {
98 EFI_STATUS Status;
99 SD_MMC_HC_SLOT_INFO SlotInfo;
100
101 Status = PciIo->Pci.Read (
102 PciIo,
103 EfiPciIoWidthUint8,
104 SD_MMC_HC_SLOT_OFFSET,
105 sizeof (SlotInfo),
106 &SlotInfo
107 );
108 if (EFI_ERROR (Status)) {
109 return Status;
110 }
111
112 *FirstBar = SlotInfo.FirstBar;
113 *SlotNum = SlotInfo.SlotNum + 1;
114 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
115 return EFI_SUCCESS;
116 }
117
118 /**
119 Read/Write specified SD/MMC host controller mmio register.
120
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
126 memory operation.
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
135
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
139
140 **/
141 EFI_STATUS
142 EFIAPI
143 SdMmcHcRwMmio (
144 IN EFI_PCI_IO_PROTOCOL *PciIo,
145 IN UINT8 BarIndex,
146 IN UINT32 Offset,
147 IN BOOLEAN Read,
148 IN UINT8 Count,
149 IN OUT VOID *Data
150 )
151 {
152 EFI_STATUS Status;
153
154 if ((PciIo == NULL) || (Data == NULL)) {
155 return EFI_INVALID_PARAMETER;
156 }
157
158 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if (Read) {
163 Status = PciIo->Mem.Read (
164 PciIo,
165 EfiPciIoWidthUint8,
166 BarIndex,
167 (UINT64) Offset,
168 Count,
169 Data
170 );
171 } else {
172 Status = PciIo->Mem.Write (
173 PciIo,
174 EfiPciIoWidthUint8,
175 BarIndex,
176 (UINT64) Offset,
177 Count,
178 Data
179 );
180 }
181
182 return Status;
183 }
184
185 /**
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
187
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
193 memory operation.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
199 Count bytes.
200
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
204
205 **/
206 EFI_STATUS
207 EFIAPI
208 SdMmcHcOrMmio (
209 IN EFI_PCI_IO_PROTOCOL *PciIo,
210 IN UINT8 BarIndex,
211 IN UINT32 Offset,
212 IN UINT8 Count,
213 IN VOID *OrData
214 )
215 {
216 EFI_STATUS Status;
217 UINT64 Data;
218 UINT64 Or;
219
220 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 if (Count == 1) {
226 Or = *(UINT8*) OrData;
227 } else if (Count == 2) {
228 Or = *(UINT16*) OrData;
229 } else if (Count == 4) {
230 Or = *(UINT32*) OrData;
231 } else if (Count == 8) {
232 Or = *(UINT64*) OrData;
233 } else {
234 return EFI_INVALID_PARAMETER;
235 }
236
237 Data |= Or;
238 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
239
240 return Status;
241 }
242
243 /**
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
245
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
251 memory operation.
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
257 Count bytes.
258
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
262
263 **/
264 EFI_STATUS
265 EFIAPI
266 SdMmcHcAndMmio (
267 IN EFI_PCI_IO_PROTOCOL *PciIo,
268 IN UINT8 BarIndex,
269 IN UINT32 Offset,
270 IN UINT8 Count,
271 IN VOID *AndData
272 )
273 {
274 EFI_STATUS Status;
275 UINT64 Data;
276 UINT64 And;
277
278 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
279 if (EFI_ERROR (Status)) {
280 return Status;
281 }
282
283 if (Count == 1) {
284 And = *(UINT8*) AndData;
285 } else if (Count == 2) {
286 And = *(UINT16*) AndData;
287 } else if (Count == 4) {
288 And = *(UINT32*) AndData;
289 } else if (Count == 8) {
290 And = *(UINT64*) AndData;
291 } else {
292 return EFI_INVALID_PARAMETER;
293 }
294
295 Data &= And;
296 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
297
298 return Status;
299 }
300
301 /**
302 Wait for the value of the specified MMIO register set to the test value.
303
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
309 memory operation.
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
314
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
318
319 **/
320 EFI_STATUS
321 EFIAPI
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL *PciIo,
324 IN UINT8 BarIndex,
325 IN UINT32 Offset,
326 IN UINT8 Count,
327 IN UINT64 MaskValue,
328 IN UINT64 TestValue
329 )
330 {
331 EFI_STATUS Status;
332 UINT64 Value;
333
334 //
335 // Access PCI MMIO space to see if the value is the tested one.
336 //
337 Value = 0;
338 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
339 if (EFI_ERROR (Status)) {
340 return Status;
341 }
342
343 Value &= MaskValue;
344
345 if (Value == TestValue) {
346 return EFI_SUCCESS;
347 }
348
349 return EFI_NOT_READY;
350 }
351
352 /**
353 Wait for the value of the specified MMIO register set to the test value.
354
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
360 memory operation.
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
367
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
369 range.
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
372
373 **/
374 EFI_STATUS
375 EFIAPI
376 SdMmcHcWaitMmioSet (
377 IN EFI_PCI_IO_PROTOCOL *PciIo,
378 IN UINT8 BarIndex,
379 IN UINT32 Offset,
380 IN UINT8 Count,
381 IN UINT64 MaskValue,
382 IN UINT64 TestValue,
383 IN UINT64 Timeout
384 )
385 {
386 EFI_STATUS Status;
387 BOOLEAN InfiniteWait;
388
389 if (Timeout == 0) {
390 InfiniteWait = TRUE;
391 } else {
392 InfiniteWait = FALSE;
393 }
394
395 while (InfiniteWait || (Timeout > 0)) {
396 Status = SdMmcHcCheckMmioSet (
397 PciIo,
398 BarIndex,
399 Offset,
400 Count,
401 MaskValue,
402 TestValue
403 );
404 if (Status != EFI_NOT_READY) {
405 return Status;
406 }
407
408 //
409 // Stall for 1 microsecond.
410 //
411 gBS->Stall (1);
412
413 Timeout--;
414 }
415
416 return EFI_TIMEOUT;
417 }
418
419 /**
420 Software reset the specified SD/MMC host controller and enable all interrupts.
421
422 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
424
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
427
428 **/
429 EFI_STATUS
430 SdMmcHcReset (
431 IN SD_MMC_HC_PRIVATE_DATA *Private,
432 IN UINT8 Slot
433 )
434 {
435 EFI_STATUS Status;
436 UINT8 SwReset;
437 EFI_PCI_IO_PROTOCOL *PciIo;
438
439 //
440 // Notify the SD/MMC override protocol that we are about to reset
441 // the SD/MMC host controller.
442 //
443 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
444 Status = mOverride->NotifyPhase (
445 Private->ControllerHandle,
446 Slot,
447 EdkiiSdMmcResetPre,
448 NULL);
449 if (EFI_ERROR (Status)) {
450 DEBUG ((DEBUG_WARN,
451 "%a: SD/MMC pre reset notifier callback failed - %r\n",
452 __FUNCTION__, Status));
453 return Status;
454 }
455 }
456
457 PciIo = Private->PciIo;
458 SwReset = BIT0;
459 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
460
461 if (EFI_ERROR (Status)) {
462 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
463 return Status;
464 }
465
466 Status = SdMmcHcWaitMmioSet (
467 PciIo,
468 Slot,
469 SD_MMC_HC_SW_RST,
470 sizeof (SwReset),
471 BIT0,
472 0x00,
473 SD_MMC_HC_GENERIC_TIMEOUT
474 );
475 if (EFI_ERROR (Status)) {
476 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
477 return Status;
478 }
479
480 //
481 // Enable all interrupt after reset all.
482 //
483 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
484 if (EFI_ERROR (Status)) {
485 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
486 Status));
487 return Status;
488 }
489
490 //
491 // Notify the SD/MMC override protocol that we have just reset
492 // the SD/MMC host controller.
493 //
494 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
495 Status = mOverride->NotifyPhase (
496 Private->ControllerHandle,
497 Slot,
498 EdkiiSdMmcResetPost,
499 NULL);
500 if (EFI_ERROR (Status)) {
501 DEBUG ((DEBUG_WARN,
502 "%a: SD/MMC post reset notifier callback failed - %r\n",
503 __FUNCTION__, Status));
504 }
505 }
506
507 return Status;
508 }
509
510 /**
511 Set all interrupt status bits in Normal and Error Interrupt Status Enable
512 register.
513
514 @param[in] PciIo The PCI IO protocol instance.
515 @param[in] Slot The slot number of the SD card to send the command to.
516
517 @retval EFI_SUCCESS The operation executes successfully.
518 @retval Others The operation fails.
519
520 **/
521 EFI_STATUS
522 SdMmcHcEnableInterrupt (
523 IN EFI_PCI_IO_PROTOCOL *PciIo,
524 IN UINT8 Slot
525 )
526 {
527 EFI_STATUS Status;
528 UINT16 IntStatus;
529
530 //
531 // Enable all bits in Error Interrupt Status Enable Register
532 //
533 IntStatus = 0xFFFF;
534 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
535 if (EFI_ERROR (Status)) {
536 return Status;
537 }
538 //
539 // Enable all bits in Normal Interrupt Status Enable Register
540 //
541 IntStatus = 0xFFFF;
542 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
543
544 return Status;
545 }
546
547 /**
548 Get the capability data from the specified slot.
549
550 @param[in] PciIo The PCI IO protocol instance.
551 @param[in] Slot The slot number of the SD card to send the command to.
552 @param[out] Capability The buffer to store the capability data.
553
554 @retval EFI_SUCCESS The operation executes successfully.
555 @retval Others The operation fails.
556
557 **/
558 EFI_STATUS
559 SdMmcHcGetCapability (
560 IN EFI_PCI_IO_PROTOCOL *PciIo,
561 IN UINT8 Slot,
562 OUT SD_MMC_HC_SLOT_CAP *Capability
563 )
564 {
565 EFI_STATUS Status;
566 UINT64 Cap;
567
568 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
569 if (EFI_ERROR (Status)) {
570 return Status;
571 }
572
573 CopyMem (Capability, &Cap, sizeof (Cap));
574
575 return EFI_SUCCESS;
576 }
577
578 /**
579 Get the maximum current capability data from the specified slot.
580
581 @param[in] PciIo The PCI IO protocol instance.
582 @param[in] Slot The slot number of the SD card to send the command to.
583 @param[out] MaxCurrent The buffer to store the maximum current capability data.
584
585 @retval EFI_SUCCESS The operation executes successfully.
586 @retval Others The operation fails.
587
588 **/
589 EFI_STATUS
590 SdMmcHcGetMaxCurrent (
591 IN EFI_PCI_IO_PROTOCOL *PciIo,
592 IN UINT8 Slot,
593 OUT UINT64 *MaxCurrent
594 )
595 {
596 EFI_STATUS Status;
597
598 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
599
600 return Status;
601 }
602
603 /**
604 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
605 slot.
606
607 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
608
609 @param[in] PciIo The PCI IO protocol instance.
610 @param[in] Slot The slot number of the SD card to send the command to.
611 @param[out] MediaPresent The pointer to the media present boolean value.
612
613 @retval EFI_SUCCESS There is no media change happened.
614 @retval EFI_MEDIA_CHANGED There is media change happened.
615 @retval Others The detection fails.
616
617 **/
618 EFI_STATUS
619 SdMmcHcCardDetect (
620 IN EFI_PCI_IO_PROTOCOL *PciIo,
621 IN UINT8 Slot,
622 OUT BOOLEAN *MediaPresent
623 )
624 {
625 EFI_STATUS Status;
626 UINT16 Data;
627 UINT32 PresentState;
628
629 //
630 // Check Present State Register to see if there is a card presented.
631 //
632 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
633 if (EFI_ERROR (Status)) {
634 return Status;
635 }
636
637 if ((PresentState & BIT16) != 0) {
638 *MediaPresent = TRUE;
639 } else {
640 *MediaPresent = FALSE;
641 }
642
643 //
644 // Check Normal Interrupt Status Register
645 //
646 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
647 if (EFI_ERROR (Status)) {
648 return Status;
649 }
650
651 if ((Data & (BIT6 | BIT7)) != 0) {
652 //
653 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
654 //
655 Data &= BIT6 | BIT7;
656 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
657 if (EFI_ERROR (Status)) {
658 return Status;
659 }
660
661 return EFI_MEDIA_CHANGED;
662 }
663
664 return EFI_SUCCESS;
665 }
666
667 /**
668 Stop SD/MMC card clock.
669
670 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
671
672 @param[in] PciIo The PCI IO protocol instance.
673 @param[in] Slot The slot number of the SD card to send the command to.
674
675 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
676 @retval Others Fail to stop SD/MMC clock.
677
678 **/
679 EFI_STATUS
680 SdMmcHcStopClock (
681 IN EFI_PCI_IO_PROTOCOL *PciIo,
682 IN UINT8 Slot
683 )
684 {
685 EFI_STATUS Status;
686 UINT32 PresentState;
687 UINT16 ClockCtrl;
688
689 //
690 // Ensure no SD transactions are occurring on the SD Bus by
691 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
692 // in the Present State register to be 0.
693 //
694 Status = SdMmcHcWaitMmioSet (
695 PciIo,
696 Slot,
697 SD_MMC_HC_PRESENT_STATE,
698 sizeof (PresentState),
699 BIT0 | BIT1,
700 0,
701 SD_MMC_HC_GENERIC_TIMEOUT
702 );
703 if (EFI_ERROR (Status)) {
704 return Status;
705 }
706
707 //
708 // Set SD Clock Enable in the Clock Control register to 0
709 //
710 ClockCtrl = (UINT16)~BIT2;
711 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
712
713 return Status;
714 }
715
716 /**
717 SD/MMC card clock supply.
718
719 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
720
721 @param[in] PciIo The PCI IO protocol instance.
722 @param[in] Slot The slot number of the SD card to send the command to.
723 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
724 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
725
726 @retval EFI_SUCCESS The clock is supplied successfully.
727 @retval Others The clock isn't supplied successfully.
728
729 **/
730 EFI_STATUS
731 SdMmcHcClockSupply (
732 IN EFI_PCI_IO_PROTOCOL *PciIo,
733 IN UINT8 Slot,
734 IN UINT64 ClockFreq,
735 IN UINT32 BaseClkFreq
736 )
737 {
738 EFI_STATUS Status;
739 UINT32 SettingFreq;
740 UINT32 Divisor;
741 UINT32 Remainder;
742 UINT16 ControllerVer;
743 UINT16 ClockCtrl;
744
745 //
746 // Calculate a divisor for SD clock frequency
747 //
748 ASSERT (BaseClkFreq != 0);
749
750 if (ClockFreq == 0) {
751 return EFI_INVALID_PARAMETER;
752 }
753
754 if (ClockFreq > (BaseClkFreq * 1000)) {
755 ClockFreq = BaseClkFreq * 1000;
756 }
757
758 //
759 // Calculate the divisor of base frequency.
760 //
761 Divisor = 0;
762 SettingFreq = BaseClkFreq * 1000;
763 while (ClockFreq < SettingFreq) {
764 Divisor++;
765
766 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
767 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
768 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
769 break;
770 }
771 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
772 SettingFreq ++;
773 }
774 }
775
776 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
777
778 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
779 if (EFI_ERROR (Status)) {
780 return Status;
781 }
782 //
783 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
784 //
785 if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&
786 ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {
787 ASSERT (Divisor <= 0x3FF);
788 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
789 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
790 //
791 // Only the most significant bit can be used as divisor.
792 //
793 if (((Divisor - 1) & Divisor) != 0) {
794 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
795 }
796 ASSERT (Divisor <= 0x80);
797 ClockCtrl = (Divisor & 0xFF) << 8;
798 } else {
799 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
800 return EFI_UNSUPPORTED;
801 }
802
803 //
804 // Stop bus clock at first
805 //
806 Status = SdMmcHcStopClock (PciIo, Slot);
807 if (EFI_ERROR (Status)) {
808 return Status;
809 }
810
811 //
812 // Supply clock frequency with specified divisor
813 //
814 ClockCtrl |= BIT0;
815 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
816 if (EFI_ERROR (Status)) {
817 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
818 return Status;
819 }
820
821 //
822 // Wait Internal Clock Stable in the Clock Control register to be 1
823 //
824 Status = SdMmcHcWaitMmioSet (
825 PciIo,
826 Slot,
827 SD_MMC_HC_CLOCK_CTRL,
828 sizeof (ClockCtrl),
829 BIT1,
830 BIT1,
831 SD_MMC_HC_GENERIC_TIMEOUT
832 );
833 if (EFI_ERROR (Status)) {
834 return Status;
835 }
836
837 //
838 // Set SD Clock Enable in the Clock Control register to 1
839 //
840 ClockCtrl = BIT2;
841 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
842
843 return Status;
844 }
845
846 /**
847 SD/MMC bus power control.
848
849 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
850
851 @param[in] PciIo The PCI IO protocol instance.
852 @param[in] Slot The slot number of the SD card to send the command to.
853 @param[in] PowerCtrl The value setting to the power control register.
854
855 @retval TRUE There is a SD/MMC card attached.
856 @retval FALSE There is no a SD/MMC card attached.
857
858 **/
859 EFI_STATUS
860 SdMmcHcPowerControl (
861 IN EFI_PCI_IO_PROTOCOL *PciIo,
862 IN UINT8 Slot,
863 IN UINT8 PowerCtrl
864 )
865 {
866 EFI_STATUS Status;
867
868 //
869 // Clr SD Bus Power
870 //
871 PowerCtrl &= (UINT8)~BIT0;
872 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
873 if (EFI_ERROR (Status)) {
874 return Status;
875 }
876
877 //
878 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
879 //
880 PowerCtrl |= BIT0;
881 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
882
883 return Status;
884 }
885
886 /**
887 Set the SD/MMC bus width.
888
889 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
890
891 @param[in] PciIo The PCI IO protocol instance.
892 @param[in] Slot The slot number of the SD card to send the command to.
893 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
894
895 @retval EFI_SUCCESS The bus width is set successfully.
896 @retval Others The bus width isn't set successfully.
897
898 **/
899 EFI_STATUS
900 SdMmcHcSetBusWidth (
901 IN EFI_PCI_IO_PROTOCOL *PciIo,
902 IN UINT8 Slot,
903 IN UINT16 BusWidth
904 )
905 {
906 EFI_STATUS Status;
907 UINT8 HostCtrl1;
908
909 if (BusWidth == 1) {
910 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
911 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
912 } else if (BusWidth == 4) {
913 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
914 if (EFI_ERROR (Status)) {
915 return Status;
916 }
917 HostCtrl1 |= BIT1;
918 HostCtrl1 &= (UINT8)~BIT5;
919 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
920 } else if (BusWidth == 8) {
921 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
922 if (EFI_ERROR (Status)) {
923 return Status;
924 }
925 HostCtrl1 &= (UINT8)~BIT1;
926 HostCtrl1 |= BIT5;
927 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
928 } else {
929 ASSERT (FALSE);
930 return EFI_INVALID_PARAMETER;
931 }
932
933 return Status;
934 }
935
936 /**
937 Supply SD/MMC card with lowest clock frequency at initialization.
938
939 @param[in] PciIo The PCI IO protocol instance.
940 @param[in] Slot The slot number of the SD card to send the command to.
941 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
942
943 @retval EFI_SUCCESS The clock is supplied successfully.
944 @retval Others The clock isn't supplied successfully.
945
946 **/
947 EFI_STATUS
948 SdMmcHcInitClockFreq (
949 IN EFI_PCI_IO_PROTOCOL *PciIo,
950 IN UINT8 Slot,
951 IN UINT32 BaseClkFreq
952 )
953 {
954 EFI_STATUS Status;
955 UINT32 InitFreq;
956
957 //
958 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
959 // the Capability Register 1 can be zero, which means a need for obtaining
960 // the clock frequency via another method. Fail in case it is not updated
961 // by SW at this point.
962 //
963 if (BaseClkFreq == 0) {
964 //
965 // Don't support get Base Clock Frequency information via another method
966 //
967 return EFI_UNSUPPORTED;
968 }
969 //
970 // Supply 400KHz clock frequency at initialization phase.
971 //
972 InitFreq = 400;
973 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);
974 return Status;
975 }
976
977 /**
978 Supply SD/MMC card with maximum voltage at initialization.
979
980 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
981
982 @param[in] PciIo The PCI IO protocol instance.
983 @param[in] Slot The slot number of the SD card to send the command to.
984 @param[in] Capability The capability of the slot.
985
986 @retval EFI_SUCCESS The voltage is supplied successfully.
987 @retval Others The voltage isn't supplied successfully.
988
989 **/
990 EFI_STATUS
991 SdMmcHcInitPowerVoltage (
992 IN EFI_PCI_IO_PROTOCOL *PciIo,
993 IN UINT8 Slot,
994 IN SD_MMC_HC_SLOT_CAP Capability
995 )
996 {
997 EFI_STATUS Status;
998 UINT8 MaxVoltage;
999 UINT8 HostCtrl2;
1000
1001 //
1002 // Calculate supported maximum voltage according to SD Bus Voltage Select
1003 //
1004 if (Capability.Voltage33 != 0) {
1005 //
1006 // Support 3.3V
1007 //
1008 MaxVoltage = 0x0E;
1009 } else if (Capability.Voltage30 != 0) {
1010 //
1011 // Support 3.0V
1012 //
1013 MaxVoltage = 0x0C;
1014 } else if (Capability.Voltage18 != 0) {
1015 //
1016 // Support 1.8V
1017 //
1018 MaxVoltage = 0x0A;
1019 HostCtrl2 = BIT3;
1020 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1021 gBS->Stall (5000);
1022 if (EFI_ERROR (Status)) {
1023 return Status;
1024 }
1025 } else {
1026 ASSERT (FALSE);
1027 return EFI_DEVICE_ERROR;
1028 }
1029
1030 //
1031 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1032 //
1033 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1034
1035 return Status;
1036 }
1037
1038 /**
1039 Initialize the Timeout Control register with most conservative value at initialization.
1040
1041 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1042
1043 @param[in] PciIo The PCI IO protocol instance.
1044 @param[in] Slot The slot number of the SD card to send the command to.
1045
1046 @retval EFI_SUCCESS The timeout control register is configured successfully.
1047 @retval Others The timeout control register isn't configured successfully.
1048
1049 **/
1050 EFI_STATUS
1051 SdMmcHcInitTimeoutCtrl (
1052 IN EFI_PCI_IO_PROTOCOL *PciIo,
1053 IN UINT8 Slot
1054 )
1055 {
1056 EFI_STATUS Status;
1057 UINT8 Timeout;
1058
1059 Timeout = 0x0E;
1060 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1061
1062 return Status;
1063 }
1064
1065 /**
1066 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1067 at initialization.
1068
1069 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1070 @param[in] Slot The slot number of the SD card to send the command to.
1071
1072 @retval EFI_SUCCESS The host controller is initialized successfully.
1073 @retval Others The host controller isn't initialized successfully.
1074
1075 **/
1076 EFI_STATUS
1077 SdMmcHcInitHost (
1078 IN SD_MMC_HC_PRIVATE_DATA *Private,
1079 IN UINT8 Slot
1080 )
1081 {
1082 EFI_STATUS Status;
1083 EFI_PCI_IO_PROTOCOL *PciIo;
1084 SD_MMC_HC_SLOT_CAP Capability;
1085
1086 //
1087 // Notify the SD/MMC override protocol that we are about to initialize
1088 // the SD/MMC host controller.
1089 //
1090 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1091 Status = mOverride->NotifyPhase (
1092 Private->ControllerHandle,
1093 Slot,
1094 EdkiiSdMmcInitHostPre,
1095 NULL);
1096 if (EFI_ERROR (Status)) {
1097 DEBUG ((DEBUG_WARN,
1098 "%a: SD/MMC pre init notifier callback failed - %r\n",
1099 __FUNCTION__, Status));
1100 return Status;
1101 }
1102 }
1103
1104 PciIo = Private->PciIo;
1105 Capability = Private->Capability[Slot];
1106
1107 Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
1108 if (EFI_ERROR (Status)) {
1109 return Status;
1110 }
1111
1112 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1113 if (EFI_ERROR (Status)) {
1114 return Status;
1115 }
1116
1117 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1118 if (EFI_ERROR (Status)) {
1119 return Status;
1120 }
1121
1122 //
1123 // Notify the SD/MMC override protocol that we are have just initialized
1124 // the SD/MMC host controller.
1125 //
1126 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1127 Status = mOverride->NotifyPhase (
1128 Private->ControllerHandle,
1129 Slot,
1130 EdkiiSdMmcInitHostPost,
1131 NULL);
1132 if (EFI_ERROR (Status)) {
1133 DEBUG ((DEBUG_WARN,
1134 "%a: SD/MMC post init notifier callback failed - %r\n",
1135 __FUNCTION__, Status));
1136 }
1137 }
1138 return Status;
1139 }
1140
1141 /**
1142 Set SD Host Controler control 2 registry according to selected speed.
1143
1144 @param[in] ControllerHandle The handle of the controller.
1145 @param[in] PciIo The PCI IO protocol instance.
1146 @param[in] Slot The slot number of the SD card to send the command to.
1147 @param[in] Timing The timing to select.
1148
1149 @retval EFI_SUCCESS The timing is set successfully.
1150 @retval Others The timing isn't set successfully.
1151 **/
1152 EFI_STATUS
1153 SdMmcHcUhsSignaling (
1154 IN EFI_HANDLE ControllerHandle,
1155 IN EFI_PCI_IO_PROTOCOL *PciIo,
1156 IN UINT8 Slot,
1157 IN SD_MMC_BUS_MODE Timing
1158 )
1159 {
1160 EFI_STATUS Status;
1161 UINT8 HostCtrl2;
1162
1163 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1164 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1165 if (EFI_ERROR (Status)) {
1166 return Status;
1167 }
1168
1169 switch (Timing) {
1170 case SdMmcUhsSdr12:
1171 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1172 break;
1173 case SdMmcUhsSdr25:
1174 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1175 break;
1176 case SdMmcUhsSdr50:
1177 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1178 break;
1179 case SdMmcUhsSdr104:
1180 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1181 break;
1182 case SdMmcUhsDdr50:
1183 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1184 break;
1185 case SdMmcMmcLegacy:
1186 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1187 break;
1188 case SdMmcMmcHsSdr:
1189 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1190 break;
1191 case SdMmcMmcHsDdr:
1192 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1193 break;
1194 case SdMmcMmcHs200:
1195 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1196 break;
1197 case SdMmcMmcHs400:
1198 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1199 break;
1200 default:
1201 HostCtrl2 = 0;
1202 break;
1203 }
1204 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1205 if (EFI_ERROR (Status)) {
1206 return Status;
1207 }
1208
1209 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1210 Status = mOverride->NotifyPhase (
1211 ControllerHandle,
1212 Slot,
1213 EdkiiSdMmcUhsSignaling,
1214 &Timing
1215 );
1216 if (EFI_ERROR (Status)) {
1217 DEBUG ((
1218 DEBUG_ERROR,
1219 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1220 __FUNCTION__,
1221 Status
1222 ));
1223 return Status;
1224 }
1225 }
1226
1227 return EFI_SUCCESS;
1228 }
1229
1230 /**
1231 Turn on/off LED.
1232
1233 @param[in] PciIo The PCI IO protocol instance.
1234 @param[in] Slot The slot number of the SD card to send the command to.
1235 @param[in] On The boolean to turn on/off LED.
1236
1237 @retval EFI_SUCCESS The LED is turned on/off successfully.
1238 @retval Others The LED isn't turned on/off successfully.
1239
1240 **/
1241 EFI_STATUS
1242 SdMmcHcLedOnOff (
1243 IN EFI_PCI_IO_PROTOCOL *PciIo,
1244 IN UINT8 Slot,
1245 IN BOOLEAN On
1246 )
1247 {
1248 EFI_STATUS Status;
1249 UINT8 HostCtrl1;
1250
1251 if (On) {
1252 HostCtrl1 = BIT0;
1253 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1254 } else {
1255 HostCtrl1 = (UINT8)~BIT0;
1256 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1257 }
1258
1259 return Status;
1260 }
1261
1262 /**
1263 Build ADMA descriptor table for transfer.
1264
1265 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1266
1267 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1268
1269 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1270 @retval Others The ADMA descriptor table isn't created successfully.
1271
1272 **/
1273 EFI_STATUS
1274 BuildAdmaDescTable (
1275 IN SD_MMC_HC_TRB *Trb
1276 )
1277 {
1278 EFI_PHYSICAL_ADDRESS Data;
1279 UINT64 DataLen;
1280 UINT64 Entries;
1281 UINT32 Index;
1282 UINT64 Remaining;
1283 UINT32 Address;
1284 UINTN TableSize;
1285 EFI_PCI_IO_PROTOCOL *PciIo;
1286 EFI_STATUS Status;
1287 UINTN Bytes;
1288
1289 Data = Trb->DataPhy;
1290 DataLen = Trb->DataLen;
1291 PciIo = Trb->Private->PciIo;
1292 //
1293 // Only support 32bit ADMA Descriptor Table
1294 //
1295 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
1296 return EFI_INVALID_PARAMETER;
1297 }
1298 //
1299 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1300 // for 32-bit address descriptor table.
1301 //
1302 if ((Data & (BIT0 | BIT1)) != 0) {
1303 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1304 }
1305
1306 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
1307 TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));
1308 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1309 Status = PciIo->AllocateBuffer (
1310 PciIo,
1311 AllocateAnyPages,
1312 EfiBootServicesData,
1313 EFI_SIZE_TO_PAGES (TableSize),
1314 (VOID **)&Trb->AdmaDesc,
1315 0
1316 );
1317 if (EFI_ERROR (Status)) {
1318 return EFI_OUT_OF_RESOURCES;
1319 }
1320 ZeroMem (Trb->AdmaDesc, TableSize);
1321 Bytes = TableSize;
1322 Status = PciIo->Map (
1323 PciIo,
1324 EfiPciIoOperationBusMasterCommonBuffer,
1325 Trb->AdmaDesc,
1326 &Bytes,
1327 &Trb->AdmaDescPhy,
1328 &Trb->AdmaMap
1329 );
1330
1331 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1332 //
1333 // Map error or unable to map the whole RFis buffer into a contiguous region.
1334 //
1335 PciIo->FreeBuffer (
1336 PciIo,
1337 EFI_SIZE_TO_PAGES (TableSize),
1338 Trb->AdmaDesc
1339 );
1340 return EFI_OUT_OF_RESOURCES;
1341 }
1342
1343 if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1344 //
1345 // The ADMA doesn't support 64bit addressing.
1346 //
1347 PciIo->Unmap (
1348 PciIo,
1349 Trb->AdmaMap
1350 );
1351 PciIo->FreeBuffer (
1352 PciIo,
1353 EFI_SIZE_TO_PAGES (TableSize),
1354 Trb->AdmaDesc
1355 );
1356 return EFI_DEVICE_ERROR;
1357 }
1358
1359 Remaining = DataLen;
1360 Address = (UINT32)Data;
1361 for (Index = 0; Index < Entries; Index++) {
1362 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
1363 Trb->AdmaDesc[Index].Valid = 1;
1364 Trb->AdmaDesc[Index].Act = 2;
1365 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
1366 Trb->AdmaDesc[Index].Address = Address;
1367 break;
1368 } else {
1369 Trb->AdmaDesc[Index].Valid = 1;
1370 Trb->AdmaDesc[Index].Act = 2;
1371 Trb->AdmaDesc[Index].Length = 0;
1372 Trb->AdmaDesc[Index].Address = Address;
1373 }
1374
1375 Remaining -= ADMA_MAX_DATA_PER_LINE;
1376 Address += ADMA_MAX_DATA_PER_LINE;
1377 }
1378
1379 //
1380 // Set the last descriptor line as end of descriptor table
1381 //
1382 Trb->AdmaDesc[Index].End = 1;
1383 return EFI_SUCCESS;
1384 }
1385
1386 /**
1387 Create a new TRB for the SD/MMC cmd request.
1388
1389 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1390 @param[in] Slot The slot number of the SD card to send the command to.
1391 @param[in] Packet A pointer to the SD command data structure.
1392 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1393 not NULL, then nonblocking I/O is performed, and Event
1394 will be signaled when the Packet completes.
1395
1396 @return Created Trb or NULL.
1397
1398 **/
1399 SD_MMC_HC_TRB *
1400 SdMmcCreateTrb (
1401 IN SD_MMC_HC_PRIVATE_DATA *Private,
1402 IN UINT8 Slot,
1403 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1404 IN EFI_EVENT Event
1405 )
1406 {
1407 SD_MMC_HC_TRB *Trb;
1408 EFI_STATUS Status;
1409 EFI_TPL OldTpl;
1410 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1411 EFI_PCI_IO_PROTOCOL *PciIo;
1412 UINTN MapLength;
1413
1414 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1415 if (Trb == NULL) {
1416 return NULL;
1417 }
1418
1419 Trb->Signature = SD_MMC_HC_TRB_SIG;
1420 Trb->Slot = Slot;
1421 Trb->BlockSize = 0x200;
1422 Trb->Packet = Packet;
1423 Trb->Event = Event;
1424 Trb->Started = FALSE;
1425 Trb->Timeout = Packet->Timeout;
1426 Trb->Private = Private;
1427
1428 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1429 Trb->Data = Packet->InDataBuffer;
1430 Trb->DataLen = Packet->InTransferLength;
1431 Trb->Read = TRUE;
1432 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1433 Trb->Data = Packet->OutDataBuffer;
1434 Trb->DataLen = Packet->OutTransferLength;
1435 Trb->Read = FALSE;
1436 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1437 Trb->Data = NULL;
1438 Trb->DataLen = 0;
1439 } else {
1440 goto Error;
1441 }
1442
1443 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1444 Trb->BlockSize = (UINT16)Trb->DataLen;
1445 }
1446
1447 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1448 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1449 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1450 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1451 Trb->Mode = SdMmcPioMode;
1452 } else {
1453 if (Trb->Read) {
1454 Flag = EfiPciIoOperationBusMasterWrite;
1455 } else {
1456 Flag = EfiPciIoOperationBusMasterRead;
1457 }
1458
1459 PciIo = Private->PciIo;
1460 if (Trb->DataLen != 0) {
1461 MapLength = Trb->DataLen;
1462 Status = PciIo->Map (
1463 PciIo,
1464 Flag,
1465 Trb->Data,
1466 &MapLength,
1467 &Trb->DataPhy,
1468 &Trb->DataMap
1469 );
1470 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1471 Status = EFI_BAD_BUFFER_SIZE;
1472 goto Error;
1473 }
1474 }
1475
1476 if (Trb->DataLen == 0) {
1477 Trb->Mode = SdMmcNoData;
1478 } else if (Private->Capability[Slot].Adma2 != 0) {
1479 Trb->Mode = SdMmcAdmaMode;
1480 Status = BuildAdmaDescTable (Trb);
1481 if (EFI_ERROR (Status)) {
1482 PciIo->Unmap (PciIo, Trb->DataMap);
1483 goto Error;
1484 }
1485 } else if (Private->Capability[Slot].Sdma != 0) {
1486 Trb->Mode = SdMmcSdmaMode;
1487 } else {
1488 Trb->Mode = SdMmcPioMode;
1489 }
1490 }
1491
1492 if (Event != NULL) {
1493 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1494 InsertTailList (&Private->Queue, &Trb->TrbList);
1495 gBS->RestoreTPL (OldTpl);
1496 }
1497
1498 return Trb;
1499
1500 Error:
1501 SdMmcFreeTrb (Trb);
1502 return NULL;
1503 }
1504
1505 /**
1506 Free the resource used by the TRB.
1507
1508 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1509
1510 **/
1511 VOID
1512 SdMmcFreeTrb (
1513 IN SD_MMC_HC_TRB *Trb
1514 )
1515 {
1516 EFI_PCI_IO_PROTOCOL *PciIo;
1517
1518 PciIo = Trb->Private->PciIo;
1519
1520 if (Trb->AdmaMap != NULL) {
1521 PciIo->Unmap (
1522 PciIo,
1523 Trb->AdmaMap
1524 );
1525 }
1526 if (Trb->AdmaDesc != NULL) {
1527 PciIo->FreeBuffer (
1528 PciIo,
1529 Trb->AdmaPages,
1530 Trb->AdmaDesc
1531 );
1532 }
1533 if (Trb->DataMap != NULL) {
1534 PciIo->Unmap (
1535 PciIo,
1536 Trb->DataMap
1537 );
1538 }
1539 FreePool (Trb);
1540 return;
1541 }
1542
1543 /**
1544 Check if the env is ready for execute specified TRB.
1545
1546 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1547 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1548
1549 @retval EFI_SUCCESS The env is ready for TRB execution.
1550 @retval EFI_NOT_READY The env is not ready for TRB execution.
1551 @retval Others Some erros happen.
1552
1553 **/
1554 EFI_STATUS
1555 SdMmcCheckTrbEnv (
1556 IN SD_MMC_HC_PRIVATE_DATA *Private,
1557 IN SD_MMC_HC_TRB *Trb
1558 )
1559 {
1560 EFI_STATUS Status;
1561 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1562 EFI_PCI_IO_PROTOCOL *PciIo;
1563 UINT32 PresentState;
1564
1565 Packet = Trb->Packet;
1566
1567 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1568 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1569 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1570 //
1571 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1572 // the Present State register to be 0
1573 //
1574 PresentState = BIT0 | BIT1;
1575 } else {
1576 //
1577 // Wait Command Inhibit (CMD) in the Present State register
1578 // to be 0
1579 //
1580 PresentState = BIT0;
1581 }
1582
1583 PciIo = Private->PciIo;
1584 Status = SdMmcHcCheckMmioSet (
1585 PciIo,
1586 Trb->Slot,
1587 SD_MMC_HC_PRESENT_STATE,
1588 sizeof (PresentState),
1589 PresentState,
1590 0
1591 );
1592
1593 return Status;
1594 }
1595
1596 /**
1597 Wait for the env to be ready for execute specified TRB.
1598
1599 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1600 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1601
1602 @retval EFI_SUCCESS The env is ready for TRB execution.
1603 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1604 @retval Others Some erros happen.
1605
1606 **/
1607 EFI_STATUS
1608 SdMmcWaitTrbEnv (
1609 IN SD_MMC_HC_PRIVATE_DATA *Private,
1610 IN SD_MMC_HC_TRB *Trb
1611 )
1612 {
1613 EFI_STATUS Status;
1614 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1615 UINT64 Timeout;
1616 BOOLEAN InfiniteWait;
1617
1618 //
1619 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1620 //
1621 Packet = Trb->Packet;
1622 Timeout = Packet->Timeout;
1623 if (Timeout == 0) {
1624 InfiniteWait = TRUE;
1625 } else {
1626 InfiniteWait = FALSE;
1627 }
1628
1629 while (InfiniteWait || (Timeout > 0)) {
1630 //
1631 // Check Trb execution result by reading Normal Interrupt Status register.
1632 //
1633 Status = SdMmcCheckTrbEnv (Private, Trb);
1634 if (Status != EFI_NOT_READY) {
1635 return Status;
1636 }
1637 //
1638 // Stall for 1 microsecond.
1639 //
1640 gBS->Stall (1);
1641
1642 Timeout--;
1643 }
1644
1645 return EFI_TIMEOUT;
1646 }
1647
1648 /**
1649 Execute the specified TRB.
1650
1651 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1652 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1653
1654 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1655 @retval Others Some erros happen when sending this request to the host controller.
1656
1657 **/
1658 EFI_STATUS
1659 SdMmcExecTrb (
1660 IN SD_MMC_HC_PRIVATE_DATA *Private,
1661 IN SD_MMC_HC_TRB *Trb
1662 )
1663 {
1664 EFI_STATUS Status;
1665 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1666 EFI_PCI_IO_PROTOCOL *PciIo;
1667 UINT16 Cmd;
1668 UINT16 IntStatus;
1669 UINT32 Argument;
1670 UINT16 BlkCount;
1671 UINT16 BlkSize;
1672 UINT16 TransMode;
1673 UINT8 HostCtrl1;
1674 UINT32 SdmaAddr;
1675 UINT64 AdmaAddr;
1676
1677 Packet = Trb->Packet;
1678 PciIo = Trb->Private->PciIo;
1679 //
1680 // Clear all bits in Error Interrupt Status Register
1681 //
1682 IntStatus = 0xFFFF;
1683 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1684 if (EFI_ERROR (Status)) {
1685 return Status;
1686 }
1687 //
1688 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1689 //
1690 IntStatus = 0xFF3F;
1691 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1692 if (EFI_ERROR (Status)) {
1693 return Status;
1694 }
1695 //
1696 // Set Host Control 1 register DMA Select field
1697 //
1698 if (Trb->Mode == SdMmcAdmaMode) {
1699 HostCtrl1 = BIT4;
1700 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1701 if (EFI_ERROR (Status)) {
1702 return Status;
1703 }
1704 }
1705
1706 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1707
1708 if (Trb->Mode == SdMmcSdmaMode) {
1709 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1710 return EFI_INVALID_PARAMETER;
1711 }
1712
1713 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1714 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1715 if (EFI_ERROR (Status)) {
1716 return Status;
1717 }
1718 } else if (Trb->Mode == SdMmcAdmaMode) {
1719 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1720 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1721 if (EFI_ERROR (Status)) {
1722 return Status;
1723 }
1724 }
1725
1726 BlkSize = Trb->BlockSize;
1727 if (Trb->Mode == SdMmcSdmaMode) {
1728 //
1729 // Set SDMA boundary to be 512K bytes.
1730 //
1731 BlkSize |= 0x7000;
1732 }
1733
1734 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1735 if (EFI_ERROR (Status)) {
1736 return Status;
1737 }
1738
1739 BlkCount = 0;
1740 if (Trb->Mode != SdMmcNoData) {
1741 //
1742 // Calcuate Block Count.
1743 //
1744 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1745 }
1746 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1747 if (EFI_ERROR (Status)) {
1748 return Status;
1749 }
1750
1751 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1752 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1753 if (EFI_ERROR (Status)) {
1754 return Status;
1755 }
1756
1757 TransMode = 0;
1758 if (Trb->Mode != SdMmcNoData) {
1759 if (Trb->Mode != SdMmcPioMode) {
1760 TransMode |= BIT0;
1761 }
1762 if (Trb->Read) {
1763 TransMode |= BIT4;
1764 }
1765 if (BlkCount > 1) {
1766 TransMode |= BIT5 | BIT1;
1767 }
1768 //
1769 // Only SD memory card needs to use AUTO CMD12 feature.
1770 //
1771 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1772 if (BlkCount > 1) {
1773 TransMode |= BIT2;
1774 }
1775 }
1776 }
1777
1778 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1779 if (EFI_ERROR (Status)) {
1780 return Status;
1781 }
1782
1783 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1784 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1785 Cmd |= BIT5;
1786 }
1787 //
1788 // Convert ResponseType to value
1789 //
1790 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1791 switch (Packet->SdMmcCmdBlk->ResponseType) {
1792 case SdMmcResponseTypeR1:
1793 case SdMmcResponseTypeR5:
1794 case SdMmcResponseTypeR6:
1795 case SdMmcResponseTypeR7:
1796 Cmd |= (BIT1 | BIT3 | BIT4);
1797 break;
1798 case SdMmcResponseTypeR2:
1799 Cmd |= (BIT0 | BIT3);
1800 break;
1801 case SdMmcResponseTypeR3:
1802 case SdMmcResponseTypeR4:
1803 Cmd |= BIT1;
1804 break;
1805 case SdMmcResponseTypeR1b:
1806 case SdMmcResponseTypeR5b:
1807 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1808 break;
1809 default:
1810 ASSERT (FALSE);
1811 break;
1812 }
1813 }
1814 //
1815 // Execute cmd
1816 //
1817 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1818 return Status;
1819 }
1820
1821 /**
1822 Check the TRB execution result.
1823
1824 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1825 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1826
1827 @retval EFI_SUCCESS The TRB is executed successfully.
1828 @retval EFI_NOT_READY The TRB is not completed for execution.
1829 @retval Others Some erros happen when executing this request.
1830
1831 **/
1832 EFI_STATUS
1833 SdMmcCheckTrbResult (
1834 IN SD_MMC_HC_PRIVATE_DATA *Private,
1835 IN SD_MMC_HC_TRB *Trb
1836 )
1837 {
1838 EFI_STATUS Status;
1839 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1840 UINT16 IntStatus;
1841 UINT32 Response[4];
1842 UINT32 SdmaAddr;
1843 UINT8 Index;
1844 UINT8 SwReset;
1845 UINT32 PioLength;
1846
1847 SwReset = 0;
1848 Packet = Trb->Packet;
1849 //
1850 // Check Trb execution result by reading Normal Interrupt Status register.
1851 //
1852 Status = SdMmcHcRwMmio (
1853 Private->PciIo,
1854 Trb->Slot,
1855 SD_MMC_HC_NOR_INT_STS,
1856 TRUE,
1857 sizeof (IntStatus),
1858 &IntStatus
1859 );
1860 if (EFI_ERROR (Status)) {
1861 goto Done;
1862 }
1863 //
1864 // Check Transfer Complete bit is set or not.
1865 //
1866 if ((IntStatus & BIT1) == BIT1) {
1867 if ((IntStatus & BIT15) == BIT15) {
1868 //
1869 // Read Error Interrupt Status register to check if the error is
1870 // Data Timeout Error.
1871 // If yes, treat it as success as Transfer Complete has higher
1872 // priority than Data Timeout Error.
1873 //
1874 Status = SdMmcHcRwMmio (
1875 Private->PciIo,
1876 Trb->Slot,
1877 SD_MMC_HC_ERR_INT_STS,
1878 TRUE,
1879 sizeof (IntStatus),
1880 &IntStatus
1881 );
1882 if (!EFI_ERROR (Status)) {
1883 if ((IntStatus & BIT4) == BIT4) {
1884 Status = EFI_SUCCESS;
1885 } else {
1886 Status = EFI_DEVICE_ERROR;
1887 }
1888 }
1889 }
1890
1891 goto Done;
1892 }
1893 //
1894 // Check if there is a error happened during cmd execution.
1895 // If yes, then do error recovery procedure to follow SD Host Controller
1896 // Simplified Spec 3.0 section 3.10.1.
1897 //
1898 if ((IntStatus & BIT15) == BIT15) {
1899 Status = SdMmcHcRwMmio (
1900 Private->PciIo,
1901 Trb->Slot,
1902 SD_MMC_HC_ERR_INT_STS,
1903 TRUE,
1904 sizeof (IntStatus),
1905 &IntStatus
1906 );
1907 if (EFI_ERROR (Status)) {
1908 goto Done;
1909 }
1910 if ((IntStatus & 0x0F) != 0) {
1911 SwReset |= BIT1;
1912 }
1913 if ((IntStatus & 0xF0) != 0) {
1914 SwReset |= BIT2;
1915 }
1916
1917 Status = SdMmcHcRwMmio (
1918 Private->PciIo,
1919 Trb->Slot,
1920 SD_MMC_HC_SW_RST,
1921 FALSE,
1922 sizeof (SwReset),
1923 &SwReset
1924 );
1925 if (EFI_ERROR (Status)) {
1926 goto Done;
1927 }
1928 Status = SdMmcHcWaitMmioSet (
1929 Private->PciIo,
1930 Trb->Slot,
1931 SD_MMC_HC_SW_RST,
1932 sizeof (SwReset),
1933 0xFF,
1934 0,
1935 SD_MMC_HC_GENERIC_TIMEOUT
1936 );
1937 if (EFI_ERROR (Status)) {
1938 goto Done;
1939 }
1940
1941 Status = EFI_DEVICE_ERROR;
1942 goto Done;
1943 }
1944 //
1945 // Check if DMA interrupt is signalled for the SDMA transfer.
1946 //
1947 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1948 //
1949 // Clear DMA interrupt bit.
1950 //
1951 IntStatus = BIT3;
1952 Status = SdMmcHcRwMmio (
1953 Private->PciIo,
1954 Trb->Slot,
1955 SD_MMC_HC_NOR_INT_STS,
1956 FALSE,
1957 sizeof (IntStatus),
1958 &IntStatus
1959 );
1960 if (EFI_ERROR (Status)) {
1961 goto Done;
1962 }
1963 //
1964 // Update SDMA Address register.
1965 //
1966 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
1967 Status = SdMmcHcRwMmio (
1968 Private->PciIo,
1969 Trb->Slot,
1970 SD_MMC_HC_SDMA_ADDR,
1971 FALSE,
1972 sizeof (UINT32),
1973 &SdmaAddr
1974 );
1975 if (EFI_ERROR (Status)) {
1976 goto Done;
1977 }
1978 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1979 }
1980
1981 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
1982 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
1983 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
1984 if ((IntStatus & BIT0) == BIT0) {
1985 Status = EFI_SUCCESS;
1986 goto Done;
1987 }
1988 }
1989
1990 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1991 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1992 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1993 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1994 //
1995 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
1996 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
1997 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
1998 //
1999 if ((IntStatus & BIT5) == BIT5) {
2000 //
2001 // Clear Buffer Read Ready interrupt at first.
2002 //
2003 IntStatus = BIT5;
2004 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2005 //
2006 // Read data out from Buffer Port register
2007 //
2008 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2009 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2010 }
2011 Status = EFI_SUCCESS;
2012 goto Done;
2013 }
2014 }
2015
2016 Status = EFI_NOT_READY;
2017 Done:
2018 //
2019 // Get response data when the cmd is executed successfully.
2020 //
2021 if (!EFI_ERROR (Status)) {
2022 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2023 for (Index = 0; Index < 4; Index++) {
2024 Status = SdMmcHcRwMmio (
2025 Private->PciIo,
2026 Trb->Slot,
2027 SD_MMC_HC_RESPONSE + Index * 4,
2028 TRUE,
2029 sizeof (UINT32),
2030 &Response[Index]
2031 );
2032 if (EFI_ERROR (Status)) {
2033 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2034 return Status;
2035 }
2036 }
2037 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2038 }
2039 }
2040
2041 if (Status != EFI_NOT_READY) {
2042 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2043 }
2044
2045 return Status;
2046 }
2047
2048 /**
2049 Wait for the TRB execution result.
2050
2051 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2052 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2053
2054 @retval EFI_SUCCESS The TRB is executed successfully.
2055 @retval Others Some erros happen when executing this request.
2056
2057 **/
2058 EFI_STATUS
2059 SdMmcWaitTrbResult (
2060 IN SD_MMC_HC_PRIVATE_DATA *Private,
2061 IN SD_MMC_HC_TRB *Trb
2062 )
2063 {
2064 EFI_STATUS Status;
2065 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2066 UINT64 Timeout;
2067 BOOLEAN InfiniteWait;
2068
2069 Packet = Trb->Packet;
2070 //
2071 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2072 //
2073 Timeout = Packet->Timeout;
2074 if (Timeout == 0) {
2075 InfiniteWait = TRUE;
2076 } else {
2077 InfiniteWait = FALSE;
2078 }
2079
2080 while (InfiniteWait || (Timeout > 0)) {
2081 //
2082 // Check Trb execution result by reading Normal Interrupt Status register.
2083 //
2084 Status = SdMmcCheckTrbResult (Private, Trb);
2085 if (Status != EFI_NOT_READY) {
2086 return Status;
2087 }
2088 //
2089 // Stall for 1 microsecond.
2090 //
2091 gBS->Stall (1);
2092
2093 Timeout--;
2094 }
2095
2096 return EFI_TIMEOUT;
2097 }
2098
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