[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c

/** @file\r
  This driver is used to manage SD/MMC PCI host controllers which are compliance\r
  with SD Host Controller Simplified Specification version 3.00 plus the 64-bit\r
  System Addressing support in SD Host Controller Simplified Specification version\r
  4.20.\r
\r
  It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r
\r
  Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.\r
  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "SdMmcPciHcDxe.h"\r
\r
/**\r
  Dump the content of SD/MMC host controller's Capability Register.\r
\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[in]  Capability      The buffer to store the capability data.\r
\r
**/\r
VOID\r
DumpCapabilityReg (\r
  IN UINT8                Slot,\r
  IN SD_MMC_HC_SLOT_CAP   *Capability\r
  )\r
{\r
  //\r
  // Dump Capability Data\r
  //\r
  DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));\r
  DEBUG ((DEBUG_INFO, "   Timeout Clk Freq  %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));\r
  DEBUG ((DEBUG_INFO, "   Base Clk Freq     %dMHz\n", Capability->BaseClkFreq));\r
  DEBUG ((DEBUG_INFO, "   Max Blk Len       %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));\r
  DEBUG ((DEBUG_INFO, "   8-bit Support     %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   ADMA2 Support     %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   SDMA Support      %a\n", Capability->Sdma ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Suspend/Resume    %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Voltage 3.3       %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Voltage 3.0       %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Voltage 1.8       %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Async Interrupt   %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   SlotType          "));\r
  if (Capability->SlotType == 0x00) {\r
    DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));\r
  } else if (Capability->SlotType == 0x01) {\r
    DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));\r
  } else if (Capability->SlotType == 0x02) {\r
    DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));\r
  } else {\r
    DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));\r
  }\r
  DEBUG ((DEBUG_INFO, "   SDR50  Support    %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   SDR104 Support    %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   DDR50  Support    %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Driver Type A     %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Driver Type C     %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Driver Type D     %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Driver Type 4     %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));\r
  if (Capability->TimerCount == 0) {\r
    DEBUG ((DEBUG_INFO, "   Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));\r
  } else {\r
    DEBUG ((DEBUG_INFO, "   Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));\r
  }\r
  DEBUG ((DEBUG_INFO, "   SDR50 Tuning      %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));\r
  DEBUG ((DEBUG_INFO, "   Retuning Mode     Mode %d\n", Capability->RetuningMod + 1));\r
  DEBUG ((DEBUG_INFO, "   Clock Multiplier  M = %d\n", Capability->ClkMultiplier + 1));\r
  DEBUG ((DEBUG_INFO, "   HS 400            %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));\r
  return;\r
}\r
\r
/**\r
  Read SlotInfo register from SD/MMC host controller pci config space.\r
\r
  @param[in]  PciIo        The PCI IO protocol instance.\r
  @param[out] FirstBar     The buffer to store the first BAR value.\r
  @param[out] SlotNum      The buffer to store the supported slot number.\r
\r
  @retval EFI_SUCCESS      The operation succeeds.\r
  @retval Others           The operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcGetSlotInfo (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
     OUT UINT8                 *FirstBar,\r
     OUT UINT8                 *SlotNum\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  SD_MMC_HC_SLOT_INFO          SlotInfo;\r
\r
  Status = PciIo->Pci.Read (\r
                        PciIo,\r
                        EfiPciIoWidthUint8,\r
                        SD_MMC_HC_SLOT_OFFSET,\r
                        sizeof (SlotInfo),\r
                        &SlotInfo\r
                        );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  *FirstBar = SlotInfo.FirstBar;\r
  *SlotNum  = SlotInfo.SlotNum + 1;\r
  ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Read/Write specified SD/MMC host controller mmio register.\r
\r
  @param[in]      PciIo        The PCI IO protocol instance.\r
  @param[in]      BarIndex     The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in]      Offset       The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in]      Read         A boolean to indicate it's read or write operation.\r
  @param[in]      Count        The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in, out] Data         For read operations, the destination buffer to store\r
                               the results. For write operations, the source buffer\r
                               to write data from. The caller is responsible for\r
                               having ownership of the data buffer and ensuring its\r
                               size not less than Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The read/write operation succeeds.\r
  @retval Others                The read/write operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcRwMmio (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
  IN     UINT8                 BarIndex,\r
  IN     UINT32                Offset,\r
  IN     BOOLEAN               Read,\r
  IN     UINT8                 Count,\r
  IN OUT VOID                  *Data\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  EFI_PCI_IO_PROTOCOL_WIDTH    Width;\r
\r
  if ((PciIo == NULL) || (Data == NULL))  {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  switch (Count) {\r
    case 1:\r
      Width = EfiPciIoWidthUint8;\r
      break;\r
    case 2:\r
      Width = EfiPciIoWidthUint16;\r
      Count = 1;\r
      break;\r
    case 4:\r
      Width = EfiPciIoWidthUint32;\r
      Count = 1;\r
      break;\r
    case 8:\r
      Width = EfiPciIoWidthUint32;\r
      Count = 2;\r
      break;\r
    default:\r
      return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Read) {\r
    Status = PciIo->Mem.Read (\r
                          PciIo,\r
                          Width,\r
                          BarIndex,\r
                          (UINT64) Offset,\r
                          Count,\r
                          Data\r
                          );\r
  } else {\r
    Status = PciIo->Mem.Write (\r
                          PciIo,\r
                          Width,\r
                          BarIndex,\r
                          (UINT64) Offset,\r
                          Count,\r
                          Data\r
                          );\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] OrData            The pointer to the data used to do OR operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The OR operation succeeds.\r
  @retval Others                The OR operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcOrMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *OrData\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  UINT64                       Data;\r
  UINT64                       Or;\r
\r
  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if (Count == 1) {\r
    Or = *(UINT8*) OrData;\r
  } else if (Count == 2) {\r
    Or = *(UINT16*) OrData;\r
  } else if (Count == 4) {\r
    Or = *(UINT32*) OrData;\r
  } else if (Count == 8) {\r
    Or = *(UINT64*) OrData;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Data  |= Or;\r
  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r
\r
  return Status;\r
}\r
\r
/**\r
  Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] AndData           The pointer to the data used to do AND operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The AND operation succeeds.\r
  @retval Others                The AND operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcAndMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *AndData\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  UINT64                       Data;\r
  UINT64                       And;\r
\r
  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if (Count == 1) {\r
    And = *(UINT8*) AndData;\r
  } else if (Count == 2) {\r
    And = *(UINT16*) AndData;\r
  } else if (Count == 4) {\r
    And = *(UINT32*) AndData;\r
  } else if (Count == 8) {\r
    And = *(UINT64*) AndData;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Data  &= And;\r
  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r
\r
  return Status;\r
}\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  BarIndex      The BAR index of the standard PCI Configuration\r
                            header to use as the base address for the memory\r
                            operation to perform.\r
  @param[in]  Offset        The offset within the selected BAR to start the\r
                            memory operation.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
\r
  @retval EFI_NOT_READY     The MMIO register hasn't set to the expected value.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcCheckMmioSet (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     BarIndex,\r
  IN  UINT32                    Offset,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue\r
  )\r
{\r
  EFI_STATUS            Status;\r
  UINT64                Value;\r
\r
  //\r
  // Access PCI MMIO space to see if the value is the tested one.\r
  //\r
  Value  = 0;\r
  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Value &= MaskValue;\r
\r
  if (Value == TestValue) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  return EFI_NOT_READY;\r
}\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  BarIndex      The BAR index of the standard PCI Configuration\r
                            header to use as the base address for the memory\r
                            operation to perform.\r
  @param[in]  Offset        The offset within the selected BAR to start the\r
                            memory operation.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
  @param[in]  Timeout       The time out value for wait memory set, uses 1\r
                            microsecond as a unit.\r
\r
  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout\r
                            range.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcWaitMmioSet (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     BarIndex,\r
  IN  UINT32                    Offset,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue,\r
  IN  UINT64                    Timeout\r
  )\r
{\r
  EFI_STATUS            Status;\r
  BOOLEAN               InfiniteWait;\r
\r
  if (Timeout == 0) {\r
    InfiniteWait = TRUE;\r
  } else {\r
    InfiniteWait = FALSE;\r
  }\r
\r
  while (InfiniteWait || (Timeout > 0)) {\r
    Status = SdMmcHcCheckMmioSet (\r
               PciIo,\r
               BarIndex,\r
               Offset,\r
               Count,\r
               MaskValue,\r
               TestValue\r
               );\r
    if (Status != EFI_NOT_READY) {\r
      return Status;\r
    }\r
\r
    //\r
    // Stall for 1 microsecond.\r
    //\r
    gBS->Stall (1);\r
\r
    Timeout--;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Get the controller version information from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Version         The buffer to store the version information.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetControllerVersion (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
  OUT    UINT16               *Version\r
  )\r
{\r
  EFI_STATUS                Status;\r
\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  *Version &= 0xFF;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Software reset the specified SD/MMC host controller and enable all interrupts.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The software reset executes successfully.\r
  @retval Others            The software reset fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcReset (\r
  IN SD_MMC_HC_PRIVATE_DATA *Private,\r
  IN UINT8                  Slot\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     SwReset;\r
  EFI_PCI_IO_PROTOCOL       *PciIo;\r
\r
  //\r
  // Notify the SD/MMC override protocol that we are about to reset\r
  // the SD/MMC host controller.\r
  //\r
  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
    Status = mOverride->NotifyPhase (\r
                          Private->ControllerHandle,\r
                          Slot,\r
                          EdkiiSdMmcResetPre,\r
                          NULL);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_WARN,\r
        "%a: SD/MMC pre reset notifier callback failed - %r\n",\r
        __FUNCTION__, Status));\r
      return Status;\r
    }\r
  }\r
\r
  PciIo   = Private->PciIo;\r
  SwReset = BIT0;\r
  Status  = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));\r
    return Status;\r
  }\r
\r
  Status = SdMmcHcWaitMmioSet (\r
             PciIo,\r
             Slot,\r
             SD_MMC_HC_SW_RST,\r
             sizeof (SwReset),\r
             BIT0,\r
             0x00,\r
             SD_MMC_HC_GENERIC_TIMEOUT\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r
    return Status;\r
  }\r
\r
  //\r
  // Enable all interrupt after reset all.\r
  //\r
  Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",\r
      Status));\r
    return Status;\r
  }\r
\r
  //\r
  // Notify the SD/MMC override protocol that we have just reset\r
  // the SD/MMC host controller.\r
  //\r
  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
    Status = mOverride->NotifyPhase (\r
                          Private->ControllerHandle,\r
                          Slot,\r
                          EdkiiSdMmcResetPost,\r
                          NULL);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_WARN,\r
        "%a: SD/MMC post reset notifier callback failed - %r\n",\r
        __FUNCTION__, Status));\r
    }\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcEnableInterrupt (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT16                    IntStatus;\r
\r
  //\r
  // Enable all bits in Error Interrupt Status Enable Register\r
  //\r
  IntStatus = 0xFFFF;\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Enable all bits in Normal Interrupt Status Enable Register\r
  //\r
  IntStatus = 0xFFFF;\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
\r
  return Status;\r
}\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetCapability (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT SD_MMC_HC_SLOT_CAP   *Capability\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT64                    Cap;\r
\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  CopyMem (Capability, &Cap, sizeof (Cap));\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Get the maximum current capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] MaxCurrent      The buffer to store the maximum current capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetMaxCurrent (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT UINT64               *MaxCurrent\r
  )\r
{\r
  EFI_STATUS          Status;\r
\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);\r
\r
  return Status;\r
}\r
\r
/**\r
  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  Slot          The slot number of the SD card to send the command to.\r
  @param[out] MediaPresent  The pointer to the media present boolean value.\r
\r
  @retval EFI_SUCCESS       There is no media change happened.\r
  @retval EFI_MEDIA_CHANGED There is media change happened.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcCardDetect (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
     OUT BOOLEAN            *MediaPresent\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT16                    Data;\r
  UINT32                    PresentState;\r
\r
  //\r
  // Check Present State Register to see if there is a card presented.\r
  //\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if ((PresentState & BIT16) != 0) {\r
    *MediaPresent = TRUE;\r
  } else {\r
    *MediaPresent = FALSE;\r
  }\r
\r
  //\r
  // Check Normal Interrupt Status Register\r
  //\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if ((Data & (BIT6 | BIT7)) != 0) {\r
    //\r
    // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r
    //\r
    Data  &= BIT6 | BIT7;\r
    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    return EFI_MEDIA_CHANGED;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Stop SD/MMC card clock.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.\r
  @retval Others            Fail to stop SD/MMC clock.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcStopClock (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT32                    PresentState;\r
  UINT16                    ClockCtrl;\r
\r
  //\r
  // Ensure no SD transactions are occurring on the SD Bus by\r
  // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r
  // in the Present State register to be 0.\r
  //\r
  Status = SdMmcHcWaitMmioSet (\r
             PciIo,\r
             Slot,\r
             SD_MMC_HC_PRESENT_STATE,\r
             sizeof (PresentState),\r
             BIT0 | BIT1,\r
             0,\r
             SD_MMC_HC_GENERIC_TIMEOUT\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Set SD Clock Enable in the Clock Control register to 0\r
  //\r
  ClockCtrl = (UINT16)~BIT2;\r
  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
  return Status;\r
}\r
\r
/**\r
  SD/MMC card clock supply.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.\r
  @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcClockSupply (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT64                 ClockFreq,\r
  IN UINT32                 BaseClkFreq,\r
  IN UINT16                 ControllerVer\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT32                    SettingFreq;\r
  UINT32                    Divisor;\r
  UINT32                    Remainder;\r
  UINT16                    ClockCtrl;\r
\r
  //\r
  // Calculate a divisor for SD clock frequency\r
  //\r
  ASSERT (BaseClkFreq != 0);\r
\r
  if (ClockFreq == 0) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (ClockFreq > (BaseClkFreq * 1000)) {\r
    ClockFreq = BaseClkFreq * 1000;\r
  }\r
\r
  //\r
  // Calculate the divisor of base frequency.\r
  //\r
  Divisor     = 0;\r
  SettingFreq = BaseClkFreq * 1000;\r
  while (ClockFreq < SettingFreq) {\r
    Divisor++;\r
\r
    SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r
    Remainder   = (BaseClkFreq * 1000) % (2 * Divisor);\r
    if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r
      break;\r
    }\r
    if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r
      SettingFreq ++;\r
    }\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r
\r
  //\r
  // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
  //\r
  if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&\r
      (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {\r
    ASSERT (Divisor <= 0x3FF);\r
    ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
  } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||\r
             (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {\r
    //\r
    // Only the most significant bit can be used as divisor.\r
    //\r
    if (((Divisor - 1) & Divisor) != 0) {\r
      Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r
    }\r
    ASSERT (Divisor <= 0x80);\r
    ClockCtrl = (Divisor & 0xFF) << 8;\r
  } else {\r
    DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Stop bus clock at first\r
  //\r
  Status = SdMmcHcStopClock (PciIo, Slot);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Supply clock frequency with specified divisor\r
  //\r
  ClockCtrl |= BIT0;\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r
    return Status;\r
  }\r
\r
  //\r
  // Wait Internal Clock Stable in the Clock Control register to be 1\r
  //\r
  Status = SdMmcHcWaitMmioSet (\r
             PciIo,\r
             Slot,\r
             SD_MMC_HC_CLOCK_CTRL,\r
             sizeof (ClockCtrl),\r
             BIT1,\r
             BIT1,\r
             SD_MMC_HC_GENERIC_TIMEOUT\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Set SD Clock Enable in the Clock Control register to 1\r
  //\r
  ClockCtrl = BIT2;\r
  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
  return Status;\r
}\r
\r
/**\r
  SD/MMC bus power control.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] PowerCtrl      The value setting to the power control register.\r
\r
  @retval TRUE              There is a SD/MMC card attached.\r
  @retval FALSE             There is no a SD/MMC card attached.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcPowerControl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT8                  PowerCtrl\r
  )\r
{\r
  EFI_STATUS                Status;\r
\r
  //\r
  // Clr SD Bus Power\r
  //\r
  PowerCtrl &= (UINT8)~BIT0;\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
  //\r
  PowerCtrl |= BIT0;\r
  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
\r
  return Status;\r
}\r
\r
/**\r
  Set the SD/MMC bus width.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
\r
  @retval EFI_SUCCESS       The bus width is set successfully.\r
  @retval Others            The bus width isn't set successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcSetBusWidth (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT16                 BusWidth\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     HostCtrl1;\r
\r
  if (BusWidth == 1) {\r
    HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r
    Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
  } else if (BusWidth == 4) {\r
    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    HostCtrl1 |= BIT1;\r
    HostCtrl1 &= (UINT8)~BIT5;\r
    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
  } else if (BusWidth == 8) {\r
    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    HostCtrl1 &= (UINT8)~BIT1;\r
    HostCtrl1 |= BIT5;\r
    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
  } else {\r
    ASSERT (FALSE);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Configure V4 controller enhancements at initialization.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Capability     The capability of the slot.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitV4Enhancements (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_HC_SLOT_CAP     Capability,\r
  IN UINT16                 ControllerVer\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT16                    HostCtrl2;\r
\r
  //\r
  // Check if controller version V4 or higher\r
  //\r
  if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r
    HostCtrl2 = SD_MMC_HC_V4_EN;\r
    //\r
    // Check if V4 64bit support is available\r
    //\r
    if (Capability.SysBus64V4 != 0) {\r
      HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r
      DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r
    }\r
    //\r
    // Check if controller version V4.10 or higher\r
    //\r
    if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {\r
      HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;\r
      DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));\r
    }\r
    Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Supply SD/MMC card with lowest clock frequency at initialization.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitClockFreq (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT32                 BaseClkFreq,\r
  IN UINT16                 ControllerVer\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT32                    InitFreq;\r
\r
  //\r
  // According to SDHCI specification ver. 4.2, BaseClkFreq field value of\r
  // the Capability Register 1 can be zero, which means a need for obtaining\r
  // the clock frequency via another method. Fail in case it is not updated\r
  // by SW at this point.\r
  //\r
  if (BaseClkFreq == 0) {\r
    //\r
    // Don't support get Base Clock Frequency information via another method\r
    //\r
    return EFI_UNSUPPORTED;\r
  }\r
  //\r
  // Supply 400KHz clock frequency at initialization phase.\r
  //\r
  InitFreq = 400;\r
  Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);\r
  return Status;\r
}\r
\r
/**\r
  Supply SD/MMC card with maximum voltage at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Capability     The capability of the slot.\r
\r
  @retval EFI_SUCCESS       The voltage is supplied successfully.\r
  @retval Others            The voltage isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitPowerVoltage (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_HC_SLOT_CAP     Capability\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     MaxVoltage;\r
  UINT8                     HostCtrl2;\r
\r
  //\r
  // Calculate supported maximum voltage according to SD Bus Voltage Select\r
  //\r
  if (Capability.Voltage33 != 0) {\r
    //\r
    // Support 3.3V\r
    //\r
    MaxVoltage = 0x0E;\r
  } else if (Capability.Voltage30 != 0) {\r
    //\r
    // Support 3.0V\r
    //\r
    MaxVoltage = 0x0C;\r
  } else if (Capability.Voltage18 != 0) {\r
    //\r
    // Support 1.8V\r
    //\r
    MaxVoltage = 0x0A;\r
    HostCtrl2  = BIT3;\r
    Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
    gBS->Stall (5000);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  } else {\r
    ASSERT (FALSE);\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
  //\r
  Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);\r
\r
  return Status;\r
}\r
\r
/**\r
  Initialize the Timeout Control register with most conservative value at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The timeout control register is configured successfully.\r
  @retval Others            The timeout control register isn't configured successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitTimeoutCtrl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     Timeout;\r
\r
  Timeout = 0x0E;\r
  Status  = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r
\r
  return Status;\r
}\r
\r
/**\r
  Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r
  at initialization.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The host controller is initialized successfully.\r
  @retval Others            The host controller isn't initialized successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitHost (\r
  IN SD_MMC_HC_PRIVATE_DATA *Private,\r
  IN UINT8                  Slot\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EFI_PCI_IO_PROTOCOL       *PciIo;\r
  SD_MMC_HC_SLOT_CAP        Capability;\r
\r
  //\r
  // Notify the SD/MMC override protocol that we are about to initialize\r
  // the SD/MMC host controller.\r
  //\r
  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
    Status = mOverride->NotifyPhase (\r
                          Private->ControllerHandle,\r
                          Slot,\r
                          EdkiiSdMmcInitHostPre,\r
                          NULL);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_WARN,\r
        "%a: SD/MMC pre init notifier callback failed - %r\n",\r
        __FUNCTION__, Status));\r
      return Status;\r
    }\r
  }\r
\r
  PciIo = Private->PciIo;\r
  Capability = Private->Capability[Slot];\r
\r
  Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Notify the SD/MMC override protocol that we are have just initialized\r
  // the SD/MMC host controller.\r
  //\r
  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
    Status = mOverride->NotifyPhase (\r
                          Private->ControllerHandle,\r
                          Slot,\r
                          EdkiiSdMmcInitHostPost,\r
                          NULL);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_WARN,\r
        "%a: SD/MMC post init notifier callback failed - %r\n",\r
        __FUNCTION__, Status));\r
    }\r
  }\r
  return Status;\r
}\r
\r
/**\r
  Set SD Host Controler control 2 registry according to selected speed.\r
\r
  @param[in] ControllerHandle The handle of the controller.\r
  @param[in] PciIo            The PCI IO protocol instance.\r
  @param[in] Slot             The slot number of the SD card to send the command to.\r
  @param[in] Timing           The timing to select.\r
\r
  @retval EFI_SUCCESS         The timing is set successfully.\r
  @retval Others              The timing isn't set successfully.\r
**/\r
EFI_STATUS\r
SdMmcHcUhsSignaling (\r
  IN EFI_HANDLE             ControllerHandle,\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_BUS_MODE        Timing\r
  )\r
{\r
  EFI_STATUS                 Status;\r
  UINT8                      HostCtrl2;\r
\r
  HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;\r
  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  switch (Timing) {\r
    case SdMmcUhsSdr12:\r
      HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;\r
      break;\r
    case SdMmcUhsSdr25:\r
      HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;\r
      break;\r
    case SdMmcUhsSdr50:\r
      HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;\r
      break;\r
    case SdMmcUhsSdr104:\r
      HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;\r
      break;\r
    case SdMmcUhsDdr50:\r
      HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;\r
      break;\r
    case SdMmcMmcLegacy:\r
      HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;\r
      break;\r
    case SdMmcMmcHsSdr:\r
      HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;\r
      break;\r
    case SdMmcMmcHsDdr:\r
      HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;\r
      break;\r
    case SdMmcMmcHs200:\r
      HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;\r
      break;\r
    case SdMmcMmcHs400:\r
      HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;\r
      break;\r
    default:\r
     HostCtrl2 = 0;\r
     break;\r
  }\r
  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
    Status = mOverride->NotifyPhase (\r
                          ControllerHandle,\r
                          Slot,\r
                          EdkiiSdMmcUhsSignaling,\r
                          &Timing\r
                          );\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((\r
        DEBUG_ERROR,\r
        "%a: SD/MMC uhs signaling notifier callback failed - %r\n",\r
        __FUNCTION__,\r
        Status\r
        ));\r
      return Status;\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Turn on/off LED.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] On             The boolean to turn on/off LED.\r
\r
  @retval EFI_SUCCESS       The LED is turned on/off successfully.\r
  @retval Others            The LED isn't turned on/off successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcLedOnOff (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN BOOLEAN                On\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     HostCtrl1;\r
\r
  if (On) {\r
    HostCtrl1 = BIT0;\r
    Status    = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
  } else {\r
    HostCtrl1 = (UINT8)~BIT0;\r
    Status    = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Build ADMA descriptor table for transfer.\r
\r
  Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.\r
\r
  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The ADMA descriptor table is created successfully.\r
  @retval Others            The ADMA descriptor table isn't created successfully.\r
\r
**/\r
EFI_STATUS\r
BuildAdmaDescTable (\r
  IN SD_MMC_HC_TRB          *Trb,\r
  IN UINT16                 ControllerVer\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS      Data;\r
  UINT64                    DataLen;\r
  UINT64                    Entries;\r
  UINT32                    Index;\r
  UINT64                    Remaining;\r
  UINT64                    Address;\r
  UINTN                     TableSize;\r
  EFI_PCI_IO_PROTOCOL       *PciIo;\r
  EFI_STATUS                Status;\r
  UINTN                     Bytes;\r
  BOOLEAN                   AddressingMode64;\r
  BOOLEAN                   DataLength26;\r
  UINT32                    AdmaMaxDataPerLine;\r
  UINT32                    DescSize;\r
  VOID                      *AdmaDesc;\r
\r
  AddressingMode64   = FALSE;\r
  DataLength26       = FALSE;\r
  AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;\r
  DescSize           = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);\r
  AdmaDesc           = NULL;\r
\r
  Data    = Trb->DataPhy;\r
  DataLen = Trb->DataLen;\r
  PciIo   = Trb->Private->PciIo;\r
\r
  //\r
  // Detect whether 64bit addressing is supported.\r
  //\r
  if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r
    Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r
                                 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);\r
    if (!EFI_ERROR (Status)) {\r
      AddressingMode64 = TRUE;\r
      DescSize = sizeof (SD_MMC_HC_ADMA_64_DESC_LINE);\r
    }\r
  }\r
  //\r
  // Check for valid ranges in 32bit ADMA Descriptor Table\r
  //\r
  if (!AddressingMode64 &&\r
      ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  //\r
  // Check address field alignment\r
  //\r
  if (AddressingMode64) {\r
    //\r
    // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)\r
    //\r
    if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {\r
      DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));\r
    }\r
  } else {\r
    //\r
    // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
    //\r
    if ((Data & (BIT0 | BIT1)) != 0) {\r
      DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r
    }\r
  }\r
  //\r
  // Detect whether 26bit data length is supported.\r
  //\r
  Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r
                               SD_MMC_HC_26_DATA_LEN_ADMA_EN, SD_MMC_HC_26_DATA_LEN_ADMA_EN);\r
  if (!EFI_ERROR (Status)) {\r
    DataLength26 = TRUE;\r
    AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;\r
  }\r
\r
  Entries   = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);\r
  TableSize = (UINTN)MultU64x32 (Entries, DescSize);\r
  Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r
  Status = PciIo->AllocateBuffer (\r
                    PciIo,\r
                    AllocateAnyPages,\r
                    EfiBootServicesData,\r
                    EFI_SIZE_TO_PAGES (TableSize),\r
                    (VOID **)&AdmaDesc,\r
                    0\r
                    );\r
  if (EFI_ERROR (Status)) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
  ZeroMem (AdmaDesc, TableSize);\r
  Bytes  = TableSize;\r
  Status = PciIo->Map (\r
                    PciIo,\r
                    EfiPciIoOperationBusMasterCommonBuffer,\r
                    AdmaDesc,\r
                    &Bytes,\r
                    &Trb->AdmaDescPhy,\r
                    &Trb->AdmaMap\r
                    );\r
\r
  if (EFI_ERROR (Status) || (Bytes != TableSize)) {\r
    //\r
    // Map error or unable to map the whole RFis buffer into a contiguous region.\r
    //\r
    PciIo->FreeBuffer (\r
             PciIo,\r
             EFI_SIZE_TO_PAGES (TableSize),\r
             AdmaDesc\r
             );\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  if ((!AddressingMode64) &&\r
      (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r
    //\r
    // The ADMA doesn't support 64bit addressing.\r
    //\r
    PciIo->Unmap (\r
      PciIo,\r
      Trb->AdmaMap\r
    );\r
    PciIo->FreeBuffer (\r
      PciIo,\r
      EFI_SIZE_TO_PAGES (TableSize),\r
      AdmaDesc\r
    );\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  Remaining = DataLen;\r
  Address   = Data;\r
  if (!AddressingMode64) {\r
    Trb->Adma32Desc = AdmaDesc;\r
    Trb->Adma64Desc = NULL;\r
  } else {\r
    Trb->Adma64Desc = AdmaDesc;\r
    Trb->Adma32Desc = NULL;\r
  }\r
  for (Index = 0; Index < Entries; Index++) {\r
    if (!AddressingMode64) {\r
      if (Remaining <= AdmaMaxDataPerLine) {\r
        Trb->Adma32Desc[Index].Valid = 1;\r
        Trb->Adma32Desc[Index].Act   = 2;\r
        if (DataLength26) {\r
          Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r
        }\r
        Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r
        Trb->Adma32Desc[Index].Address = (UINT32)Address;\r
        break;\r
      } else {\r
        Trb->Adma32Desc[Index].Valid = 1;\r
        Trb->Adma32Desc[Index].Act   = 2;\r
        if (DataLength26) {\r
          Trb->Adma32Desc[Index].UpperLength  = 0;\r
        }\r
        Trb->Adma32Desc[Index].LowerLength  = 0;\r
        Trb->Adma32Desc[Index].Address = (UINT32)Address;\r
      }\r
    } else {\r
      if (Remaining <= AdmaMaxDataPerLine) {\r
        Trb->Adma64Desc[Index].Valid = 1;\r
        Trb->Adma64Desc[Index].Act   = 2;\r
        if (DataLength26) {\r
          Trb->Adma64Desc[Index].UpperLength  = (UINT16)RShiftU64 (Remaining, 16);\r
        }\r
        Trb->Adma64Desc[Index].LowerLength  = (UINT16)(Remaining & MAX_UINT16);\r
        Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;\r
        Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r
        break;\r
      } else {\r
        Trb->Adma64Desc[Index].Valid = 1;\r
        Trb->Adma64Desc[Index].Act   = 2;\r
        if (DataLength26) {\r
          Trb->Adma64Desc[Index].UpperLength  = 0;\r
        }\r
        Trb->Adma64Desc[Index].LowerLength  = 0;\r
        Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;\r
        Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r
      }\r
    }\r
\r
    Remaining -= AdmaMaxDataPerLine;\r
    Address   += AdmaMaxDataPerLine;\r
  }\r
\r
  //\r
  // Set the last descriptor line as end of descriptor table\r
  //\r
  AddressingMode64 ? (Trb->Adma64Desc[Index].End = 1) : (Trb->Adma32Desc[Index].End = 1);\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Create a new TRB for the SD/MMC cmd request.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Packet         A pointer to the SD command data structure.\r
  @param[in] Event          If Event is NULL, blocking I/O is performed. If Event is\r
                            not NULL, then nonblocking I/O is performed, and Event\r
                            will be signaled when the Packet completes.\r
\r
  @return Created Trb or NULL.\r
\r
**/\r
SD_MMC_HC_TRB *\r
SdMmcCreateTrb (\r
  IN SD_MMC_HC_PRIVATE_DATA              *Private,\r
  IN UINT8                               Slot,\r
  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r
  IN EFI_EVENT                           Event\r
  )\r
{\r
  SD_MMC_HC_TRB                 *Trb;\r
  EFI_STATUS                    Status;\r
  EFI_TPL                       OldTpl;\r
  EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
  EFI_PCI_IO_PROTOCOL           *PciIo;\r
  UINTN                         MapLength;\r
\r
  Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));\r
  if (Trb == NULL) {\r
    return NULL;\r
  }\r
\r
  Trb->Signature = SD_MMC_HC_TRB_SIG;\r
  Trb->Slot      = Slot;\r
  Trb->BlockSize = 0x200;\r
  Trb->Packet    = Packet;\r
  Trb->Event     = Event;\r
  Trb->Started   = FALSE;\r
  Trb->Timeout   = Packet->Timeout;\r
  Trb->Private   = Private;\r
\r
  if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r
    Trb->Data    = Packet->InDataBuffer;\r
    Trb->DataLen = Packet->InTransferLength;\r
    Trb->Read    = TRUE;\r
  } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r
    Trb->Data    = Packet->OutDataBuffer;\r
    Trb->DataLen = Packet->OutTransferLength;\r
    Trb->Read    = FALSE;\r
  } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r
    Trb->Data    = NULL;\r
    Trb->DataLen = 0;\r
  } else {\r
    goto Error;\r
  }\r
\r
  if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r
    Trb->BlockSize = (UINT16)Trb->DataLen;\r
  }\r
\r
  if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r
       (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r
      ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r
       (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r
    Trb->Mode = SdMmcPioMode;\r
  } else {\r
    if (Trb->Read) {\r
      Flag = EfiPciIoOperationBusMasterWrite;\r
    } else {\r
      Flag = EfiPciIoOperationBusMasterRead;\r
    }\r
\r
    PciIo = Private->PciIo;\r
    if (Trb->DataLen != 0) {\r
      MapLength = Trb->DataLen;\r
      Status = PciIo->Map (\r
                        PciIo,\r
                        Flag,\r
                        Trb->Data,\r
                        &MapLength,\r
                        &Trb->DataPhy,\r
                        &Trb->DataMap\r
                        );\r
      if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {\r
        Status = EFI_BAD_BUFFER_SIZE;\r
        goto Error;\r
      }\r
    }\r
\r
    if (Trb->DataLen == 0) {\r
      Trb->Mode = SdMmcNoData;\r
    } else if (Private->Capability[Slot].Adma2 != 0) {\r
      Trb->Mode = SdMmcAdmaMode;\r
      Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);\r
      if (EFI_ERROR (Status)) {\r
        PciIo->Unmap (PciIo, Trb->DataMap);\r
        goto Error;\r
      }\r
    } else if (Private->Capability[Slot].Sdma != 0) {\r
      Trb->Mode = SdMmcSdmaMode;\r
    } else {\r
      Trb->Mode = SdMmcPioMode;\r
    }\r
  }\r
\r
  if (Event != NULL) {\r
    OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
    InsertTailList (&Private->Queue, &Trb->TrbList);\r
    gBS->RestoreTPL (OldTpl);\r
  }\r
\r
  return Trb;\r
\r
Error:\r
  SdMmcFreeTrb (Trb);\r
  return NULL;\r
}\r
\r
/**\r
  Free the resource used by the TRB.\r
\r
  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.\r
\r
**/\r
VOID\r
SdMmcFreeTrb (\r
  IN SD_MMC_HC_TRB           *Trb\r
  )\r
{\r
  EFI_PCI_IO_PROTOCOL        *PciIo;\r
\r
  PciIo = Trb->Private->PciIo;\r
\r
  if (Trb->AdmaMap != NULL) {\r
    PciIo->Unmap (\r
      PciIo,\r
      Trb->AdmaMap\r
    );\r
  }\r
  if (Trb->Adma32Desc != NULL) {\r
    PciIo->FreeBuffer (\r
      PciIo,\r
      Trb->AdmaPages,\r
      Trb->Adma32Desc\r
    );\r
  }\r
  if (Trb->Adma64Desc != NULL) {\r
    PciIo->FreeBuffer (\r
      PciIo,\r
      Trb->AdmaPages,\r
      Trb->Adma64Desc\r
    );\r
  }\r
  if (Trb->DataMap != NULL) {\r
    PciIo->Unmap (\r
      PciIo,\r
      Trb->DataMap\r
    );\r
  }\r
  FreePool (Trb);\r
  return;\r
}\r
\r
/**\r
  Check if the env is ready for execute specified TRB.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The env is ready for TRB execution.\r
  @retval EFI_NOT_READY     The env is not ready for TRB execution.\r
  @retval Others            Some erros happen.\r
\r
**/\r
EFI_STATUS\r
SdMmcCheckTrbEnv (\r
  IN SD_MMC_HC_PRIVATE_DATA           *Private,\r
  IN SD_MMC_HC_TRB                    *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
  EFI_PCI_IO_PROTOCOL                 *PciIo;\r
  UINT32                              PresentState;\r
\r
  Packet = Trb->Packet;\r
\r
  if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r
      (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r
      (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {\r
    //\r
    // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r
    // the Present State register to be 0\r
    //\r
    PresentState = BIT0 | BIT1;\r
  } else {\r
    //\r
    // Wait Command Inhibit (CMD) in the Present State register\r
    // to be 0\r
    //\r
    PresentState = BIT0;\r
  }\r
\r
  PciIo  = Private->PciIo;\r
  Status = SdMmcHcCheckMmioSet (\r
             PciIo,\r
             Trb->Slot,\r
             SD_MMC_HC_PRESENT_STATE,\r
             sizeof (PresentState),\r
             PresentState,\r
             0\r
             );\r
\r
  return Status;\r
}\r
\r
/**\r
  Wait for the env to be ready for execute specified TRB.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The env is ready for TRB execution.\r
  @retval EFI_TIMEOUT       The env is not ready for TRB execution in time.\r
  @retval Others            Some erros happen.\r
\r
**/\r
EFI_STATUS\r
SdMmcWaitTrbEnv (\r
  IN SD_MMC_HC_PRIVATE_DATA           *Private,\r
  IN SD_MMC_HC_TRB                    *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
  UINT64                              Timeout;\r
  BOOLEAN                             InfiniteWait;\r
\r
  //\r
  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
  //\r
  Packet  = Trb->Packet;\r
  Timeout = Packet->Timeout;\r
  if (Timeout == 0) {\r
    InfiniteWait = TRUE;\r
  } else {\r
    InfiniteWait = FALSE;\r
  }\r
\r
  while (InfiniteWait || (Timeout > 0)) {\r
    //\r
    // Check Trb execution result by reading Normal Interrupt Status register.\r
    //\r
    Status = SdMmcCheckTrbEnv (Private, Trb);\r
    if (Status != EFI_NOT_READY) {\r
      return Status;\r
    }\r
    //\r
    // Stall for 1 microsecond.\r
    //\r
    gBS->Stall (1);\r
\r
    Timeout--;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Execute the specified TRB.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The TRB is sent to host controller successfully.\r
  @retval Others            Some erros happen when sending this request to the host controller.\r
\r
**/\r
EFI_STATUS\r
SdMmcExecTrb (\r
  IN SD_MMC_HC_PRIVATE_DATA           *Private,\r
  IN SD_MMC_HC_TRB                    *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
  EFI_PCI_IO_PROTOCOL                 *PciIo;\r
  UINT16                              Cmd;\r
  UINT16                              IntStatus;\r
  UINT32                              Argument;\r
  UINT32                              BlkCount;\r
  UINT16                              BlkSize;\r
  UINT16                              TransMode;\r
  UINT8                               HostCtrl1;\r
  UINT64                              SdmaAddr;\r
  UINT64                              AdmaAddr;\r
  BOOLEAN                             AddressingMode64;\r
\r
  AddressingMode64 = FALSE;\r
\r
  Packet = Trb->Packet;\r
  PciIo  = Trb->Private->PciIo;\r
  //\r
  // Clear all bits in Error Interrupt Status Register\r
  //\r
  IntStatus = 0xFFFF;\r
  Status    = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.\r
  //\r
  IntStatus = 0xFF3F;\r
  Status    = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set Host Control 1 register DMA Select field\r
  //\r
  if (Trb->Mode == SdMmcAdmaMode) {\r
    HostCtrl1 = BIT4;\r
    Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r
\r
  if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
    Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r
                                 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);\r
    if (!EFI_ERROR (Status)) {\r
      AddressingMode64 = TRUE;\r
    }\r
  }\r
\r
  if (Trb->Mode == SdMmcSdmaMode) {\r
    if ((!AddressingMode64) &&\r
        ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;\r
\r
    if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
      Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);\r
    } else {\r
      Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);\r
    }\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  } else if (Trb->Mode == SdMmcAdmaMode) {\r
    AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;\r
    Status   = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  BlkSize = Trb->BlockSize;\r
  if (Trb->Mode == SdMmcSdmaMode) {\r
    //\r
    // Set SDMA boundary to be 512K bytes.\r
    //\r
    BlkSize |= 0x7000;\r
  }\r
\r
  Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  BlkCount = 0;\r
  if (Trb->Mode != SdMmcNoData) {\r
    //\r
    // Calcuate Block Count.\r
    //\r
    BlkCount = (Trb->DataLen / Trb->BlockSize);\r
  }\r
  if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {\r
    Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);\r
  } else {\r
    Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);\r
  }\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Argument = Packet->SdMmcCmdBlk->CommandArgument;\r
  Status   = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  TransMode = 0;\r
  if (Trb->Mode != SdMmcNoData) {\r
    if (Trb->Mode != SdMmcPioMode) {\r
      TransMode |= BIT0;\r
    }\r
    if (Trb->Read) {\r
      TransMode |= BIT4;\r
    }\r
    if (BlkCount > 1) {\r
      TransMode |= BIT5 | BIT1;\r
    }\r
    //\r
    // Only SD memory card needs to use AUTO CMD12 feature.\r
    //\r
    if (Private->Slot[Trb->Slot].CardType == SdCardType) {\r
      if (BlkCount > 1) {\r
        TransMode |= BIT2;\r
      }\r
    }\r
  }\r
\r
  Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);\r
  if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {\r
    Cmd |= BIT5;\r
  }\r
  //\r
  // Convert ResponseType to value\r
  //\r
  if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r
    switch (Packet->SdMmcCmdBlk->ResponseType) {\r
      case SdMmcResponseTypeR1:\r
      case SdMmcResponseTypeR5:\r
      case SdMmcResponseTypeR6:\r
      case SdMmcResponseTypeR7:\r
        Cmd |= (BIT1 | BIT3 | BIT4);\r
        break;\r
      case SdMmcResponseTypeR2:\r
        Cmd |= (BIT0 | BIT3);\r
       break;\r
      case SdMmcResponseTypeR3:\r
      case SdMmcResponseTypeR4:\r
        Cmd |= BIT1;\r
        break;\r
      case SdMmcResponseTypeR1b:\r
      case SdMmcResponseTypeR5b:\r
        Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r
        break;\r
      default:\r
        ASSERT (FALSE);\r
        break;\r
    }\r
  }\r
  //\r
  // Execute cmd\r
  //\r
  Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r
  return Status;\r
}\r
\r
/**\r
  Check the TRB execution result.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The TRB is executed successfully.\r
  @retval EFI_NOT_READY     The TRB is not completed for execution.\r
  @retval Others            Some erros happen when executing this request.\r
\r
**/\r
EFI_STATUS\r
SdMmcCheckTrbResult (\r
  IN SD_MMC_HC_PRIVATE_DATA           *Private,\r
  IN SD_MMC_HC_TRB                    *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
  UINT16                              IntStatus;\r
  UINT32                              Response[4];\r
  UINT64                              SdmaAddr;\r
  UINT8                               Index;\r
  UINT8                               SwReset;\r
  UINT32                              PioLength;\r
\r
  SwReset = 0;\r
  Packet  = Trb->Packet;\r
  //\r
  // Check Trb execution result by reading Normal Interrupt Status register.\r
  //\r
  Status = SdMmcHcRwMmio (\r
             Private->PciIo,\r
             Trb->Slot,\r
             SD_MMC_HC_NOR_INT_STS,\r
             TRUE,\r
             sizeof (IntStatus),\r
             &IntStatus\r
             );\r
  if (EFI_ERROR (Status)) {\r
    goto Done;\r
  }\r
  //\r
  // Check Transfer Complete bit is set or not.\r
  //\r
  if ((IntStatus & BIT1) == BIT1) {\r
    if ((IntStatus & BIT15) == BIT15) {\r
      //\r
      // Read Error Interrupt Status register to check if the error is\r
      // Data Timeout Error.\r
      // If yes, treat it as success as Transfer Complete has higher\r
      // priority than Data Timeout Error.\r
      //\r
      Status = SdMmcHcRwMmio (\r
                 Private->PciIo,\r
                 Trb->Slot,\r
                 SD_MMC_HC_ERR_INT_STS,\r
                 TRUE,\r
                 sizeof (IntStatus),\r
                 &IntStatus\r
                 );\r
      if (!EFI_ERROR (Status)) {\r
        if ((IntStatus & BIT4) == BIT4) {\r
          Status = EFI_SUCCESS;\r
        } else {\r
          Status = EFI_DEVICE_ERROR;\r
        }\r
      }\r
    }\r
\r
    goto Done;\r
  }\r
  //\r
  // Check if there is a error happened during cmd execution.\r
  // If yes, then do error recovery procedure to follow SD Host Controller\r
  // Simplified Spec 3.0 section 3.10.1.\r
  //\r
  if ((IntStatus & BIT15) == BIT15) {\r
    Status = SdMmcHcRwMmio (\r
               Private->PciIo,\r
               Trb->Slot,\r
               SD_MMC_HC_ERR_INT_STS,\r
               TRUE,\r
               sizeof (IntStatus),\r
               &IntStatus\r
               );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
    if ((IntStatus & 0x0F) != 0) {\r
      SwReset |= BIT1;\r
    }\r
    if ((IntStatus & 0xF0) != 0) {\r
      SwReset |= BIT2;\r
    }\r
\r
    Status  = SdMmcHcRwMmio (\r
                Private->PciIo,\r
                Trb->Slot,\r
                SD_MMC_HC_SW_RST,\r
                FALSE,\r
                sizeof (SwReset),\r
                &SwReset\r
                );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
    Status = SdMmcHcWaitMmioSet (\r
               Private->PciIo,\r
               Trb->Slot,\r
               SD_MMC_HC_SW_RST,\r
               sizeof (SwReset),\r
               0xFF,\r
               0,\r
               SD_MMC_HC_GENERIC_TIMEOUT\r
               );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
\r
    Status = EFI_DEVICE_ERROR;\r
    goto Done;\r
  }\r
  //\r
  // Check if DMA interrupt is signalled for the SDMA transfer.\r
  //\r
  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r
    //\r
    // Clear DMA interrupt bit.\r
    //\r
    IntStatus = BIT3;\r
    Status    = SdMmcHcRwMmio (\r
                  Private->PciIo,\r
                  Trb->Slot,\r
                  SD_MMC_HC_NOR_INT_STS,\r
                  FALSE,\r
                  sizeof (IntStatus),\r
                  &IntStatus\r
                  );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
    //\r
    // Update SDMA Address register.\r
    //\r
    SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r
\r
    if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
      Status = SdMmcHcRwMmio (\r
                 Private->PciIo,\r
                 Trb->Slot,\r
                 SD_MMC_HC_ADMA_SYS_ADDR,\r
                 FALSE,\r
                 sizeof (UINT64),\r
                 &SdmaAddr\r
                 );\r
    } else {\r
      Status = SdMmcHcRwMmio (\r
                 Private->PciIo,\r
                 Trb->Slot,\r
                 SD_MMC_HC_SDMA_ADDR,\r
                 FALSE,\r
                 sizeof (UINT32),\r
                 &SdmaAddr\r
                 );\r
    }\r
\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
    Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;\r
  }\r
\r
  if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&\r
      (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&\r
      (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {\r
    if ((IntStatus & BIT0) == BIT0) {\r
      Status = EFI_SUCCESS;\r
      goto Done;\r
    }\r
  }\r
\r
  if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r
       (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r
      ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r
       (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r
    //\r
    // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,\r
    // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.\r
    // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.\r
    //\r
    if ((IntStatus & BIT5) == BIT5) {\r
      //\r
      // Clear Buffer Read Ready interrupt at first.\r
      //\r
      IntStatus = BIT5;\r
      SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
      //\r
      // Read data out from Buffer Port register\r
      //\r
      for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {\r
        SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);\r
      }\r
      Status = EFI_SUCCESS;\r
      goto Done;\r
    }\r
  }\r
\r
  Status = EFI_NOT_READY;\r
Done:\r
  //\r
  // Get response data when the cmd is executed successfully.\r
  //\r
  if (!EFI_ERROR (Status)) {\r
    if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r
      for (Index = 0; Index < 4; Index++) {\r
        Status = SdMmcHcRwMmio (\r
                   Private->PciIo,\r
                   Trb->Slot,\r
                   SD_MMC_HC_RESPONSE + Index * 4,\r
                   TRUE,\r
                   sizeof (UINT32),\r
                   &Response[Index]\r
                   );\r
        if (EFI_ERROR (Status)) {\r
          SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r
          return Status;\r
        }\r
      }\r
      CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));\r
    }\r
  }\r
\r
  if (Status != EFI_NOT_READY) {\r
    SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Wait for the TRB execution result.\r
\r
  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The TRB is executed successfully.\r
  @retval Others            Some erros happen when executing this request.\r
\r
**/\r
EFI_STATUS\r
SdMmcWaitTrbResult (\r
  IN SD_MMC_HC_PRIVATE_DATA           *Private,\r
  IN SD_MMC_HC_TRB                    *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
  UINT64                              Timeout;\r
  BOOLEAN                             InfiniteWait;\r
\r
  Packet = Trb->Packet;\r
  //\r
  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
  //\r
  Timeout = Packet->Timeout;\r
  if (Timeout == 0) {\r
    InfiniteWait = TRUE;\r
  } else {\r
    InfiniteWait = FALSE;\r
  }\r
\r
  while (InfiniteWait || (Timeout > 0)) {\r
    //\r
    // Check Trb execution result by reading Normal Interrupt Status register.\r
    //\r
    Status = SdMmcCheckTrbResult (Private, Trb);\r
    if (Status != EFI_NOT_READY) {\r
      return Status;\r
    }\r
    //\r
    // Stall for 1 microsecond.\r
    //\r
    gBS->Stall (1);\r
\r
    Timeout--;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r