[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.h

/** @file\r
\r
  Provides some data structure definitions used by the SD/MMC host controller driver.\r
\r
Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _SD_MMC_PCI_HCI_H_\r
#define _SD_MMC_PCI_HCI_H_\r
\r
//\r
// SD Host Controller SlotInfo Register Offset\r
//\r
#define SD_MMC_HC_SLOT_OFFSET         0x40\r
\r
#define SD_MMC_HC_MAX_SLOT            6\r
\r
//\r
// SD Host Controller MMIO Register Offset\r
//\r
#define SD_MMC_HC_SDMA_ADDR           0x00\r
#define SD_MMC_HC_ARG2                0x00\r
#define SD_MMC_HC_BLK_SIZE            0x04\r
#define SD_MMC_HC_BLK_COUNT           0x06\r
#define SD_MMC_HC_ARG1                0x08\r
#define SD_MMC_HC_TRANS_MOD           0x0C\r
#define SD_MMC_HC_COMMAND             0x0E\r
#define SD_MMC_HC_RESPONSE            0x10\r
#define SD_MMC_HC_BUF_DAT_PORT        0x20\r
#define SD_MMC_HC_PRESENT_STATE       0x24\r
#define SD_MMC_HC_HOST_CTRL1          0x28\r
#define SD_MMC_HC_POWER_CTRL          0x29\r
#define SD_MMC_HC_BLK_GAP_CTRL        0x2A\r
#define SD_MMC_HC_WAKEUP_CTRL         0x2B\r
#define SD_MMC_HC_CLOCK_CTRL          0x2C\r
#define SD_MMC_HC_TIMEOUT_CTRL        0x2E\r
#define SD_MMC_HC_SW_RST              0x2F\r
#define SD_MMC_HC_NOR_INT_STS         0x30\r
#define SD_MMC_HC_ERR_INT_STS         0x32\r
#define SD_MMC_HC_NOR_INT_STS_EN      0x34\r
#define SD_MMC_HC_ERR_INT_STS_EN      0x36\r
#define SD_MMC_HC_NOR_INT_SIG_EN      0x38\r
#define SD_MMC_HC_ERR_INT_SIG_EN      0x3A\r
#define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C\r
#define SD_MMC_HC_HOST_CTRL2          0x3E\r
#define SD_MMC_HC_CAP                 0x40\r
#define SD_MMC_HC_MAX_CURRENT_CAP     0x48\r
#define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50\r
#define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52\r
#define SD_MMC_HC_ADMA_ERR_STS        0x54\r
#define SD_MMC_HC_ADMA_SYS_ADDR       0x58\r
#define SD_MMC_HC_PRESET_VAL          0x60\r
#define SD_MMC_HC_SHARED_BUS_CTRL     0xE0\r
#define SD_MMC_HC_SLOT_INT_STS        0xFC\r
#define SD_MMC_HC_CTRL_VER            0xFE\r
\r
//\r
// SD Host Controller bits to HOST_CTRL2 register\r
//\r
#define SD_MMC_HC_CTRL_UHS_MASK       0x0007\r
#define SD_MMC_HC_CTRL_UHS_SDR12      0x0000\r
#define SD_MMC_HC_CTRL_UHS_SDR25      0x0001\r
#define SD_MMC_HC_CTRL_UHS_SDR50      0x0002\r
#define SD_MMC_HC_CTRL_UHS_SDR104     0x0003\r
#define SD_MMC_HC_CTRL_UHS_DDR50      0x0004\r
#define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000\r
#define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001\r
#define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004\r
#define SD_MMC_HC_CTRL_MMC_HS200      0x0003\r
#define SD_MMC_HC_CTRL_MMC_HS400      0x0005\r
\r
//\r
// The transfer modes supported by SD Host Controller\r
//\r
typedef enum {\r
  SdMmcNoData,\r
  SdMmcPioMode,\r
  SdMmcSdmaMode,\r
  SdMmcAdma32bMode,\r
  SdMmcAdma64bV3Mode,\r
  SdMmcAdma64bV4Mode\r
} SD_MMC_HC_TRANSFER_MODE;\r
\r
//\r
// The ADMA transfer lengths supported by SD Host Controller\r
//\r
typedef enum {\r
  SdMmcAdmaLen16b,\r
  SdMmcAdmaLen26b\r
} SD_MMC_HC_ADMA_LENGTH_MODE;\r
\r
//\r
// The maximum data length of each descriptor line\r
//\r
#define ADMA_MAX_DATA_PER_LINE_16B     SIZE_64KB\r
#define ADMA_MAX_DATA_PER_LINE_26B     SIZE_64MB\r
\r
//\r
// ADMA descriptor for 32b addressing.\r
//\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 Address;\r
} SD_MMC_HC_ADMA_32_DESC_LINE;\r
\r
//\r
// ADMA descriptor for 64b addressing.\r
//\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 LowerAddress;\r
  UINT32 UpperAddress;\r
} SD_MMC_HC_ADMA_64_V3_DESC_LINE;\r
\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 LowerAddress;\r
  UINT32 UpperAddress;\r
  UINT32 Reserved1;\r
} SD_MMC_HC_ADMA_64_V4_DESC_LINE;\r
\r
#define SD_MMC_SDMA_BOUNDARY          512 * 1024\r
#define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))\r
\r
typedef struct {\r
  UINT8    FirstBar:3;        // bit 0:2\r
  UINT8    Reserved:1;        // bit 3\r
  UINT8    SlotNum:3;         // bit 4:6\r
  UINT8    Reserved1:1;       // bit 7\r
} SD_MMC_HC_SLOT_INFO;\r
\r
typedef struct {\r
  UINT32   TimeoutFreq:6;     // bit 0:5\r
  UINT32   Reserved:1;        // bit 6\r
  UINT32   TimeoutUnit:1;     // bit 7\r
  UINT32   BaseClkFreq:8;     // bit 8:15\r
  UINT32   MaxBlkLen:2;       // bit 16:17\r
  UINT32   BusWidth8:1;       // bit 18\r
  UINT32   Adma2:1;           // bit 19\r
  UINT32   Reserved2:1;       // bit 20\r
  UINT32   HighSpeed:1;       // bit 21\r
  UINT32   Sdma:1;            // bit 22\r
  UINT32   SuspRes:1;         // bit 23\r
  UINT32   Voltage33:1;       // bit 24\r
  UINT32   Voltage30:1;       // bit 25\r
  UINT32   Voltage18:1;       // bit 26\r
  UINT32   SysBus64V4:1;      // bit 27\r
  UINT32   SysBus64V3:1;      // bit 28\r
  UINT32   AsyncInt:1;        // bit 29\r
  UINT32   SlotType:2;        // bit 30:31\r
  UINT32   Sdr50:1;           // bit 32\r
  UINT32   Sdr104:1;          // bit 33\r
  UINT32   Ddr50:1;           // bit 34\r
  UINT32   Reserved3:1;       // bit 35\r
  UINT32   DriverTypeA:1;     // bit 36\r
  UINT32   DriverTypeC:1;     // bit 37\r
  UINT32   DriverTypeD:1;     // bit 38\r
  UINT32   DriverType4:1;     // bit 39\r
  UINT32   TimerCount:4;      // bit 40:43\r
  UINT32   Reserved4:1;       // bit 44\r
  UINT32   TuningSDR50:1;     // bit 45\r
  UINT32   RetuningMod:2;     // bit 46:47\r
  UINT32   ClkMultiplier:8;   // bit 48:55\r
  UINT32   Reserved5:7;       // bit 56:62\r
  UINT32   Hs400:1;           // bit 63\r
} SD_MMC_HC_SLOT_CAP;\r
\r
//\r
// SD Host controller version\r
//\r
#define SD_MMC_HC_CTRL_VER_100        0x00\r
#define SD_MMC_HC_CTRL_VER_200        0x01\r
#define SD_MMC_HC_CTRL_VER_300        0x02\r
#define SD_MMC_HC_CTRL_VER_400        0x03\r
#define SD_MMC_HC_CTRL_VER_410        0x04\r
#define SD_MMC_HC_CTRL_VER_420        0x05\r
\r
//\r
// SD Host controller V4 enhancements\r
//\r
#define SD_MMC_HC_V4_EN               BIT12\r
#define SD_MMC_HC_64_ADDR_EN          BIT13\r
#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
\r
/**\r
  Dump the content of SD/MMC host controller's Capability Register.\r
\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[in]  Capability      The buffer to store the capability data.\r
\r
**/\r
VOID\r
DumpCapabilityReg (\r
  IN UINT8                Slot,\r
  IN SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Read SlotInfo register from SD/MMC host controller pci config space.\r
\r
  @param[in]  PciIo        The PCI IO protocol instance.\r
  @param[out] FirstBar     The buffer to store the first BAR value.\r
  @param[out] SlotNum      The buffer to store the supported slot number.\r
\r
  @retval EFI_SUCCESS      The operation succeeds.\r
  @retval Others           The operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcGetSlotInfo (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
     OUT UINT8                 *FirstBar,\r
     OUT UINT8                 *SlotNum\r
  );\r
\r
/**\r
  Read/Write specified SD/MMC host controller mmio register.\r
\r
  @param[in]      PciIo        The PCI IO protocol instance.\r
  @param[in]      BarIndex     The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in]      Offset       The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in]      Read         A boolean to indicate it's read or write operation.\r
  @param[in]      Count        The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in, out] Data         For read operations, the destination buffer to store\r
                               the results. For write operations, the source buffer\r
                               to write data from. The caller is responsible for\r
                               having ownership of the data buffer and ensuring its\r
                               size not less than Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The read/write operation succeeds.\r
  @retval Others                The read/write operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcRwMmio (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
  IN     UINT8                 BarIndex,\r
  IN     UINT32                Offset,\r
  IN     BOOLEAN               Read,\r
  IN     UINT8                 Count,\r
  IN OUT VOID                  *Data\r
  );\r
\r
/**\r
  Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] OrData            The pointer to the data used to do OR operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The OR operation succeeds.\r
  @retval Others                The OR operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcOrMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *OrData\r
  );\r
\r
/**\r
  Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] AndData           The pointer to the data used to do AND operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The AND operation succeeds.\r
  @retval Others                The AND operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcAndMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *AndData\r
  );\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  BarIndex      The BAR index of the standard PCI Configuration\r
                            header to use as the base address for the memory\r
                            operation to perform.\r
  @param[in]  Offset        The offset within the selected BAR to start the\r
                            memory operation.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
  @param[in]  Timeout       The time out value for wait memory set, uses 1\r
                            microsecond as a unit.\r
\r
  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout\r
                            range.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcWaitMmioSet (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     BarIndex,\r
  IN  UINT32                    Offset,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue,\r
  IN  UINT64                    Timeout\r
  );\r
\r
/**\r
  Get the controller version information from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Version         The buffer to store the version information.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetControllerVersion (\r
  IN  EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN  UINT8                Slot,\r
  OUT UINT16               *Version\r
  );\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcEnableInterrupt (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetCapability (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Get the maximum current capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] MaxCurrent      The buffer to store the maximum current capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetMaxCurrent (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT UINT64               *MaxCurrent\r
  );\r
\r
/**\r
  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  Slot          The slot number of the SD card to send the command to.\r
  @param[out] MediaPresent  The pointer to the media present boolean value.\r
\r
  @retval EFI_SUCCESS       There is no media change happened.\r
  @retval EFI_MEDIA_CHANGED There is media change happened.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcCardDetect (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
     OUT BOOLEAN            *MediaPresent\r
  );\r
\r
/**\r
  Stop SD/MMC card clock.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.\r
  @retval Others            Fail to stop SD/MMC clock.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcStopClock (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  SD/MMC card clock supply.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.\r
  @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcClockSupply (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT64                 ClockFreq,\r
  IN UINT32                 BaseClkFreq,\r
  IN UINT16                 ControllerVer\r
  );\r
\r
/**\r
  SD/MMC bus power control.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] PowerCtrl      The value setting to the power control register.\r
\r
  @retval TRUE              There is a SD/MMC card attached.\r
  @retval FALSE             There is no a SD/MMC card attached.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcPowerControl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT8                  PowerCtrl\r
  );\r
\r
/**\r
  Set the SD/MMC bus width.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
\r
  @retval EFI_SUCCESS       The bus width is set successfully.\r
  @retval Others            The bus width isn't set successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcSetBusWidth (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT16                 BusWidth\r
  );\r
\r
/**\r
  Supply SD/MMC card with lowest clock frequency at initialization.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitClockFreq (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT32                 BaseClkFreq,\r
  IN UINT16                 ControllerVer\r
  );\r
\r
/**\r
  Supply SD/MMC card with maximum voltage at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Capability     The capability of the slot.\r
\r
  @retval EFI_SUCCESS       The voltage is supplied successfully.\r
  @retval Others            The voltage isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitPowerVoltage (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_HC_SLOT_CAP     Capability\r
  );\r
\r
/**\r
  Initialize the Timeout Control register with most conservative value at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The timeout control register is configured successfully.\r
  @retval Others            The timeout control register isn't configured successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitTimeoutCtrl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Set SD Host Controller control 2 registry according to selected speed.\r
\r
  @param[in] ControllerHandle The handle of the controller.\r
  @param[in] PciIo            The PCI IO protocol instance.\r
  @param[in] Slot             The slot number of the SD card to send the command to.\r
  @param[in] Timing           The timing to select.\r
\r
  @retval EFI_SUCCESS         The timing is set successfully.\r
  @retval Others              The timing isn't set successfully.\r
**/\r
EFI_STATUS\r
SdMmcHcUhsSignaling (\r
  IN EFI_HANDLE             ControllerHandle,\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_BUS_MODE        Timing\r
  );\r
\r
#endif\r
Commit	Line	Data
48555339 FT	1	/** @file\r
	2	\r
	3	Provides some data structure definitions used by the SD/MMC host controller driver.\r
	4	\r
690d60c0	5	Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
48555339	6	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
9d510e61	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
48555339 FT	8	\r
	9	**/\r
	10	\r
	11	#ifndef _SD_MMC_PCI_HCI_H_\r
	12	#define _SD_MMC_PCI_HCI_H_\r
	13	\r
	14	//\r
	15	// SD Host Controller SlotInfo Register Offset\r
	16	//\r
	17	#define SD_MMC_HC_SLOT_OFFSET 0x40\r
	18	\r
	19	#define SD_MMC_HC_MAX_SLOT 6\r
	20	\r
	21	//\r
	22	// SD Host Controller MMIO Register Offset\r
	23	//\r
	24	#define SD_MMC_HC_SDMA_ADDR 0x00\r
	25	#define SD_MMC_HC_ARG2 0x00\r
	26	#define SD_MMC_HC_BLK_SIZE 0x04\r
	27	#define SD_MMC_HC_BLK_COUNT 0x06\r
	28	#define SD_MMC_HC_ARG1 0x08\r
	29	#define SD_MMC_HC_TRANS_MOD 0x0C\r
	30	#define SD_MMC_HC_COMMAND 0x0E\r
	31	#define SD_MMC_HC_RESPONSE 0x10\r
	32	#define SD_MMC_HC_BUF_DAT_PORT 0x20\r
	33	#define SD_MMC_HC_PRESENT_STATE 0x24\r
	34	#define SD_MMC_HC_HOST_CTRL1 0x28\r
	35	#define SD_MMC_HC_POWER_CTRL 0x29\r
	36	#define SD_MMC_HC_BLK_GAP_CTRL 0x2A\r
	37	#define SD_MMC_HC_WAKEUP_CTRL 0x2B\r
	38	#define SD_MMC_HC_CLOCK_CTRL 0x2C\r
	39	#define SD_MMC_HC_TIMEOUT_CTRL 0x2E\r
	40	#define SD_MMC_HC_SW_RST 0x2F\r
	41	#define SD_MMC_HC_NOR_INT_STS 0x30\r
	42	#define SD_MMC_HC_ERR_INT_STS 0x32\r
	43	#define SD_MMC_HC_NOR_INT_STS_EN 0x34\r
	44	#define SD_MMC_HC_ERR_INT_STS_EN 0x36\r
	45	#define SD_MMC_HC_NOR_INT_SIG_EN 0x38\r
	46	#define SD_MMC_HC_ERR_INT_SIG_EN 0x3A\r
	47	#define SD_MMC_HC_AUTO_CMD_ERR_STS 0x3C\r
	48	#define SD_MMC_HC_HOST_CTRL2 0x3E\r
	49	#define SD_MMC_HC_CAP 0x40\r
	50	#define SD_MMC_HC_MAX_CURRENT_CAP 0x48\r
	51	#define SD_MMC_HC_FORCE_EVT_AUTO_CMD 0x50\r
	52	#define SD_MMC_HC_FORCE_EVT_ERR_INT 0x52\r
	53	#define SD_MMC_HC_ADMA_ERR_STS 0x54\r
	54	#define SD_MMC_HC_ADMA_SYS_ADDR 0x58\r
	55	#define SD_MMC_HC_PRESET_VAL 0x60\r
	56	#define SD_MMC_HC_SHARED_BUS_CTRL 0xE0\r
	57	#define SD_MMC_HC_SLOT_INT_STS 0xFC\r
	58	#define SD_MMC_HC_CTRL_VER 0xFE\r
	59	\r
a4708009 TM	60	//\r
	61	// SD Host Controller bits to HOST_CTRL2 register\r
	62	//\r
	63	#define SD_MMC_HC_CTRL_UHS_MASK 0x0007\r
	64	#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000\r
	65	#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001\r
	66	#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002\r
	67	#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003\r
	68	#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004\r
	69	#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000\r
	70	#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001\r
	71	#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004\r
	72	#define SD_MMC_HC_CTRL_MMC_HS200 0x0003\r
	73	#define SD_MMC_HC_CTRL_MMC_HS400 0x0005\r
	74	\r
48555339 FT	75	//\r
48555339 FT	76	// The transfer modes supported by SD Host Controller\r
48555339 FT	77	//\r
	78	typedef enum {\r
	79	SdMmcNoData,\r
	80	SdMmcPioMode,\r
	81	SdMmcSdmaMode,\r
690d60c0 AS	82	SdMmcAdma32bMode,\r
	83	SdMmcAdma64bV3Mode,\r
	84	SdMmcAdma64bV4Mode\r
48555339 FT	85	} SD_MMC_HC_TRANSFER_MODE;\r
48555339 FT	86	\r
690d60c0 AS	87	//\r
	88	// The ADMA transfer lengths supported by SD Host Controller\r
	89	//\r
	90	typedef enum {\r
	91	SdMmcAdmaLen16b,\r
	92	SdMmcAdmaLen26b\r
	93	} SD_MMC_HC_ADMA_LENGTH_MODE;\r
	94	\r
48555339 FT	95	//\r
	96	// The maximum data length of each descriptor line\r
	97	//\r
b5547b9c AS	98	#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB\r
b5547b9c AS	99	#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB\r
48555339	100	\r
b5547b9c AS	101	//\r
	102	// ADMA descriptor for 32b addressing.\r
	103	//\r
48555339 FT	104	typedef struct {\r
	105	UINT32 Valid:1;\r
	106	UINT32 End:1;\r
	107	UINT32 Int:1;\r
	108	UINT32 Reserved:1;\r
	109	UINT32 Act:2;\r
b5547b9c AS	110	UINT32 UpperLength:10;\r
b5547b9c AS	111	UINT32 LowerLength:16;\r
48555339	112	UINT32 Address;\r
b5547b9c AS	113	} SD_MMC_HC_ADMA_32_DESC_LINE;\r
	114	\r
	115	//\r
	116	// ADMA descriptor for 64b addressing.\r
	117	//\r
690d60c0 AS	118	typedef struct {\r
	119	UINT32 Valid:1;\r
	120	UINT32 End:1;\r
	121	UINT32 Int:1;\r
	122	UINT32 Reserved:1;\r
	123	UINT32 Act:2;\r
	124	UINT32 UpperLength:10;\r
	125	UINT32 LowerLength:16;\r
	126	UINT32 LowerAddress;\r
	127	UINT32 UpperAddress;\r
	128	} SD_MMC_HC_ADMA_64_V3_DESC_LINE;\r
	129	\r
b5547b9c AS	130	typedef struct {\r
	131	UINT32 Valid:1;\r
	132	UINT32 End:1;\r
	133	UINT32 Int:1;\r
	134	UINT32 Reserved:1;\r
	135	UINT32 Act:2;\r
	136	UINT32 UpperLength:10;\r
	137	UINT32 LowerLength:16;\r
	138	UINT32 LowerAddress;\r
	139	UINT32 UpperAddress;\r
	140	UINT32 Reserved1;\r
690d60c0	141	} SD_MMC_HC_ADMA_64_V4_DESC_LINE;\r
48555339 FT	142	\r
	143	#define SD_MMC_SDMA_BOUNDARY 512 * 1024\r
	144	#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
	145	\r
	146	typedef struct {\r
	147	UINT8 FirstBar:3; // bit 0:2\r
	148	UINT8 Reserved:1; // bit 3\r
	149	UINT8 SlotNum:3; // bit 4:6\r
	150	UINT8 Reserved1:1; // bit 7\r
	151	} SD_MMC_HC_SLOT_INFO;\r
	152	\r
	153	typedef struct {\r
	154	UINT32 TimeoutFreq:6; // bit 0:5\r
	155	UINT32 Reserved:1; // bit 6\r
	156	UINT32 TimeoutUnit:1; // bit 7\r
	157	UINT32 BaseClkFreq:8; // bit 8:15\r
	158	UINT32 MaxBlkLen:2; // bit 16:17\r
	159	UINT32 BusWidth8:1; // bit 18\r
	160	UINT32 Adma2:1; // bit 19\r
	161	UINT32 Reserved2:1; // bit 20\r
	162	UINT32 HighSpeed:1; // bit 21\r
	163	UINT32 Sdma:1; // bit 22\r
	164	UINT32 SuspRes:1; // bit 23\r
	165	UINT32 Voltage33:1; // bit 24\r
	166	UINT32 Voltage30:1; // bit 25\r
	167	UINT32 Voltage18:1; // bit 26\r
b5547b9c AS	168	UINT32 SysBus64V4:1; // bit 27\r
b5547b9c AS	169	UINT32 SysBus64V3:1; // bit 28\r
48555339 FT	170	UINT32 AsyncInt:1; // bit 29\r
	171	UINT32 SlotType:2; // bit 30:31\r
	172	UINT32 Sdr50:1; // bit 32\r
	173	UINT32 Sdr104:1; // bit 33\r
	174	UINT32 Ddr50:1; // bit 34\r
b5547b9c	175	UINT32 Reserved3:1; // bit 35\r
48555339 FT	176	UINT32 DriverTypeA:1; // bit 36\r
	177	UINT32 DriverTypeC:1; // bit 37\r
	178	UINT32 DriverTypeD:1; // bit 38\r
	179	UINT32 DriverType4:1; // bit 39\r
	180	UINT32 TimerCount:4; // bit 40:43\r
b5547b9c	181	UINT32 Reserved4:1; // bit 44\r
48555339 FT	182	UINT32 TuningSDR50:1; // bit 45\r
	183	UINT32 RetuningMod:2; // bit 46:47\r
	184	UINT32 ClkMultiplier:8; // bit 48:55\r
b5547b9c	185	UINT32 Reserved5:7; // bit 56:62\r
48555339 FT	186	UINT32 Hs400:1; // bit 63\r
	187	} SD_MMC_HC_SLOT_CAP;\r
	188	\r
bdf038cc JB	189	//\r
	190	// SD Host controller version\r
	191	//\r
b5547b9c AS	192	#define SD_MMC_HC_CTRL_VER_100 0x00\r
	193	#define SD_MMC_HC_CTRL_VER_200 0x01\r
	194	#define SD_MMC_HC_CTRL_VER_300 0x02\r
	195	#define SD_MMC_HC_CTRL_VER_400 0x03\r
	196	#define SD_MMC_HC_CTRL_VER_410 0x04\r
	197	#define SD_MMC_HC_CTRL_VER_420 0x05\r
	198	\r
	199	//\r
	200	// SD Host controller V4 enhancements\r
	201	//\r
	202	#define SD_MMC_HC_V4_EN BIT12\r
	203	#define SD_MMC_HC_64_ADDR_EN BIT13\r
	204	#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
bdf038cc	205	\r
48555339 FT	206	/**\r
	207	Dump the content of SD/MMC host controller's Capability Register.\r
	208	\r
	209	@param[in] Slot The slot number of the SD card to send the command to.\r
	210	@param[in] Capability The buffer to store the capability data.\r
	211	\r
	212	**/\r
	213	VOID\r
	214	DumpCapabilityReg (\r
	215	IN UINT8 Slot,\r
	216	IN SD_MMC_HC_SLOT_CAP *Capability\r
	217	);\r
	218	\r
	219	/**\r
	220	Read SlotInfo register from SD/MMC host controller pci config space.\r
	221	\r
	222	@param[in] PciIo The PCI IO protocol instance.\r
	223	@param[out] FirstBar The buffer to store the first BAR value.\r
	224	@param[out] SlotNum The buffer to store the supported slot number.\r
	225	\r
	226	@retval EFI_SUCCESS The operation succeeds.\r
	227	@retval Others The operation fails.\r
	228	\r
	229	**/\r
	230	EFI_STATUS\r
	231	EFIAPI\r
	232	SdMmcHcGetSlotInfo (\r
	233	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	234	OUT UINT8 *FirstBar,\r
	235	OUT UINT8 *SlotNum\r
	236	);\r
	237	\r
	238	/**\r
	239	Read/Write specified SD/MMC host controller mmio register.\r
	240	\r
	241	@param[in] PciIo The PCI IO protocol instance.\r
	242	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
	243	header to use as the base address for the memory\r
	244	operation to perform.\r
	245	@param[in] Offset The offset within the selected BAR to start the\r
	246	memory operation.\r
	247	@param[in] Read A boolean to indicate it's read or write operation.\r
	248	@param[in] Count The width of the mmio register in bytes.\r
	249	Must be 1, 2 , 4 or 8 bytes.\r
	250	@param[in, out] Data For read operations, the destination buffer to store\r
	251	the results. For write operations, the source buffer\r
	252	to write data from. The caller is responsible for\r
	253	having ownership of the data buffer and ensuring its\r
	254	size not less than Count bytes.\r
	255	\r
	256	@retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
	257	@retval EFI_SUCCESS The read/write operation succeeds.\r
	258	@retval Others The read/write operation fails.\r
	259	\r
	260	**/\r
	261	EFI_STATUS\r
	262	EFIAPI\r
	263	SdMmcHcRwMmio (\r
	264	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	265	IN UINT8 BarIndex,\r
	266	IN UINT32 Offset,\r
	267	IN BOOLEAN Read,\r
	268	IN UINT8 Count,\r
	269	IN OUT VOID *Data\r
270	);\r
271	\r
272	/**\r
273	Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
274	\r
275	@param[in] PciIo The PCI IO protocol instance.\r
276	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
277	header to use as the base address for the memory\r
278	operation to perform.\r
279	@param[in] Offset The offset within the selected BAR to start the\r
280	memory operation.\r
281	@param[in] Count The width of the mmio register in bytes.\r
282	Must be 1, 2 , 4 or 8 bytes.\r
283	@param[in] OrData The pointer to the data used to do OR operation.\r
284	The caller is responsible for having ownership of\r
285	the data buffer and ensuring its size not less than\r
286	Count bytes.\r
287	\r
288	@retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
289	@retval EFI_SUCCESS The OR operation succeeds.\r
290	@retval Others The OR operation fails.\r
291	\r
292	**/\r
293	EFI_STATUS\r
294	EFIAPI\r
295	SdMmcHcOrMmio (\r
296	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
297	IN UINT8 BarIndex,\r
298	IN UINT32 Offset,\r
299	IN UINT8 Count,\r
300	IN VOID *OrData\r
301	);\r
302	\r
303	/**\r
304	Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
305	\r
306	@param[in] PciIo The PCI IO protocol instance.\r
307	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
308	header to use as the base address for the memory\r
309	operation to perform.\r
310	@param[in] Offset The offset within the selected BAR to start the\r
311	memory operation.\r
312	@param[in] Count The width of the mmio register in bytes.\r
313	Must be 1, 2 , 4 or 8 bytes.\r
314	@param[in] AndData The pointer to the data used to do AND operation.\r
315	The caller is responsible for having ownership of\r
316	the data buffer and ensuring its size not less than\r
317	Count bytes.\r
318	\r
319	@retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
320	@retval EFI_SUCCESS The AND operation succeeds.\r
321	@retval Others The AND operation fails.\r
322	\r
323	**/\r
324	EFI_STATUS\r
325	EFIAPI\r
326	SdMmcHcAndMmio (\r
327	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
328	IN UINT8 BarIndex,\r
329	IN UINT32 Offset,\r
330	IN UINT8 Count,\r
331	IN VOID *AndData\r
332	);\r
333	\r
334	/**\r
335	Wait for the value of the specified MMIO register set to the test value.\r
336	\r
337	@param[in] PciIo The PCI IO protocol instance.\r
338	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
339	header to use as the base address for the memory\r
340	operation to perform.\r
341	@param[in] Offset The offset within the selected BAR to start the\r
342	memory operation.\r
343	@param[in] Count The width of the mmio register in bytes.\r
344	Must be 1, 2, 4 or 8 bytes.\r
345	@param[in] MaskValue The mask value of memory.\r
346	@param[in] TestValue The test value of memory.\r
347	@param[in] Timeout The time out value for wait memory set, uses 1\r
348	microsecond as a unit.\r
349	\r
350	@retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r
351	range.\r
352	@retval EFI_SUCCESS The MMIO register has expected value.\r
353	@retval Others The MMIO operation fails.\r
354	\r
355	**/\r
356	EFI_STATUS\r
357	EFIAPI\r
358	SdMmcHcWaitMmioSet (\r
359	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
360	IN UINT8 BarIndex,\r
361	IN UINT32 Offset,\r
362	IN UINT8 Count,\r
363	IN UINT64 MaskValue,\r
364	IN UINT64 TestValue,\r
365	IN UINT64 Timeout\r
366	);\r
367	\r
b5547b9c AS	368	/**\r
	369	Get the controller version information from the specified slot.\r
	370	\r
	371	@param[in] PciIo The PCI IO protocol instance.\r
	372	@param[in] Slot The slot number of the SD card to send the command to.\r
	373	@param[out] Version The buffer to store the version information.\r
	374	\r
	375	@retval EFI_SUCCESS The operation executes successfully.\r
	376	@retval Others The operation fails.\r
	377	\r
	378	**/\r
	379	EFI_STATUS\r
	380	SdMmcHcGetControllerVersion (\r
	381	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	382	IN UINT8 Slot,\r
	383	OUT UINT16 *Version\r
	384	);\r
	385	\r
48555339 FT	386	/**\r
	387	Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
	388	register.\r
	389	\r
	390	@param[in] PciIo The PCI IO protocol instance.\r
	391	@param[in] Slot The slot number of the SD card to send the command to.\r
	392	\r
	393	@retval EFI_SUCCESS The operation executes successfully.\r
	394	@retval Others The operation fails.\r
	395	\r
	396	**/\r
	397	EFI_STATUS\r
	398	SdMmcHcEnableInterrupt (\r
	399	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	400	IN UINT8 Slot\r
	401	);\r
	402	\r
	403	/**\r
	404	Get the capability data from the specified slot.\r
	405	\r
	406	@param[in] PciIo The PCI IO protocol instance.\r
	407	@param[in] Slot The slot number of the SD card to send the command to.\r
	408	@param[out] Capability The buffer to store the capability data.\r
	409	\r
	410	@retval EFI_SUCCESS The operation executes successfully.\r
	411	@retval Others The operation fails.\r
	412	\r
	413	**/\r
	414	EFI_STATUS\r
	415	SdMmcHcGetCapability (\r
	416	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	417	IN UINT8 Slot,\r
	418	OUT SD_MMC_HC_SLOT_CAP *Capability\r
	419	);\r
	420	\r
	421	/**\r
	422	Get the maximum current capability data from the specified slot.\r
	423	\r
	424	@param[in] PciIo The PCI IO protocol instance.\r
	425	@param[in] Slot The slot number of the SD card to send the command to.\r
	426	@param[out] MaxCurrent The buffer to store the maximum current capability data.\r
	427	\r
	428	@retval EFI_SUCCESS The operation executes successfully.\r
	429	@retval Others The operation fails.\r
	430	\r
	431	**/\r
	432	EFI_STATUS\r
	433	SdMmcHcGetMaxCurrent (\r
	434	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	435	IN UINT8 Slot,\r
	436	OUT UINT64 *MaxCurrent\r
	437	);\r
	438	\r
	439	/**\r
	440	Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
	441	slot.\r
	442	\r
	443	Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
	444	\r
	445	@param[in] PciIo The PCI IO protocol instance.\r
	446	@param[in] Slot The slot number of the SD card to send the command to.\r
	447	@param[out] MediaPresent The pointer to the media present boolean value.\r
	448	\r
	449	@retval EFI_SUCCESS There is no media change happened.\r
450	@retval EFI_MEDIA_CHANGED There is media change happened.\r
451	@retval Others The detection fails.\r
452	\r
453	**/\r
454	EFI_STATUS\r
455	SdMmcHcCardDetect (\r
456	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
457	IN UINT8 Slot,\r
458	OUT BOOLEAN *MediaPresent\r
459	);\r
460	\r
461	/**\r
462	Stop SD/MMC card clock.\r
463	\r
464	Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
465	\r
466	@param[in] PciIo The PCI IO protocol instance.\r
467	@param[in] Slot The slot number of the SD card to send the command to.\r
468	\r
469	@retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r
470	@retval Others Fail to stop SD/MMC clock.\r
471	\r
472	**/\r
473	EFI_STATUS\r
474	SdMmcHcStopClock (\r
475	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
476	IN UINT8 Slot\r
477	);\r
478	\r
479	/**\r
480	SD/MMC card clock supply.\r
481	\r
482	Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
483	\r
484	@param[in] PciIo The PCI IO protocol instance.\r
485	@param[in] Slot The slot number of the SD card to send the command to.\r
486	@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
7f3b0bad	487	@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
b5547b9c	488	@param[in] ControllerVer The version of host controller.\r
48555339 FT	489	\r
	490	@retval EFI_SUCCESS The clock is supplied successfully.\r
	491	@retval Others The clock isn't supplied successfully.\r
	492	\r
	493	**/\r
	494	EFI_STATUS\r
	495	SdMmcHcClockSupply (\r
	496	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	497	IN UINT8 Slot,\r
	498	IN UINT64 ClockFreq,\r
b5547b9c AS	499	IN UINT32 BaseClkFreq,\r
b5547b9c AS	500	IN UINT16 ControllerVer\r
48555339 FT	501	);\r
	502	\r
	503	/**\r
	504	SD/MMC bus power control.\r
	505	\r
	506	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
	507	\r
	508	@param[in] PciIo The PCI IO protocol instance.\r
	509	@param[in] Slot The slot number of the SD card to send the command to.\r
	510	@param[in] PowerCtrl The value setting to the power control register.\r
	511	\r
	512	@retval TRUE There is a SD/MMC card attached.\r
	513	@retval FALSE There is no a SD/MMC card attached.\r
	514	\r
	515	**/\r
	516	EFI_STATUS\r
	517	SdMmcHcPowerControl (\r
	518	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	519	IN UINT8 Slot,\r
	520	IN UINT8 PowerCtrl\r
	521	);\r
	522	\r
	523	/**\r
	524	Set the SD/MMC bus width.\r
	525	\r
	526	Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
	527	\r
	528	@param[in] PciIo The PCI IO protocol instance.\r
	529	@param[in] Slot The slot number of the SD card to send the command to.\r
	530	@param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
	531	\r
	532	@retval EFI_SUCCESS The bus width is set successfully.\r
	533	@retval Others The bus width isn't set successfully.\r
	534	\r
	535	**/\r
	536	EFI_STATUS\r
	537	SdMmcHcSetBusWidth (\r
	538	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	539	IN UINT8 Slot,\r
	540	IN UINT16 BusWidth\r
	541	);\r
	542	\r
	543	/**\r
	544	Supply SD/MMC card with lowest clock frequency at initialization.\r
	545	\r
	546	@param[in] PciIo The PCI IO protocol instance.\r
	547	@param[in] Slot The slot number of the SD card to send the command to.\r
7f3b0bad	548	@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
b5547b9c	549	@param[in] ControllerVer The version of host controller.\r
48555339 FT	550	\r
	551	@retval EFI_SUCCESS The clock is supplied successfully.\r
	552	@retval Others The clock isn't supplied successfully.\r
	553	\r
	554	**/\r
	555	EFI_STATUS\r
	556	SdMmcHcInitClockFreq (\r
	557	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	558	IN UINT8 Slot,\r
b5547b9c AS	559	IN UINT32 BaseClkFreq,\r
b5547b9c AS	560	IN UINT16 ControllerVer\r
48555339 FT	561	);\r
	562	\r
	563	/**\r
	564	Supply SD/MMC card with maximum voltage at initialization.\r
	565	\r
	566	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
	567	\r
	568	@param[in] PciIo The PCI IO protocol instance.\r
	569	@param[in] Slot The slot number of the SD card to send the command to.\r
	570	@param[in] Capability The capability of the slot.\r
	571	\r
	572	@retval EFI_SUCCESS The voltage is supplied successfully.\r
	573	@retval Others The voltage isn't supplied successfully.\r
	574	\r
	575	**/\r
	576	EFI_STATUS\r
	577	SdMmcHcInitPowerVoltage (\r
	578	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	579	IN UINT8 Slot,\r
	580	IN SD_MMC_HC_SLOT_CAP Capability\r
	581	);\r
	582	\r
	583	/**\r
	584	Initialize the Timeout Control register with most conservative value at initialization.\r
	585	\r
	586	Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
	587	\r
	588	@param[in] PciIo The PCI IO protocol instance.\r
	589	@param[in] Slot The slot number of the SD card to send the command to.\r
	590	\r
	591	@retval EFI_SUCCESS The timeout control register is configured successfully.\r
	592	@retval Others The timeout control register isn't configured successfully.\r
	593	\r
	594	**/\r
	595	EFI_STATUS\r
	596	SdMmcHcInitTimeoutCtrl (\r
	597	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	598	IN UINT8 Slot\r
	599	);\r
	600	\r
a4708009 TM	601	/**\r
	602	Set SD Host Controller control 2 registry according to selected speed.\r
	603	\r
	604	@param[in] ControllerHandle The handle of the controller.\r
	605	@param[in] PciIo The PCI IO protocol instance.\r
	606	@param[in] Slot The slot number of the SD card to send the command to.\r
	607	@param[in] Timing The timing to select.\r
	608	\r
	609	@retval EFI_SUCCESS The timing is set successfully.\r
	610	@retval Others The timing isn't set successfully.\r
	611	**/\r
	612	EFI_STATUS\r
	613	SdMmcHcUhsSignaling (\r
	614	IN EFI_HANDLE ControllerHandle,\r
	615	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	616	IN UINT8 Slot,\r
	617	IN SD_MMC_BUS_MODE Timing\r
	618	);\r
	619	\r
48555339	620	#endif\r