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913cb9dc | 1 | /** @file\r |
2 | \r | |
ab6495ea | 3 | The definition for UHCI register operation routines.\r |
4 | \r | |
b4c24e2d | 5 | Copyright (c) 2007 - 2008, Intel Corporation\r |
913cb9dc | 6 | All rights reserved. This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
913cb9dc | 14 | **/\r |
15 | \r | |
16 | #ifndef _EFI_UHCI_REG_H_\r | |
17 | #define _EFI_UHCI_REG_H_\r | |
18 | \r | |
19 | #define BIT(a) (1 << (a))\r | |
20 | \r | |
ab6495ea | 21 | typedef enum {\r |
913cb9dc | 22 | UHCI_FRAME_NUM = 1024,\r |
23 | \r | |
24 | //\r | |
25 | // Register offset and PCI related staff\r | |
26 | //\r | |
27 | CLASSC_OFFSET = 0x09,\r | |
28 | USBBASE_OFFSET = 0x20,\r | |
29 | USB_BAR_INDEX = 4,\r | |
30 | PCI_CLASSC_PI_UHCI = 0x00,\r | |
31 | \r | |
32 | USBCMD_OFFSET = 0,\r | |
33 | USBSTS_OFFSET = 2,\r | |
34 | USBINTR_OFFSET = 4,\r | |
35 | USBPORTSC_OFFSET = 0x10,\r | |
36 | USB_FRAME_NO_OFFSET = 6,\r | |
37 | USB_FRAME_BASE_OFFSET = 8,\r | |
38 | USB_EMULATION_OFFSET = 0xC0,\r | |
39 | \r | |
40 | //\r | |
41 | // Packet IDs\r | |
42 | //\r | |
43 | SETUP_PACKET_ID = 0x2D,\r | |
44 | INPUT_PACKET_ID = 0x69,\r | |
45 | OUTPUT_PACKET_ID = 0xE1,\r | |
46 | ERROR_PACKET_ID = 0x55,\r | |
47 | \r | |
48 | //\r | |
49 | // USB port status and control bit definition.\r | |
50 | //\r | |
51 | USBPORTSC_CCS = BIT(0), // Current Connect Status\r | |
52 | USBPORTSC_CSC = BIT(1), // Connect Status Change\r | |
53 | USBPORTSC_PED = BIT(2), // Port Enable / Disable\r | |
54 | USBPORTSC_PEDC = BIT(3), // Port Enable / Disable Change\r | |
55 | USBPORTSC_LSL = BIT(4), // Line Status Low BIT\r | |
56 | USBPORTSC_LSH = BIT(5), // Line Status High BIT\r | |
57 | USBPORTSC_RD = BIT(6), // Resume Detect\r | |
58 | USBPORTSC_LSDA = BIT(8), // Low Speed Device Attached\r | |
59 | USBPORTSC_PR = BIT(9), // Port Reset\r | |
60 | USBPORTSC_SUSP = BIT(12), // Suspend\r | |
61 | \r | |
b4c24e2d | 62 | //\r |
63 | // UHCI Spec said it must implement 2 ports each host at least,\r | |
64 | // and if more, check whether the bit7 of PORTSC is always 1.\r | |
65 | // So here assume the max of port number each host is 16.\r | |
66 | //\r | |
67 | USB_MAX_ROOTHUB_PORT = 0x0F,\r | |
68 | \r | |
913cb9dc | 69 | //\r |
70 | // Command register bit definitions\r | |
71 | //\r | |
72 | USBCMD_RS = BIT(0), // Run/Stop\r | |
73 | USBCMD_HCRESET = BIT(1), // Host reset\r | |
74 | USBCMD_GRESET = BIT(2), // Global reset\r | |
75 | USBCMD_EGSM = BIT(3), // Global Suspend Mode\r | |
76 | USBCMD_FGR = BIT(4), // Force Global Resume\r | |
77 | USBCMD_SWDBG = BIT(5), // SW Debug mode\r | |
78 | USBCMD_CF = BIT(6), // Config Flag (sw only)\r | |
79 | USBCMD_MAXP = BIT(7), // Max Packet (0 = 32, 1 = 64)\r | |
80 | \r | |
81 | //\r | |
82 | // USB Status register bit definitions\r | |
83 | //\r | |
84 | USBSTS_USBINT = BIT(0), // Interrupt due to IOC\r | |
85 | USBSTS_ERROR = BIT(1), // Interrupt due to error\r | |
86 | USBSTS_RD = BIT(2), // Resume Detect\r | |
87 | USBSTS_HSE = BIT(3), // Host System Error\r | |
88 | USBSTS_HCPE = BIT(4), // Host Controller Process Error\r | |
89 | USBSTS_HCH = BIT(5), // HC Halted\r | |
90 | \r | |
91 | USBTD_ACTIVE = BIT(7), // TD is still active\r | |
92 | USBTD_STALLED = BIT(6), // TD is stalled\r | |
93 | USBTD_BUFFERR = BIT(5), // Buffer underflow or overflow\r | |
94 | USBTD_BABBLE = BIT(4), // Babble condition\r | |
95 | USBTD_NAK = BIT(3), // NAK is received\r | |
96 | USBTD_CRC = BIT(2), // CRC/Time out error\r | |
c52fa98c | 97 | USBTD_BITSTUFF = BIT(1) // Bit stuff error\r |
ab6495ea | 98 | }UHCI_REGISTER_OFFSET;\r |
913cb9dc | 99 | \r |
100 | \r | |
101 | /**\r | |
ab6495ea | 102 | Read a UHCI register.\r |
913cb9dc | 103 | \r |
ab6495ea | 104 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
105 | @param Offset Register offset to USB_BAR_INDEX.\r | |
913cb9dc | 106 | \r |
ab6495ea | 107 | @return Content of register.\r |
913cb9dc | 108 | \r |
109 | **/\r | |
110 | UINT16\r | |
111 | UhciReadReg (\r | |
112 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
113 | IN UINT32 Offset\r | |
ed66e1bc | 114 | );\r |
913cb9dc | 115 | \r |
116 | \r | |
117 | \r | |
118 | /**\r | |
ab6495ea | 119 | Write data to UHCI register.\r |
913cb9dc | 120 | \r |
ab6495ea | 121 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
122 | @param Offset Register offset to USB_BAR_INDEX.\r | |
123 | @param Data Data to write.\r | |
913cb9dc | 124 | \r |
ab6495ea | 125 | @return None.\r |
913cb9dc | 126 | \r |
127 | **/\r | |
128 | VOID\r | |
129 | UhciWriteReg (\r | |
130 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
131 | IN UINT32 Offset,\r | |
132 | IN UINT16 Data\r | |
ed66e1bc | 133 | );\r |
913cb9dc | 134 | \r |
135 | \r | |
136 | \r | |
137 | /**\r | |
ab6495ea | 138 | Set a bit of the UHCI Register.\r |
913cb9dc | 139 | \r |
ab6495ea | 140 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
141 | @param Offset Register offset to USB_BAR_INDEX.\r | |
142 | @param Bit The bit to set.\r | |
913cb9dc | 143 | \r |
ab6495ea | 144 | @return None.\r |
913cb9dc | 145 | \r |
146 | **/\r | |
147 | VOID\r | |
148 | UhciSetRegBit (\r | |
149 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
150 | IN UINT32 Offset,\r | |
151 | IN UINT16 Bit\r | |
ed66e1bc | 152 | );\r |
913cb9dc | 153 | \r |
154 | \r | |
155 | \r | |
156 | /**\r | |
ab6495ea | 157 | Clear a bit of the UHCI Register.\r |
913cb9dc | 158 | \r |
ab6495ea | 159 | @param PciIo The PCI_IO protocol to access the PCI.\r |
160 | @param Offset Register offset to USB_BAR_INDEX.\r | |
161 | @param Bit The bit to clear.\r | |
913cb9dc | 162 | \r |
ab6495ea | 163 | @return None.\r |
913cb9dc | 164 | \r |
165 | **/\r | |
166 | VOID\r | |
167 | UhciClearRegBit (\r | |
168 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
169 | IN UINT32 Offset,\r | |
170 | IN UINT16 Bit\r | |
ed66e1bc | 171 | );\r |
913cb9dc | 172 | \r |
173 | \r | |
174 | /**\r | |
175 | Clear all the interrutp status bits, these bits\r | |
ab6495ea | 176 | are Write-Clean.\r |
913cb9dc | 177 | \r |
ab6495ea | 178 | @param Uhc The UHCI device.\r |
913cb9dc | 179 | \r |
ab6495ea | 180 | @return None.\r |
913cb9dc | 181 | \r |
182 | **/\r | |
183 | VOID\r | |
184 | UhciAckAllInterrupt (\r | |
185 | IN USB_HC_DEV *Uhc\r | |
ed66e1bc | 186 | );\r |
913cb9dc | 187 | \r |
188 | \r | |
189 | /**\r | |
ab6495ea | 190 | Stop the host controller.\r |
913cb9dc | 191 | \r |
ab6495ea | 192 | @param Uhc The UHCI device.\r |
193 | @param Timeout Max time allowed.\r | |
913cb9dc | 194 | \r |
ab6495ea | 195 | @retval EFI_SUCCESS The host controller is stopped.\r |
196 | @retval EFI_TIMEOUT Failed to stop the host controller.\r | |
913cb9dc | 197 | \r |
198 | **/\r | |
199 | EFI_STATUS\r | |
200 | UhciStopHc (\r | |
201 | IN USB_HC_DEV *Uhc,\r | |
202 | IN UINTN Timeout\r | |
ed66e1bc | 203 | );\r |
913cb9dc | 204 | \r |
205 | \r | |
206 | \r | |
207 | /**\r | |
ab6495ea | 208 | Check whether the host controller operates well.\r |
913cb9dc | 209 | \r |
ab6495ea | 210 | @param PciIo The PCI_IO protocol to use.\r |
913cb9dc | 211 | \r |
ab6495ea | 212 | @retval TRUE Host controller is working.\r |
213 | @retval FALSE Host controller is halted or system error.\r | |
913cb9dc | 214 | \r |
215 | **/\r | |
216 | BOOLEAN\r | |
217 | UhciIsHcWorking (\r | |
218 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 219 | );\r |
913cb9dc | 220 | \r |
221 | \r | |
222 | /**\r | |
223 | Set the UHCI frame list base address. It can't use\r | |
224 | UhciWriteReg which access memory in UINT16.\r | |
225 | \r | |
ab6495ea | 226 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
227 | @param Addr Address to set.\r | |
913cb9dc | 228 | \r |
ab6495ea | 229 | @return None.\r |
913cb9dc | 230 | \r |
231 | **/\r | |
232 | VOID\r | |
233 | UhciSetFrameListBaseAddr (\r | |
234 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
235 | IN VOID *Addr\r | |
ed66e1bc | 236 | );\r |
913cb9dc | 237 | \r |
238 | \r | |
239 | /**\r | |
ab6495ea | 240 | Disable USB Emulation.\r |
913cb9dc | 241 | \r |
ab6495ea | 242 | @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r |
913cb9dc | 243 | \r |
ab6495ea | 244 | @return None.\r |
913cb9dc | 245 | \r |
246 | **/\r | |
247 | VOID\r | |
248 | UhciTurnOffUsbEmulation (\r | |
249 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 250 | );\r |
913cb9dc | 251 | #endif\r |