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Commit | Line | Data |
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913cb9dc | 1 | /** @file\r |
2 | \r | |
ab6495ea | 3 | The definition for UHCI register operation routines.\r |
4 | \r | |
cd5ebaa0 | 5 | Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
913cb9dc | 7 | \r |
913cb9dc | 8 | **/\r |
9 | \r | |
10 | #ifndef _EFI_UHCI_REG_H_\r | |
11 | #define _EFI_UHCI_REG_H_\r | |
12 | \r | |
1ccdbf2a | 13 | //\r |
14 | // UHCI register offset\r | |
15 | //\r | |
16 | \r | |
17 | #define UHCI_FRAME_NUM 1024\r | |
18 | \r | |
19 | //\r | |
20 | // Register offset and PCI related staff\r | |
21 | //\r | |
22 | #define USB_BAR_INDEX 4\r | |
23 | \r | |
24 | #define USBCMD_OFFSET 0\r | |
25 | #define USBSTS_OFFSET 2\r | |
26 | #define USBINTR_OFFSET 4\r | |
27 | #define USBPORTSC_OFFSET 0x10\r | |
28 | #define USB_FRAME_NO_OFFSET 6\r | |
29 | #define USB_FRAME_BASE_OFFSET 8\r | |
30 | #define USB_EMULATION_OFFSET 0xC0\r | |
31 | \r | |
32 | //\r | |
33 | // Packet IDs\r | |
34 | //\r | |
35 | #define SETUP_PACKET_ID 0x2D\r | |
36 | #define INPUT_PACKET_ID 0x69\r | |
37 | #define OUTPUT_PACKET_ID 0xE1\r | |
38 | #define ERROR_PACKET_ID 0x55\r | |
39 | \r | |
40 | //\r | |
41 | // USB port status and control bit definition.\r | |
42 | //\r | |
43 | #define USBPORTSC_CCS BIT0 // Current Connect Status\r | |
44 | #define USBPORTSC_CSC BIT1 // Connect Status Change\r | |
45 | #define USBPORTSC_PED BIT2 // Port Enable / Disable\r | |
46 | #define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change\r | |
47 | #define USBPORTSC_LSL BIT4 // Line Status Low BIT\r | |
48 | #define USBPORTSC_LSH BIT5 // Line Status High BIT\r | |
49 | #define USBPORTSC_RD BIT6 // Resume Detect\r | |
50 | #define USBPORTSC_LSDA BIT8 // Low Speed Device Attached\r | |
51 | #define USBPORTSC_PR BIT9 // Port Reset\r | |
52 | #define USBPORTSC_SUSP BIT12 // Suspend\r | |
53 | \r | |
54 | //\r | |
55 | // UHCI Spec said it must implement 2 ports each host at least,\r | |
56 | // and if more, check whether the bit7 of PORTSC is always 1.\r | |
57 | // So here assume the max of port number each host is 16.\r | |
58 | //\r | |
59 | #define USB_MAX_ROOTHUB_PORT 0x0F\r | |
60 | \r | |
61 | //\r | |
62 | // Command register bit definitions\r | |
63 | //\r | |
64 | #define USBCMD_RS BIT0 // Run/Stop\r | |
65 | #define USBCMD_HCRESET BIT1 // Host reset\r | |
66 | #define USBCMD_GRESET BIT2 // Global reset\r | |
67 | #define USBCMD_EGSM BIT3 // Global Suspend Mode\r | |
68 | #define USBCMD_FGR BIT4 // Force Global Resume\r | |
69 | #define USBCMD_SWDBG BIT5 // SW Debug mode\r | |
70 | #define USBCMD_CF BIT6 // Config Flag (sw only)\r | |
71 | #define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)\r | |
72 | \r | |
73 | //\r | |
74 | // USB Status register bit definitions\r | |
75 | //\r | |
76 | #define USBSTS_USBINT BIT0 // Interrupt due to IOC\r | |
77 | #define USBSTS_ERROR BIT1 // Interrupt due to error\r | |
78 | #define USBSTS_RD BIT2 // Resume Detect\r | |
79 | #define USBSTS_HSE BIT3 // Host System Error\r | |
80 | #define USBSTS_HCPE BIT4 // Host Controller Process Error\r | |
81 | #define USBSTS_HCH BIT5 // HC Halted\r | |
82 | \r | |
83 | #define USBTD_ACTIVE BIT7 // TD is still active\r | |
84 | #define USBTD_STALLED BIT6 // TD is stalled\r | |
85 | #define USBTD_BUFFERR BIT5 // Buffer underflow or overflow\r | |
86 | #define USBTD_BABBLE BIT4 // Babble condition\r | |
87 | #define USBTD_NAK BIT3 // NAK is received\r | |
88 | #define USBTD_CRC BIT2 // CRC/Time out error\r | |
89 | #define USBTD_BITSTUFF BIT1 // Bit stuff error\r | |
913cb9dc | 90 | \r |
91 | \r | |
92 | /**\r | |
ab6495ea | 93 | Read a UHCI register.\r |
913cb9dc | 94 | \r |
ab6495ea | 95 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
96 | @param Offset Register offset to USB_BAR_INDEX.\r | |
913cb9dc | 97 | \r |
ab6495ea | 98 | @return Content of register.\r |
913cb9dc | 99 | \r |
100 | **/\r | |
101 | UINT16\r | |
102 | UhciReadReg (\r | |
103 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
104 | IN UINT32 Offset\r | |
ed66e1bc | 105 | );\r |
913cb9dc | 106 | \r |
107 | \r | |
108 | \r | |
109 | /**\r | |
ab6495ea | 110 | Write data to UHCI register.\r |
913cb9dc | 111 | \r |
ab6495ea | 112 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
113 | @param Offset Register offset to USB_BAR_INDEX.\r | |
114 | @param Data Data to write.\r | |
913cb9dc | 115 | \r |
ab6495ea | 116 | @return None.\r |
913cb9dc | 117 | \r |
118 | **/\r | |
119 | VOID\r | |
120 | UhciWriteReg (\r | |
121 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
122 | IN UINT32 Offset,\r | |
123 | IN UINT16 Data\r | |
ed66e1bc | 124 | );\r |
913cb9dc | 125 | \r |
126 | \r | |
127 | \r | |
128 | /**\r | |
ab6495ea | 129 | Set a bit of the UHCI Register.\r |
913cb9dc | 130 | \r |
ab6495ea | 131 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
132 | @param Offset Register offset to USB_BAR_INDEX.\r | |
133 | @param Bit The bit to set.\r | |
913cb9dc | 134 | \r |
ab6495ea | 135 | @return None.\r |
913cb9dc | 136 | \r |
137 | **/\r | |
138 | VOID\r | |
139 | UhciSetRegBit (\r | |
140 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
141 | IN UINT32 Offset,\r | |
142 | IN UINT16 Bit\r | |
ed66e1bc | 143 | );\r |
913cb9dc | 144 | \r |
145 | \r | |
146 | \r | |
147 | /**\r | |
ab6495ea | 148 | Clear a bit of the UHCI Register.\r |
913cb9dc | 149 | \r |
ab6495ea | 150 | @param PciIo The PCI_IO protocol to access the PCI.\r |
151 | @param Offset Register offset to USB_BAR_INDEX.\r | |
152 | @param Bit The bit to clear.\r | |
913cb9dc | 153 | \r |
ab6495ea | 154 | @return None.\r |
913cb9dc | 155 | \r |
156 | **/\r | |
157 | VOID\r | |
158 | UhciClearRegBit (\r | |
159 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
160 | IN UINT32 Offset,\r | |
161 | IN UINT16 Bit\r | |
ed66e1bc | 162 | );\r |
913cb9dc | 163 | \r |
164 | \r | |
165 | /**\r | |
166 | Clear all the interrutp status bits, these bits\r | |
ab6495ea | 167 | are Write-Clean.\r |
913cb9dc | 168 | \r |
ab6495ea | 169 | @param Uhc The UHCI device.\r |
913cb9dc | 170 | \r |
ab6495ea | 171 | @return None.\r |
913cb9dc | 172 | \r |
173 | **/\r | |
174 | VOID\r | |
175 | UhciAckAllInterrupt (\r | |
176 | IN USB_HC_DEV *Uhc\r | |
ed66e1bc | 177 | );\r |
913cb9dc | 178 | \r |
179 | \r | |
180 | /**\r | |
ab6495ea | 181 | Stop the host controller.\r |
913cb9dc | 182 | \r |
ab6495ea | 183 | @param Uhc The UHCI device.\r |
184 | @param Timeout Max time allowed.\r | |
913cb9dc | 185 | \r |
ab6495ea | 186 | @retval EFI_SUCCESS The host controller is stopped.\r |
187 | @retval EFI_TIMEOUT Failed to stop the host controller.\r | |
913cb9dc | 188 | \r |
189 | **/\r | |
190 | EFI_STATUS\r | |
191 | UhciStopHc (\r | |
192 | IN USB_HC_DEV *Uhc,\r | |
193 | IN UINTN Timeout\r | |
ed66e1bc | 194 | );\r |
913cb9dc | 195 | \r |
196 | \r | |
197 | \r | |
198 | /**\r | |
ab6495ea | 199 | Check whether the host controller operates well.\r |
913cb9dc | 200 | \r |
ab6495ea | 201 | @param PciIo The PCI_IO protocol to use.\r |
913cb9dc | 202 | \r |
ab6495ea | 203 | @retval TRUE Host controller is working.\r |
204 | @retval FALSE Host controller is halted or system error.\r | |
913cb9dc | 205 | \r |
206 | **/\r | |
207 | BOOLEAN\r | |
208 | UhciIsHcWorking (\r | |
209 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 210 | );\r |
913cb9dc | 211 | \r |
212 | \r | |
213 | /**\r | |
214 | Set the UHCI frame list base address. It can't use\r | |
215 | UhciWriteReg which access memory in UINT16.\r | |
216 | \r | |
ab6495ea | 217 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
218 | @param Addr Address to set.\r | |
913cb9dc | 219 | \r |
ab6495ea | 220 | @return None.\r |
913cb9dc | 221 | \r |
222 | **/\r | |
223 | VOID\r | |
224 | UhciSetFrameListBaseAddr (\r | |
225 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
226 | IN VOID *Addr\r | |
ed66e1bc | 227 | );\r |
913cb9dc | 228 | \r |
229 | \r | |
230 | /**\r | |
ab6495ea | 231 | Disable USB Emulation.\r |
913cb9dc | 232 | \r |
ab6495ea | 233 | @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r |
913cb9dc | 234 | \r |
ab6495ea | 235 | @return None.\r |
913cb9dc | 236 | \r |
237 | **/\r | |
238 | VOID\r | |
239 | UhciTurnOffUsbEmulation (\r | |
240 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 241 | );\r |
913cb9dc | 242 | #endif\r |