[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

/** @file\r
\r
  This file contains the register definition of XHCI host controller.\r
\r
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_XHCI_REG_H_\r
#define _EFI_XHCI_REG_H_\r
\r
#define PCI_IF_XHCI                 0x30\r
\r
//\r
// PCI Configuration Registers\r
//\r
#define XHC_BAR_INDEX               0x00\r
\r
#define XHC_PCI_BAR_OFFSET          0x10       // Memory Bar Register Offset\r
#define XHC_PCI_BAR_MASK            0xFFFF     // Memory Base Address Mask\r
\r
#define USB_HUB_CLASS_CODE          0x09\r
#define USB_HUB_SUBCLASS_CODE       0x00\r
\r
//============================================//\r
//           XHCI register offset             //\r
//============================================//\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET               0x00 // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET              0x02 // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET              0x04 // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET              0x08 // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET              0x0c // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET               0x10 // Capability Parameters\r
#define XHC_DBOFF_OFFSET                   0x14 // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET                  0x18 // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET                  0x0000 // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET                  0x0004 // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET                0x0008 // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET                  0x0014 // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET                    0x0018 // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET                  0x0030 // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET                  0x0038 // Configure Register Offset\r
#define XHC_PORTSC_OFFSET                  0x0400 // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET                 0x00 // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET                    0x20 // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET                    0x24 // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET                  0x28 // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset\r
\r
#define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore\r
#define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8                   MaxSlots;       // Number of Device Slots\r
  UINT16                  MaxIntrs:11;    // Number of Interrupters\r
  UINT16                  Rsvd:5;\r
  UINT8                   MaxPorts;       // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS1              Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32                  Ist:4;          // Isochronous Scheduling Threshold\r
  UINT32                  Erst:4;         // Event Ring Segment Table Max\r
  UINT32                  Rsvd:13;\r
  UINT32                  ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
  UINT32                  Spr:1;          // Scratchpad Restore\r
  UINT32                  ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS2              Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16                  Ac64:1;        // 64-bit Addressing Capability\r
  UINT16                  Bnc:1;         // BW Negotiation Capability\r
  UINT16                  Csz:1;         // Context Size\r
  UINT16                  Ppc:1;         // Port Power Control\r
  UINT16                  Pind:1;        // Port Indicators\r
  UINT16                  Lhrc:1;        // Light HC Reset Capability\r
  UINT16                  Ltc:1;         // Latency Tolerance Messaging Capability\r
  UINT16                  Nss:1;         // No Secondary SID Support\r
  UINT16                  Pae:1;         // Parse All Event Data\r
  UINT16                  Rsvd:3;\r
  UINT16                  MaxPsaSize:4;  // Maximum Primary Stream Array Size\r
  UINT16                  ExtCapReg;     // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCCPARAMS               Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN                     BIT0  // Run/Stop\r
#define XHC_USBCMD_RESET                   BIT1  // Host Controller Reset\r
#define XHC_USBCMD_INTE                    BIT2  // Interrupter Enable\r
#define XHC_USBCMD_HSEE                    BIT3  // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT                    BIT0  // Host Controller Halted\r
#define XHC_USBSTS_HSE                     BIT2  // Host System Error\r
#define XHC_USBSTS_EINT                    BIT3  // Event Interrupt\r
#define XHC_USBSTS_PCD                     BIT4  // Port Change Detect\r
#define XHC_USBSTS_SSS                     BIT8  // Save State Status\r
#define XHC_USBSTS_RSS                     BIT9  // Restore State Status\r
#define XHC_USBSTS_SRE                     BIT10 // Save/Restore Error\r
#define XHC_USBSTS_CNR                     BIT11 // Host Controller Not Ready\r
#define XHC_USBSTS_HCE                     BIT12 // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK                  0xFFFF // Page Size\r
\r
#define XHC_CRCR_RCS                       BIT0  // Ring Cycle State\r
#define XHC_CRCR_CS                        BIT1  // Command Stop\r
#define XHC_CRCR_CA                        BIT2  // Command Abort\r
#define XHC_CRCR_CRR                       BIT3  // Command Ring Running\r
\r
#define XHC_CONFIG_MASK                    0xFF  // Command Ring Running\r
\r
#define XHC_PORTSC_CCS                     BIT0  // Current Connect Status\r
#define XHC_PORTSC_PED                     BIT1  // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA                     BIT3  // Over-current Active\r
#define XHC_PORTSC_RESET                   BIT4  // Port Reset\r
#define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
#define XHC_PORTSC_PP                      BIT9  // Port Power\r
#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
#define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC                     BIT17 // Connect Status Change\r
#define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC                     BIT19 // Warm Port Reset Change\r
#define XHC_PORTSC_OCC                     BIT20 // Over-Current Change\r
#define XHC_PORTSC_PRC                     BIT21 // Port Reset Change\r
#define XHC_PORTSC_PLC                     BIT22 // Port Link State Change\r
#define XHC_PORTSC_CEC                     BIT23 // Port Config Error Change\r
#define XHC_PORTSC_CAS                     BIT24 // Cold Attach Status\r
\r
#define XHC_IMAN_IP                        BIT0  // Interrupt Pending\r
#define XHC_IMAN_IE                        BIT1  // Interrupt Enable\r
\r
#define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
/**\r
  Read 1-byte width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 1-byte width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFF.\r
\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI Operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width operational register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadOpReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the 4-bytes width XHCI operational register.\r
\r
  @param  Xhc      The XHCI Instance.\r
  @param  Offset   The offset of the 4-bytes width operational register.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Write the data to the 2-bytes width XHCI operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 2-bytes width operational register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg16 (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT16               Data\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Read XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadDoorBellReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit of the register to wait for.\r
  @param  WaitToSet    Wait the bit to set or clear.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT  The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit,\r
  IN BOOLEAN              WaitToSet,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Whether the XHCI host controller is halted.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Xhc      The XHCI Instance.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Reset the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The XHCI host controller is reset.\r
  @return Others       Failed to reset the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Halt the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is halt.\r
  @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
  IN USB_XHCI_INSTANCE   *Xhc,\r
  IN UINT32              Timeout\r
  );\r
\r
/**\r
  Set the XHCI host controller to run.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is running.\r
  @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Calculate the XHCI legacy support capability register offset.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetLegSupCapAddr (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
#endif\r
Commit	Line	Data
92870c98	1	/** @file\r
	2	\r
	3	This file contains the register definition of XHCI host controller.\r
	4	\r
	5	Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _EFI_XHCI_REG_H_\r
	17	#define _EFI_XHCI_REG_H_\r
	18	\r
	19	#define PCI_IF_XHCI 0x30\r
	20	\r
	21	//\r
	22	// PCI Configuration Registers\r
	23	//\r
	24	#define XHC_BAR_INDEX 0x00\r
	25	\r
	26	#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
	27	#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
	28	\r
	29	#define USB_HUB_CLASS_CODE 0x09\r
	30	#define USB_HUB_SUBCLASS_CODE 0x00\r
	31	\r
	32	//============================================//\r
	33	// XHCI register offset //\r
	34	//============================================//\r
	35	\r
	36	//\r
	37	// Capability registers offset\r
	38	//\r
	39	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	40	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	41	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	42	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	43	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	44	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	45	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	46	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
	47	\r
	48	//\r
	49	// Operational registers offset\r
	50	//\r
	51	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	52	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	53	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	54	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	55	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	56	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	57	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	58	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
	59	\r
	60	//\r
	61	// Runtime registers offset\r
	62	//\r
	63	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	64	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
65	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
66	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
67	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
68	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
69	\r
70	#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
71	#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
72	\r
73	#pragma pack (1)\r
a9292c13	74	typedef struct {\r
	75	UINT8 MaxSlots; // Number of Device Slots\r
	76	UINT16 MaxIntrs:11; // Number of Interrupters\r
	77	UINT16 Rsvd:5;\r
	78	UINT8 MaxPorts; // Number of Ports\r
	79	} HCSPARAMS1;\r
	80	\r
92870c98	81	//\r
	82	// Structural Parameters 1 Register Bitmap Definition\r
	83	//\r
a9292c13	84	typedef union {\r
	85	UINT32 Dword;\r
	86	HCSPARAMS1 Data;\r
92870c98	87	} XHC_HCSPARAMS1;\r
92870c98	88	\r
a9292c13	89	typedef struct {\r
	90	UINT32 Ist:4; // Isochronous Scheduling Threshold\r
	91	UINT32 Erst:4; // Event Ring Segment Table Max\r
	92	UINT32 Rsvd:13;\r
	93	UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
	94	UINT32 Spr:1; // Scratchpad Restore\r
	95	UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
	96	} HCSPARAMS2;\r
	97	\r
92870c98	98	//\r
	99	// Structural Parameters 2 Register Bitmap Definition\r
	100	//\r
a9292c13	101	typedef union {\r
	102	UINT32 Dword;\r
	103	HCSPARAMS2 Data;\r
92870c98	104	} XHC_HCSPARAMS2;\r
92870c98	105	\r
a9292c13	106	typedef struct {\r
	107	UINT16 Ac64:1; // 64-bit Addressing Capability\r
	108	UINT16 Bnc:1; // BW Negotiation Capability\r
	109	UINT16 Csz:1; // Context Size\r
	110	UINT16 Ppc:1; // Port Power Control\r
	111	UINT16 Pind:1; // Port Indicators\r
	112	UINT16 Lhrc:1; // Light HC Reset Capability\r
	113	UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
	114	UINT16 Nss:1; // No Secondary SID Support\r
	115	UINT16 Pae:1; // Parse All Event Data\r
	116	UINT16 Rsvd:3;\r
	117	UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
	118	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
	119	} HCCPARAMS;\r
	120	\r
92870c98	121	//\r
	122	// Capability Parameters Register Bitmap Definition\r
	123	//\r
a9292c13	124	typedef union {\r
	125	UINT32 Dword;\r
	126	HCCPARAMS Data;\r
92870c98	127	} XHC_HCCPARAMS;\r
	128	\r
	129	#pragma pack ()\r
	130	\r
	131	//\r
	132	// Register Bit Definition\r
	133	//\r
	134	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	135	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	136	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	137	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	138	\r
	139	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	140	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	141	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
	142	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
	143	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
	144	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
	145	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
	146	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
	147	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
	148	\r
	149	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
	150	\r
	151	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
	152	#define XHC_CRCR_CS BIT1 // Command Stop\r
	153	#define XHC_CRCR_CA BIT2 // Command Abort\r
	154	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
	155	\r
	156	#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
	157	\r
	158	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
	159	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
	160	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
	161	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
	162	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
	163	#define XHC_PORTSC_PP BIT9 // Port Power\r
	164	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12\|BIT13) // Port Speed\r
	165	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
	166	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
	167	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
	168	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
	169	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
	170	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
	171	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
	172	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
	173	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
	174	\r
	175	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
	176	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
	177	\r
	178	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
	179	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
	180	\r
	181	//\r
	182	// Structure to map the hardware port states to the\r
	183	// UEFI's port states.\r
	184	//\r
	185	typedef struct {\r
	186	UINT32 HwState;\r
	187	UINT16 UefiState;\r
	188	} USB_PORT_STATE_MAP;\r
	189	\r
	190	/**\r
191	Read 1-byte width XHCI capability register.\r
192	\r
a9292c13	193	@param Xhc The XHCI Instance.\r
92870c98	194	@param Offset The offset of the 1-byte width capability register.\r
	195	\r
	196	@return The register content read.\r
	197	@retval If err, return 0xFFFF.\r
	198	\r
	199	**/\r
	200	UINT8\r
	201	XhcReadCapReg8 (\r
a9292c13	202	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	203	IN UINT32 Offset\r
	204	);\r
	205	\r
	206	/**\r
	207	Read 4-bytes width XHCI capability register.\r
	208	\r
a9292c13	209	@param Xhc The XHCI Instance.\r
92870c98	210	@param Offset The offset of the 4-bytes width capability register.\r
	211	\r
	212	@return The register content read.\r
	213	@retval If err, return 0xFFFFFFFF.\r
	214	\r
	215	**/\r
	216	UINT32\r
	217	XhcReadCapReg (\r
a9292c13	218	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	219	IN UINT32 Offset\r
	220	);\r
	221	\r
	222	/**\r
	223	Read 4-bytes width XHCI Operational register.\r
	224	\r
a9292c13	225	@param Xhc The XHCI Instance.\r
92870c98	226	@param Offset The offset of the 4-bytes width operational register.\r
	227	\r
	228	@return The register content read.\r
	229	@retval If err, return 0xFFFFFFFF.\r
	230	\r
	231	**/\r
	232	UINT32\r
	233	XhcReadOpReg (\r
a9292c13	234	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	235	IN UINT32 Offset\r
	236	);\r
	237	\r
	238	/**\r
	239	Write the data to the 4-bytes width XHCI operational register.\r
	240	\r
a9292c13	241	@param Xhc The XHCI Instance.\r
92870c98	242	@param Offset The offset of the 4-bytes width operational register.\r
	243	@param Data The data to write.\r
	244	\r
	245	**/\r
	246	VOID\r
	247	XhcWriteOpReg (\r
a9292c13	248	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	249	IN UINT32 Offset,\r
	250	IN UINT32 Data\r
	251	);\r
	252	\r
	253	/**\r
	254	Write the data to the 2-bytes width XHCI operational register.\r
	255	\r
a9292c13	256	@param Xhc The XHCI Instance.\r
92870c98	257	@param Offset The offset of the 2-bytes width operational register.\r
	258	@param Data The data to write.\r
	259	\r
	260	**/\r
	261	VOID\r
	262	XhcWriteOpReg16 (\r
a9292c13	263	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	264	IN UINT32 Offset,\r
	265	IN UINT16 Data\r
	266	);\r
	267	\r
92870c98	268	/**\r
	269	Read XHCI runtime register.\r
	270	\r
a9292c13	271	@param Xhc The XHCI Instance.\r
92870c98	272	@param Offset The offset of the runtime register.\r
	273	\r
	274	@return The register content read\r
	275	\r
	276	**/\r
	277	UINT32\r
	278	XhcReadRuntimeReg (\r
a9292c13	279	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	280	IN UINT32 Offset\r
	281	);\r
	282	\r
92870c98	283	/**\r
	284	Write the data to the XHCI runtime register.\r
	285	\r
a9292c13	286	@param Xhc The XHCI Instance.\r
92870c98	287	@param Offset The offset of the runtime register.\r
	288	@param Data The data to write.\r
	289	\r
	290	**/\r
	291	VOID\r
	292	XhcWriteRuntimeReg (\r
a9292c13	293	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	294	IN UINT32 Offset,\r
	295	IN UINT32 Data\r
	296	);\r
	297	\r
92870c98	298	/**\r
	299	Read XHCI door bell register.\r
	300	\r
a9292c13	301	@param Xhc The XHCI Instance.\r
92870c98	302	@param Offset The offset of the door bell register.\r
	303	\r
	304	@return The register content read\r
	305	\r
	306	**/\r
	307	UINT32\r
	308	XhcReadDoorBellReg (\r
a9292c13	309	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	310	IN UINT32 Offset\r
	311	);\r
	312	\r
	313	/**\r
	314	Write the data to the XHCI door bell register.\r
	315	\r
a9292c13	316	@param Xhc The XHCI Instance.\r
92870c98	317	@param Offset The offset of the door bell register.\r
	318	@param Data The data to write.\r
	319	\r
	320	**/\r
	321	VOID\r
	322	XhcWriteDoorBellReg (\r
a9292c13	323	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	324	IN UINT32 Offset,\r
	325	IN UINT32 Data\r
	326	);\r
	327	\r
	328	/**\r
	329	Set one bit of the operational register while keeping other bits.\r
	330	\r
a9292c13	331	@param Xhc The XHCI Instance.\r
92870c98	332	@param Offset The offset of the operational register.\r
	333	@param Bit The bit mask of the register to set.\r
	334	\r
	335	**/\r
	336	VOID\r
	337	XhcSetOpRegBit (\r
a9292c13	338	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	339	IN UINT32 Offset,\r
	340	IN UINT32 Bit\r
	341	);\r
	342	\r
	343	/**\r
	344	Clear one bit of the operational register while keeping other bits.\r
	345	\r
a9292c13	346	@param Xhc The XHCI Instance.\r
92870c98	347	@param Offset The offset of the operational register.\r
	348	@param Bit The bit mask of the register to clear.\r
	349	\r
	350	**/\r
	351	VOID\r
	352	XhcClearOpRegBit (\r
a9292c13	353	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	354	IN UINT32 Offset,\r
	355	IN UINT32 Bit\r
	356	);\r
	357	\r
	358	/**\r
	359	Wait the operation register's bit as specified by Bit\r
	360	to be set (or clear).\r
	361	\r
a9292c13	362	@param Xhc The XHCI Instance.\r
92870c98	363	@param Offset The offset of the operational register.\r
	364	@param Bit The bit of the register to wait for.\r
	365	@param WaitToSet Wait the bit to set or clear.\r
	366	@param Timeout The time to wait before abort (in millisecond, ms).\r
	367	\r
	368	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
	369	@retval EFI_TIMEOUT The time out occurred.\r
	370	\r
	371	**/\r
	372	EFI_STATUS\r
	373	XhcWaitOpRegBit (\r
a9292c13	374	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	375	IN UINT32 Offset,\r
	376	IN UINT32 Bit,\r
	377	IN BOOLEAN WaitToSet,\r
	378	IN UINT32 Timeout\r
	379	);\r
	380	\r
	381	/**\r
	382	Read XHCI runtime register.\r
	383	\r
a9292c13	384	@param Xhc The XHCI Instance.\r
92870c98	385	@param Offset The offset of the runtime register.\r
	386	\r
	387	@return The register content read\r
	388	\r
	389	**/\r
	390	UINT32\r
	391	XhcReadRuntimeReg (\r
a9292c13	392	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	393	IN UINT32 Offset\r
	394	);\r
	395	\r
	396	/**\r
	397	Write the data to the XHCI runtime register.\r
	398	\r
a9292c13	399	@param Xhc The XHCI Instance.\r
92870c98	400	@param Offset The offset of the runtime register.\r
	401	@param Data The data to write.\r
	402	\r
	403	**/\r
	404	VOID\r
	405	XhcWriteRuntimeReg (\r
a9292c13	406	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	407	IN UINT32 Offset,\r
	408	IN UINT32 Data\r
	409	);\r
	410	\r
	411	/**\r
	412	Set one bit of the runtime register while keeping other bits.\r
	413	\r
a9292c13	414	@param Xhc The XHCI Instance.\r
92870c98	415	@param Offset The offset of the runtime register.\r
	416	@param Bit The bit mask of the register to set.\r
	417	\r
	418	**/\r
	419	VOID\r
	420	XhcSetRuntimeRegBit (\r
a9292c13	421	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	422	IN UINT32 Offset,\r
	423	IN UINT32 Bit\r
	424	);\r
	425	\r
	426	/**\r
	427	Clear one bit of the runtime register while keeping other bits.\r
	428	\r
a9292c13	429	@param Xhc The XHCI Instance.\r
92870c98	430	@param Offset The offset of the runtime register.\r
	431	@param Bit The bit mask of the register to set.\r
	432	\r
	433	**/\r
	434	VOID\r
	435	XhcClearRuntimeRegBit (\r
a9292c13	436	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	437	IN UINT32 Offset,\r
	438	IN UINT32 Bit\r
	439	);\r
	440	\r
	441	/**\r
	442	Whether the XHCI host controller is halted.\r
	443	\r
a9292c13	444	@param Xhc The XHCI Instance.\r
92870c98	445	\r
	446	@retval TRUE The controller is halted.\r
	447	@retval FALSE It isn't halted.\r
	448	\r
	449	**/\r
	450	BOOLEAN\r
	451	XhcIsHalt (\r
a9292c13	452	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	453	);\r
	454	\r
	455	/**\r
	456	Whether system error occurred.\r
	457	\r
a9292c13	458	@param Xhc The XHCI Instance.\r
92870c98	459	\r
	460	@retval TRUE System error happened.\r
	461	@retval FALSE No system error.\r
	462	\r
	463	**/\r
	464	BOOLEAN\r
	465	XhcIsSysError (\r
a9292c13	466	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	467	);\r
	468	\r
	469	/**\r
	470	Reset the XHCI host controller.\r
	471	\r
a9292c13	472	@param Xhc The XHCI Instance.\r
92870c98	473	@param Timeout Time to wait before abort (in millisecond, ms).\r
	474	\r
	475	@retval EFI_SUCCESS The XHCI host controller is reset.\r
	476	@return Others Failed to reset the XHCI before Timeout.\r
	477	\r
	478	**/\r
	479	EFI_STATUS\r
	480	XhcResetHC (\r
a9292c13	481	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	482	IN UINT32 Timeout\r
	483	);\r
	484	\r
	485	/**\r
	486	Halt the XHCI host controller.\r
	487	\r
a9292c13	488	@param Xhc The XHCI Instance.\r
92870c98	489	@param Timeout Time to wait before abort (in millisecond, ms).\r
	490	\r
	491	@return EFI_SUCCESS The XHCI host controller is halt.\r
	492	@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r
	493	\r
	494	**/\r
	495	EFI_STATUS\r
	496	XhcHaltHC (\r
a9292c13	497	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	498	IN UINT32 Timeout\r
	499	);\r
	500	\r
	501	/**\r
	502	Set the XHCI host controller to run.\r
	503	\r
a9292c13	504	@param Xhc The XHCI Instance.\r
92870c98	505	@param Timeout Time to wait before abort (in millisecond, ms).\r
	506	\r
	507	@return EFI_SUCCESS The XHCI host controller is running.\r
	508	@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r
	509	\r
	510	**/\r
	511	EFI_STATUS\r
	512	XhcRunHC (\r
a9292c13	513	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	514	IN UINT32 Timeout\r
	515	);\r
	516	\r
	517	/**\r
	518	Calculate the XHCI legacy support capability register offset.\r
	519	\r
a9292c13	520	@param Xhc The XHCI Instance.\r
92870c98	521	\r
	522	@return The offset of XHCI legacy support capability register.\r
	523	\r
	524	**/\r
	525	UINT32\r
	526	XhcGetLegSupCapAddr (\r
a9292c13	527	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	528	);\r
	529	\r
	530	#endif\r