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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
3 This file contains the register definition of XHCI host controller.
5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_XHCI_REG_H_
17 #define _EFI_XHCI_REG_H_
19 #define PCI_IF_XHCI 0x30
22 // PCI Configuration Registers
24 #define XHC_BAR_INDEX 0x00
26 #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
27 #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
29 #define USB_HUB_CLASS_CODE 0x09
30 #define USB_HUB_SUBCLASS_CODE 0x00
32 //============================================//
33 // XHCI register offset //
34 //============================================//
37 // Capability registers offset
39 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
40 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
41 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
42 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
43 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
44 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
45 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
46 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
49 // Operational registers offset
51 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
52 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
53 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
54 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
55 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
56 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
57 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
58 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
61 // Runtime registers offset
63 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
64 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
65 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
66 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
67 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
68 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
70 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
71 #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
75 UINT8 MaxSlots
; // Number of Device Slots
76 UINT16 MaxIntrs
:11; // Number of Interrupters
78 UINT8 MaxPorts
; // Number of Ports
82 // Structural Parameters 1 Register Bitmap Definition
90 UINT32 Ist
:4; // Isochronous Scheduling Threshold
91 UINT32 Erst
:4; // Event Ring Segment Table Max
93 UINT32 ScratchBufHi
:5; // Max Scratchpad Buffers Hi
94 UINT32 Spr
:1; // Scratchpad Restore
95 UINT32 ScratchBufLo
:5; // Max Scratchpad Buffers Lo
99 // Structural Parameters 2 Register Bitmap Definition
107 UINT16 Ac64
:1; // 64-bit Addressing Capability
108 UINT16 Bnc
:1; // BW Negotiation Capability
109 UINT16 Csz
:1; // Context Size
110 UINT16 Ppc
:1; // Port Power Control
111 UINT16 Pind
:1; // Port Indicators
112 UINT16 Lhrc
:1; // Light HC Reset Capability
113 UINT16 Ltc
:1; // Latency Tolerance Messaging Capability
114 UINT16 Nss
:1; // No Secondary SID Support
115 UINT16 Pae
:1; // Parse All Event Data
117 UINT16 MaxPsaSize
:4; // Maximum Primary Stream Array Size
118 UINT16 ExtCapReg
; // xHCI Extended Capabilities Pointer
122 // Capability Parameters Register Bitmap Definition
132 // Register Bit Definition
134 #define XHC_USBCMD_RUN BIT0 // Run/Stop
135 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
136 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
137 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
139 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
140 #define XHC_USBSTS_HSE BIT2 // Host System Error
141 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
142 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
143 #define XHC_USBSTS_SSS BIT8 // Save State Status
144 #define XHC_USBSTS_RSS BIT9 // Restore State Status
145 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
146 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
147 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
149 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
151 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
152 #define XHC_CRCR_CS BIT1 // Command Stop
153 #define XHC_CRCR_CA BIT2 // Command Abort
154 #define XHC_CRCR_CRR BIT3 // Command Ring Running
156 #define XHC_CONFIG_MASK 0xFF // Command Ring Running
158 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
159 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
160 #define XHC_PORTSC_OCA BIT3 // Over-current Active
161 #define XHC_PORTSC_RESET BIT4 // Port Reset
162 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
163 #define XHC_PORTSC_PP BIT9 // Port Power
164 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
165 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
166 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
167 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
168 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
169 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
170 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
171 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
172 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
173 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
175 #define XHC_IMAN_IP BIT0 // Interrupt Pending
176 #define XHC_IMAN_IE BIT1 // Interrupt Enable
178 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
179 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
182 // Structure to map the hardware port states to the
183 // UEFI's port states.
188 } USB_PORT_STATE_MAP
;
191 Read 1-byte width XHCI capability register.
193 @param Xhc The XHCI Instance.
194 @param Offset The offset of the 1-byte width capability register.
196 @return The register content read.
197 @retval If err, return 0xFFFF.
202 IN USB_XHCI_INSTANCE
*Xhc
,
207 Read 4-bytes width XHCI capability register.
209 @param Xhc The XHCI Instance.
210 @param Offset The offset of the 4-bytes width capability register.
212 @return The register content read.
213 @retval If err, return 0xFFFFFFFF.
218 IN USB_XHCI_INSTANCE
*Xhc
,
223 Read 4-bytes width XHCI Operational register.
225 @param Xhc The XHCI Instance.
226 @param Offset The offset of the 4-bytes width operational register.
228 @return The register content read.
229 @retval If err, return 0xFFFFFFFF.
234 IN USB_XHCI_INSTANCE
*Xhc
,
239 Write the data to the 4-bytes width XHCI operational register.
241 @param Xhc The XHCI Instance.
242 @param Offset The offset of the 4-bytes width operational register.
243 @param Data The data to write.
248 IN USB_XHCI_INSTANCE
*Xhc
,
254 Write the data to the 2-bytes width XHCI operational register.
256 @param Xhc The XHCI Instance.
257 @param Offset The offset of the 2-bytes width operational register.
258 @param Data The data to write.
263 IN USB_XHCI_INSTANCE
*Xhc
,
269 Read XHCI runtime register.
271 @param Xhc The XHCI Instance.
272 @param Offset The offset of the runtime register.
274 @return The register content read
279 IN USB_XHCI_INSTANCE
*Xhc
,
284 Write the data to the XHCI runtime register.
286 @param Xhc The XHCI Instance.
287 @param Offset The offset of the runtime register.
288 @param Data The data to write.
293 IN USB_XHCI_INSTANCE
*Xhc
,
299 Read XHCI door bell register.
301 @param Xhc The XHCI Instance.
302 @param Offset The offset of the door bell register.
304 @return The register content read
309 IN USB_XHCI_INSTANCE
*Xhc
,
314 Write the data to the XHCI door bell register.
316 @param Xhc The XHCI Instance.
317 @param Offset The offset of the door bell register.
318 @param Data The data to write.
322 XhcWriteDoorBellReg (
323 IN USB_XHCI_INSTANCE
*Xhc
,
329 Set one bit of the operational register while keeping other bits.
331 @param Xhc The XHCI Instance.
332 @param Offset The offset of the operational register.
333 @param Bit The bit mask of the register to set.
338 IN USB_XHCI_INSTANCE
*Xhc
,
344 Clear one bit of the operational register while keeping other bits.
346 @param Xhc The XHCI Instance.
347 @param Offset The offset of the operational register.
348 @param Bit The bit mask of the register to clear.
353 IN USB_XHCI_INSTANCE
*Xhc
,
359 Wait the operation register's bit as specified by Bit
360 to be set (or clear).
362 @param Xhc The XHCI Instance.
363 @param Offset The offset of the operational register.
364 @param Bit The bit of the register to wait for.
365 @param WaitToSet Wait the bit to set or clear.
366 @param Timeout The time to wait before abort (in millisecond, ms).
368 @retval EFI_SUCCESS The bit successfully changed by host controller.
369 @retval EFI_TIMEOUT The time out occurred.
374 IN USB_XHCI_INSTANCE
*Xhc
,
377 IN BOOLEAN WaitToSet
,
382 Read XHCI runtime register.
384 @param Xhc The XHCI Instance.
385 @param Offset The offset of the runtime register.
387 @return The register content read
392 IN USB_XHCI_INSTANCE
*Xhc
,
397 Write the data to the XHCI runtime register.
399 @param Xhc The XHCI Instance.
400 @param Offset The offset of the runtime register.
401 @param Data The data to write.
406 IN USB_XHCI_INSTANCE
*Xhc
,
412 Set one bit of the runtime register while keeping other bits.
414 @param Xhc The XHCI Instance.
415 @param Offset The offset of the runtime register.
416 @param Bit The bit mask of the register to set.
420 XhcSetRuntimeRegBit (
421 IN USB_XHCI_INSTANCE
*Xhc
,
427 Clear one bit of the runtime register while keeping other bits.
429 @param Xhc The XHCI Instance.
430 @param Offset The offset of the runtime register.
431 @param Bit The bit mask of the register to set.
435 XhcClearRuntimeRegBit (
436 IN USB_XHCI_INSTANCE
*Xhc
,
442 Whether the XHCI host controller is halted.
444 @param Xhc The XHCI Instance.
446 @retval TRUE The controller is halted.
447 @retval FALSE It isn't halted.
452 IN USB_XHCI_INSTANCE
*Xhc
456 Whether system error occurred.
458 @param Xhc The XHCI Instance.
460 @retval TRUE System error happened.
461 @retval FALSE No system error.
466 IN USB_XHCI_INSTANCE
*Xhc
470 Reset the XHCI host controller.
472 @param Xhc The XHCI Instance.
473 @param Timeout Time to wait before abort (in millisecond, ms).
475 @retval EFI_SUCCESS The XHCI host controller is reset.
476 @return Others Failed to reset the XHCI before Timeout.
481 IN USB_XHCI_INSTANCE
*Xhc
,
486 Halt the XHCI host controller.
488 @param Xhc The XHCI Instance.
489 @param Timeout Time to wait before abort (in millisecond, ms).
491 @return EFI_SUCCESS The XHCI host controller is halt.
492 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
497 IN USB_XHCI_INSTANCE
*Xhc
,
502 Set the XHCI host controller to run.
504 @param Xhc The XHCI Instance.
505 @param Timeout Time to wait before abort (in millisecond, ms).
507 @return EFI_SUCCESS The XHCI host controller is running.
508 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
513 IN USB_XHCI_INSTANCE
*Xhc
,
518 Calculate the XHCI legacy support capability register offset.
520 @param Xhc The XHCI Instance.
522 @return The offset of XHCI legacy support capability register.
526 XhcGetLegSupCapAddr (
527 IN USB_XHCI_INSTANCE
*Xhc