[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhcPeim.c

/** @file\r
PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid\r
which is used to enable recovery function from USB Drivers.\r
\r
Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "XhcPeim.h"\r
\r
//\r
// Two arrays used to translate the XHCI port state (change)\r
// to the UEFI protocol's port state (change).\r
//\r
USB_PORT_STATE_MAP  mUsbPortStateMap[] = {\r
  {XHC_PORTSC_CCS,   USB_PORT_STAT_CONNECTION},\r
  {XHC_PORTSC_PED,   USB_PORT_STAT_ENABLE},\r
  {XHC_PORTSC_OCA,   USB_PORT_STAT_OVERCURRENT},\r
  {XHC_PORTSC_PP,    USB_PORT_STAT_POWER},\r
  {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}\r
};\r
\r
USB_PORT_STATE_MAP  mUsbPortChangeMap[] = {\r
  {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},\r
  {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},\r
  {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},\r
  {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}\r
};\r
\r
USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {\r
  {XHC_PORTSC_CSC, EfiUsbPortConnectChange},\r
  {XHC_PORTSC_PEC, EfiUsbPortEnableChange},\r
  {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},\r
  {XHC_PORTSC_PRC, EfiUsbPortResetChange}\r
};\r
\r
USB_PORT_STATE_MAP  mUsbHubPortStateMap[] = {\r
  {XHC_HUB_PORTSC_CCS,   USB_PORT_STAT_CONNECTION},\r
  {XHC_HUB_PORTSC_PED,   USB_PORT_STAT_ENABLE},\r
  {XHC_HUB_PORTSC_OCA,   USB_PORT_STAT_OVERCURRENT},\r
  {XHC_HUB_PORTSC_PP,    USB_PORT_STAT_POWER},\r
  {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}\r
};\r
\r
USB_PORT_STATE_MAP  mUsbHubPortChangeMap[] = {\r
  {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},\r
  {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},\r
  {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},\r
  {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}\r
};\r
\r
USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {\r
  {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},\r
  {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},\r
  {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},\r
  {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},\r
  {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}\r
};\r
\r
/**\r
  Read XHCI Operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
\r
  @retval the register content read.\r
\r
**/\r
UINT32\r
XhcPeiReadOpReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset\r
  )\r
{\r
  UINT32                Data;\r
\r
  ASSERT (Xhc->CapLength != 0);\r
\r
  Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset);\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the XHCI operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
  @param Data           The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteOpReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  )\r
{\r
  ASSERT (Xhc->CapLength != 0);\r
\r
  MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data);\r
}\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32                Data;\r
\r
  Data  = XhcPeiReadOpReg (Xhc, Offset);\r
  Data |= Bit;\r
  XhcPeiWriteOpReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcPeiClearOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32                Data;\r
\r
  Data  = XhcPeiReadOpReg (Xhc, Offset);\r
  Data &= ~Bit;\r
  XhcPeiWriteOpReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to become set (or clear).\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to wait for.\r
  @param  WaitToSet     Wait the bit to set or clear.\r
  @param  Timeout       The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS   The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT   The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcPeiWaitOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit,\r
  IN BOOLEAN            WaitToSet,\r
  IN UINT32             Timeout\r
  )\r
{\r
  UINT64                Index;\r
\r
  for (Index = 0; Index < Timeout * XHC_1_MILLISECOND; Index++) {\r
    if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
      return EFI_SUCCESS;\r
    }\r
\r
    MicroSecondDelay (XHC_1_MICROSECOND);\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Read XHCI capability register.\r
\r
  @param Xhc        The XHCI device.\r
  @param Offset     Capability register address.\r
\r
  @retval the register content read.\r
\r
**/\r
UINT32\r
XhcPeiReadCapRegister (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset\r
  )\r
{\r
  UINT32                Data;\r
\r
  Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset);\r
\r
  return Data;\r
}\r
\r
/**\r
  Read XHCI door bell register.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  Offset    The offset of the door bell register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcPeiReadDoorBellReg (\r
  IN  PEI_XHC_DEV       *Xhc,\r
  IN  UINT32            Offset\r
  )\r
{\r
  UINT32                  Data;\r
\r
  ASSERT (Xhc->DBOff != 0);\r
\r
  Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset);\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the door bell register.\r
  @param  Data          The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteDoorBellReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  )\r
{\r
  ASSERT (Xhc->DBOff != 0);\r
\r
  MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data);\r
}\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcPeiReadRuntimeReg (\r
  IN  PEI_XHC_DEV       *Xhc,\r
  IN  UINT32            Offset\r
  )\r
{\r
  UINT32                Data;\r
\r
  ASSERT (Xhc->RTSOff != 0);\r
\r
  Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset);\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  Offset    The offset of the runtime register.\r
  @param  Data      The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteRuntimeReg (\r
  IN PEI_XHC_DEV          *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  )\r
{\r
  ASSERT (Xhc->RTSOff != 0);\r
\r
  MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data);\r
}\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI device.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetRuntimeRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32                Data;\r
\r
  Data  = XhcPeiReadRuntimeReg (Xhc, Offset);\r
  Data |= Bit;\r
  XhcPeiWriteRuntimeReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI device.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiClearRuntimeRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32                Data;\r
\r
  Data  = XhcPeiReadRuntimeReg (Xhc, Offset);\r
  Data &= ~Bit;\r
  XhcPeiWriteRuntimeReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Check whether Xhc is halted.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          The controller is halted.\r
  @retval FALSE         The controller isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsHalt (\r
  IN PEI_XHC_DEV        *Xhc\r
  )\r
{\r
  return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);\r
}\r
\r
/**\r
  Check whether system error occurred.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          System error happened.\r
  @retval FALSE         No system error.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsSysError (\r
  IN PEI_XHC_DEV        *Xhc\r
  )\r
{\r
  return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);\r
}\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_TIMEOUT   The transfer failed due to time out.\r
  @retval Others        Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
XhcPeiResetHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  )\r
{\r
  EFI_STATUS            Status;\r
\r
  //\r
  // Host can only be reset when it is halt. If not so, halt it\r
  //\r
  if (!XhcPeiIsHalt (Xhc)) {\r
    Status = XhcPeiHaltHC (Xhc, Timeout);\r
\r
    if (EFI_ERROR (Status)) {\r
      goto ON_EXIT;\r
    }\r
  }\r
\r
  XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
  //\r
  // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.\r
  // Otherwise there may have the timeout case happened.\r
  // The below is a workaround to solve such problem.\r
  //\r
  MicroSecondDelay (1000);\r
  Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
ON_EXIT:\r
  DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status));\r
  return Status;\r
}\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_TIMEOUT   Failed to halt the controller before Timeout.\r
  @retval EFI_SUCCESS   The XHCI is halt.\r
\r
**/\r
EFI_STATUS\r
XhcPeiHaltHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  )\r
{\r
  EFI_STATUS            Status;\r
\r
  XhcPeiClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r
  Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);\r
  DEBUG ((EFI_D_INFO, "XhcPeiHaltHC: %r\n", Status));\r
  return Status;\r
}\r
\r
/**\r
  Set the XHCI to run.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_SUCCESS   The XHCI is running.\r
  @retval Others        Failed to set the XHCI to run.\r
\r
**/\r
EFI_STATUS\r
XhcPeiRunHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  )\r
{\r
  EFI_STATUS            Status;\r
\r
  XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r
  Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);\r
  DEBUG ((EFI_D_INFO, "XhcPeiRunHC: %r\n", Status));\r
  return Status;\r
}\r
\r
/**\r
  Submits control transfer to a target USB device.\r
\r
  @param  PeiServices               The pointer of EFI_PEI_SERVICES.\r
  @param  This                      The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r
  @param  DeviceAddress             The target device address.\r
  @param  DeviceSpeed               Target device speed.\r
  @param  MaximumPacketLength       Maximum packet size the default control transfer\r
                                    endpoint is capable of sending or receiving.\r
  @param  Request                   USB device request to send.\r
  @param  TransferDirection         Specifies the data direction for the data stage.\r
  @param  Data                      Data buffer to be transmitted or received from USB device.\r
  @param  DataLength                The size (in bytes) of the data buffer.\r
  @param  TimeOut                   Indicates the maximum timeout, in millisecond.\r
                                    If Timeout is 0, then the caller must wait for the function\r
                                    to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.\r
  @param  Translator                Transaction translator to be used by this device.\r
  @param  TransferResult            Return the result of this control transfer.\r
\r
  @retval EFI_SUCCESS               Transfer was completed successfully.\r
  @retval EFI_OUT_OF_RESOURCES      The transfer failed due to lack of resources.\r
  @retval EFI_INVALID_PARAMETER     Some parameters are invalid.\r
  @retval EFI_TIMEOUT               Transfer failed due to timeout.\r
  @retval EFI_DEVICE_ERROR          Transfer failed due to host controller or device error.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiControlTransfer (\r
  IN EFI_PEI_SERVICES                       **PeiServices,\r
  IN PEI_USB2_HOST_CONTROLLER_PPI           *This,\r
  IN UINT8                                  DeviceAddress,\r
  IN UINT8                                  DeviceSpeed,\r
  IN UINTN                                  MaximumPacketLength,\r
  IN EFI_USB_DEVICE_REQUEST                 *Request,\r
  IN EFI_USB_DATA_DIRECTION                 TransferDirection,\r
  IN OUT VOID                               *Data,\r
  IN OUT UINTN                              *DataLength,\r
  IN UINTN                                  TimeOut,\r
  IN EFI_USB2_HC_TRANSACTION_TRANSLATOR     *Translator,\r
  OUT UINT32                                *TransferResult\r
  )\r
{\r
  PEI_XHC_DEV                   *Xhc;\r
  URB                           *Urb;\r
  UINT8                         Endpoint;\r
  UINT8                         Index;\r
  UINT8                         DescriptorType;\r
  UINT8                         SlotId;\r
  UINT8                         TTT;\r
  UINT8                         MTT;\r
  UINT32                        MaxPacket0;\r
  EFI_USB_HUB_DESCRIPTOR        *HubDesc;\r
  EFI_STATUS                    Status;\r
  EFI_STATUS                    RecoveryStatus;\r
  UINTN                         MapSize;\r
  EFI_USB_PORT_STATUS           PortStatus;\r
  UINT32                        State;\r
  EFI_USB_DEVICE_REQUEST        ClearPortRequest;\r
  UINTN                         Len;\r
\r
  //\r
  // Validate parameters\r
  //\r
  if ((Request == NULL) || (TransferResult == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((TransferDirection != EfiUsbDataIn) &&\r
      (TransferDirection != EfiUsbDataOut) &&\r
      (TransferDirection != EfiUsbNoData)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((TransferDirection == EfiUsbNoData) &&\r
      ((Data != NULL) || (*DataLength != 0))) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((TransferDirection != EfiUsbNoData) &&\r
     ((Data == NULL) || (*DataLength == 0))) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((MaximumPacketLength != 8)  && (MaximumPacketLength != 16) &&\r
      (MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&\r
      (MaximumPacketLength != 512)\r
      ) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength != 512)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Xhc             = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r
\r
  Status          = EFI_DEVICE_ERROR;\r
  *TransferResult = EFI_USB_ERR_SYSTEM;\r
  Len             = 0;\r
\r
  if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: HC is halted or has system error\n"));\r
    goto ON_EXIT;\r
  }\r
\r
  //\r
  // Check if the device is still enabled before every transaction.\r
  //\r
  SlotId = XhcPeiBusDevAddrToSlotId (Xhc, DeviceAddress);\r
  if (SlotId == 0) {\r
    goto ON_EXIT;\r
  }\r
\r
  //\r
  // Hook the Set_Address request from UsbBus.\r
  // According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.\r
  //\r
  if ((Request->Request     == USB_REQ_SET_ADDRESS) &&\r
      (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {\r
    //\r
    // Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.\r
    // This way is used to clean the history to avoid using wrong device address afterwards.\r
    //\r
    for (Index = 0; Index < 255; Index++) {\r
      if (!Xhc->UsbDevContext[Index + 1].Enabled &&\r
          (Xhc->UsbDevContext[Index + 1].SlotId == 0) &&\r
          (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8) Request->Value)) {\r
        Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;\r
      }\r
    }\r
\r
    if (Xhc->UsbDevContext[SlotId].XhciDevAddr == 0) {\r
      goto ON_EXIT;\r
    }\r
    //\r
    // The actual device address has been assigned by XHCI during initializing the device slot.\r
    // So we just need establish the mapping relationship between the device address requested from UsbBus\r
    // and the actual device address assigned by XHCI. The following invocations through EFI_USB2_HC_PROTOCOL interface\r
    // can find out the actual device address by it.\r
    //\r
    Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8) Request->Value;\r
    Status = EFI_SUCCESS;\r
    goto ON_EXIT;\r
  }\r
\r
  //\r
  // Create a new URB, insert it into the asynchronous\r
  // schedule list, then poll the execution status.\r
  // Note that we encode the direction in address although default control\r
  // endpoint is bidirectional. XhcPeiCreateUrb expects this\r
  // combination of Ep addr and its direction.\r
  //\r
  Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));\r
  Urb = XhcPeiCreateUrb (\r
          Xhc,\r
          DeviceAddress,\r
          Endpoint,\r
          DeviceSpeed,\r
          MaximumPacketLength,\r
          XHC_CTRL_TRANSFER,\r
          Request,\r
          Data,\r
          *DataLength,\r
          NULL,\r
          NULL\r
          );\r
\r
  if (Urb == NULL) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: failed to create URB"));\r
    Status = EFI_OUT_OF_RESOURCES;\r
    goto ON_EXIT;\r
  }\r
\r
  Status = XhcPeiExecTransfer (Xhc, FALSE, Urb, TimeOut);\r
\r
  //\r
  // Get the status from URB. The result is updated in XhcPeiCheckUrbResult\r
  // which is called by XhcPeiExecTransfer\r
  //\r
  *TransferResult = Urb->Result;\r
  *DataLength     = Urb->Completed;\r
\r
  if (Status == EFI_TIMEOUT) {\r
    //\r
    // The transfer timed out. Abort the transfer by dequeueing of the TD.\r
    //\r
    RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);\r
    if (EFI_ERROR(RecoveryStatus)) {\r
      DEBUG((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));\r
    }\r
    goto FREE_URB;\r
  } else {\r
    if (*TransferResult == EFI_USB_NOERROR) {\r
      Status = EFI_SUCCESS;\r
    } else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {\r
      RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);\r
      if (EFI_ERROR (RecoveryStatus)) {\r
        DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));\r
      }\r
      Status = EFI_DEVICE_ERROR;\r
      goto FREE_URB;\r
    } else {\r
      goto FREE_URB;\r
    }\r
  }\r
\r
  //\r
  // Hook Get_Descriptor request from UsbBus as we need evaluate context and configure endpoint.\r
  // Hook Get_Status request form UsbBus as we need trace device attach/detach event happened at hub.\r
  // Hook Set_Config request from UsbBus as we need configure device endpoint.\r
  //\r
  if ((Request->Request     == USB_REQ_GET_DESCRIPTOR) &&\r
      ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||\r
      ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {\r
    DescriptorType = (UINT8) (Request->Value >> 8);\r
    if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {\r
      ASSERT (Data != NULL);\r
      //\r
      // Store a copy of device scriptor as hub device need this info to configure endpoint.\r
      //\r
      CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);\r
      if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {\r
        //\r
        // If it's a usb3.0 device, then its max packet size is a 2^n.\r
        //\r
        MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r
      } else {\r
        MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r
      }\r
      Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));\r
      if (Xhc->UsbDevContext[SlotId].ConfDesc == NULL) {\r
        Status = EFI_OUT_OF_RESOURCES;\r
        goto FREE_URB;\r
      }\r
      if (Xhc->HcCParams.Data.Csz == 0) {\r
        Status = XhcPeiEvaluateContext (Xhc, SlotId, MaxPacket0);\r
      } else {\r
        Status = XhcPeiEvaluateContext64 (Xhc, SlotId, MaxPacket0);\r
      }\r
    } else if (DescriptorType == USB_DESC_TYPE_CONFIG) {\r
      ASSERT (Data != NULL);\r
      if (*DataLength == ((UINT16 *) Data)[1]) {\r
        //\r
        // Get configuration value from request, store the configuration descriptor for Configure_Endpoint cmd.\r
        //\r
        Index = (UINT8) Request->Value;\r
        ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);\r
        Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);\r
        if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] == NULL) {\r
          Status = EFI_OUT_OF_RESOURCES;\r
          goto FREE_URB;\r
        }\r
        CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);\r
      }\r
    } else if (((DescriptorType == USB_DESC_TYPE_HUB) ||\r
               (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {\r
      ASSERT (Data != NULL);\r
      HubDesc = (EFI_USB_HUB_DESCRIPTOR *) Data;\r
      ASSERT (HubDesc->NumPorts <= 15);\r
      //\r
      // The bit 5,6 of HubCharacter field of Hub Descriptor is TTT.\r
      //\r
      TTT = (UINT8) ((HubDesc->HubCharacter & (BIT5 | BIT6)) >> 5);\r
      if (Xhc->UsbDevContext[SlotId].DevDesc.DeviceProtocol == 2) {\r
        //\r
        // Don't support multi-TT feature for super speed hub now.\r
        //\r
        MTT = 0;\r
        DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));\r
      } else {\r
        MTT = 0;\r
      }\r
\r
      if (Xhc->HcCParams.Data.Csz == 0) {\r
        Status = XhcPeiConfigHubContext (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);\r
      } else {\r
        Status = XhcPeiConfigHubContext64 (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);\r
      }\r
    }\r
  } else if ((Request->Request     == USB_REQ_SET_CONFIG) &&\r
             (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {\r
    //\r
    // Hook Set_Config request from UsbBus as we need configure device endpoint.\r
    //\r
    for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r
      if (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->ConfigurationValue == (UINT8)Request->Value) {\r
        if (Xhc->HcCParams.Data.Csz == 0) {\r
          Status = XhcPeiSetConfigCmd (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r
        } else {\r
          Status = XhcPeiSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r
        }\r
        break;\r
      }\r
    }\r
  } else if ((Request->Request     == USB_REQ_GET_STATUS) &&\r
             (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {\r
    ASSERT (Data != NULL);\r
    //\r
    // Hook Get_Status request from UsbBus to keep track of the port status change.\r
    //\r
    State                       = *(UINT32 *) Data;\r
    PortStatus.PortStatus       = 0;\r
    PortStatus.PortChangeStatus = 0;\r
\r
    if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
      //\r
      // For super speed hub, its bit10~12 presents the attached device speed.\r
      //\r
      if ((State & XHC_PORTSC_PS) >> 10 == 0) {\r
        PortStatus.PortStatus |= USB_PORT_STAT_SUPER_SPEED;\r
      }\r
    } else {\r
      //\r
      // For high or full/low speed hub, its bit9~10 presents the attached device speed.\r
      //\r
      if (XHC_BIT_IS_SET (State, BIT9)) {\r
        PortStatus.PortStatus |= USB_PORT_STAT_LOW_SPEED;\r
      } else if (XHC_BIT_IS_SET (State, BIT10)) {\r
        PortStatus.PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r
      }\r
    }\r
\r
    //\r
    // Convert the XHCI port/port change state to UEFI status\r
    //\r
    MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);\r
    for (Index = 0; Index < MapSize; Index++) {\r
      if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {\r
        PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);\r
      }\r
    }\r
\r
    MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);\r
    for (Index = 0; Index < MapSize; Index++) {\r
      if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {\r
        PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);\r
      }\r
    }\r
\r
    MapSize = sizeof (mUsbHubClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);\r
\r
    for (Index = 0; Index < MapSize; Index++) {\r
      if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {\r
        ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));\r
        ClearPortRequest.RequestType  = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);\r
        ClearPortRequest.Request      = (UINT8) USB_REQ_CLEAR_FEATURE;\r
        ClearPortRequest.Value        = mUsbHubClearPortChangeMap[Index].Selector;\r
        ClearPortRequest.Index        = Request->Index;\r
        ClearPortRequest.Length       = 0;\r
\r
        XhcPeiControlTransfer (\r
          PeiServices,\r
          This,\r
          DeviceAddress,\r
          DeviceSpeed,\r
          MaximumPacketLength,\r
          &ClearPortRequest,\r
          EfiUsbNoData,\r
          NULL,\r
          &Len,\r
          TimeOut,\r
          Translator,\r
          TransferResult\r
          );\r
      }\r
    }\r
\r
    XhcPeiPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);\r
\r
    *(UINT32 *) Data = *(UINT32 *) &PortStatus;\r
  }\r
\r
FREE_URB:\r
  XhcPeiFreeUrb (Xhc, Urb);\r
\r
ON_EXIT:\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Submits bulk transfer to a bulk endpoint of a USB device.\r
\r
  @param  PeiServices           The pointer of EFI_PEI_SERVICES.\r
  @param  This                  The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r
  @param  DeviceAddress         Target device address.\r
  @param  EndPointAddress       Endpoint number and its direction in bit 7.\r
  @param  DeviceSpeed           Device speed, Low speed device doesn't support\r
                                bulk transfer.\r
  @param  MaximumPacketLength   Maximum packet size the endpoint is capable of\r
                                sending or receiving.\r
  @param  Data                  Array of pointers to the buffers of data to transmit\r
                                from or receive into.\r
  @param  DataLength            The lenght of the data buffer.\r
  @param  DataToggle            On input, the initial data toggle for the transfer;\r
                                On output, it is updated to to next data toggle to use of\r
                                the subsequent bulk transfer.\r
  @param  TimeOut               Indicates the maximum time, in millisecond, which the\r
                                transfer is allowed to complete.\r
                                If Timeout is 0, then the caller must wait for the function\r
                                to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.\r
  @param  Translator            A pointr to the transaction translator data.\r
  @param  TransferResult        A pointer to the detailed result information of the\r
                                bulk transfer.\r
\r
  @retval EFI_SUCCESS           The transfer was completed successfully.\r
  @retval EFI_OUT_OF_RESOURCES  The transfer failed due to lack of resource.\r
  @retval EFI_INVALID_PARAMETER Parameters are invalid.\r
  @retval EFI_TIMEOUT           The transfer failed due to timeout.\r
  @retval EFI_DEVICE_ERROR      The transfer failed due to host controller error.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiBulkTransfer (\r
  IN EFI_PEI_SERVICES                       **PeiServices,\r
  IN PEI_USB2_HOST_CONTROLLER_PPI           *This,\r
  IN UINT8                                  DeviceAddress,\r
  IN UINT8                                  EndPointAddress,\r
  IN UINT8                                  DeviceSpeed,\r
  IN UINTN                                  MaximumPacketLength,\r
  IN OUT VOID                               *Data[EFI_USB_MAX_BULK_BUFFER_NUM],\r
  IN OUT UINTN                              *DataLength,\r
  IN OUT UINT8                              *DataToggle,\r
  IN UINTN                                  TimeOut,\r
  IN EFI_USB2_HC_TRANSACTION_TRANSLATOR     *Translator,\r
  OUT UINT32                                *TransferResult\r
  )\r
{\r
  PEI_XHC_DEV                   *Xhc;\r
  URB                           *Urb;\r
  UINT8                         SlotId;\r
  EFI_STATUS                    Status;\r
  EFI_STATUS                    RecoveryStatus;\r
\r
  //\r
  // Validate the parameters\r
  //\r
  if ((DataLength == NULL) || (*DataLength == 0) ||\r
      (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((*DataToggle != 0) && (*DataToggle != 1)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||\r
      ((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r
      ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 512)) ||\r
      ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength > 1024))) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Xhc             = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r
\r
  *TransferResult = EFI_USB_ERR_SYSTEM;\r
  Status          = EFI_DEVICE_ERROR;\r
\r
  if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: HC is halted or has system error\n"));\r
    goto ON_EXIT;\r
  }\r
\r
  //\r
  // Check if the device is still enabled before every transaction.\r
  //\r
  SlotId = XhcPeiBusDevAddrToSlotId (Xhc, DeviceAddress);\r
  if (SlotId == 0) {\r
    goto ON_EXIT;\r
  }\r
\r
  //\r
  // Create a new URB, insert it into the asynchronous\r
  // schedule list, then poll the execution status.\r
  //\r
  Urb = XhcPeiCreateUrb (\r
          Xhc,\r
          DeviceAddress,\r
          EndPointAddress,\r
          DeviceSpeed,\r
          MaximumPacketLength,\r
          XHC_BULK_TRANSFER,\r
          NULL,\r
          Data[0],\r
          *DataLength,\r
          NULL,\r
          NULL\r
          );\r
\r
  if (Urb == NULL) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: failed to create URB\n"));\r
    Status = EFI_OUT_OF_RESOURCES;\r
    goto ON_EXIT;\r
  }\r
\r
  Status = XhcPeiExecTransfer (Xhc, FALSE, Urb, TimeOut);\r
\r
  *TransferResult = Urb->Result;\r
  *DataLength     = Urb->Completed;\r
\r
  if (Status == EFI_TIMEOUT) {\r
    //\r
    // The transfer timed out. Abort the transfer by dequeueing of the TD.\r
    //\r
    RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);\r
    if (EFI_ERROR(RecoveryStatus)) {\r
      DEBUG((EFI_D_ERROR, "XhcPeiBulkTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));\r
    }\r
  } else {\r
    if (*TransferResult == EFI_USB_NOERROR) {\r
      Status = EFI_SUCCESS;\r
    } else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {\r
      RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);\r
      if (EFI_ERROR (RecoveryStatus)) {\r
        DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));\r
      }\r
      Status = EFI_DEVICE_ERROR;\r
    }\r
  }\r
\r
  XhcPeiFreeUrb (Xhc, Urb);\r
\r
ON_EXIT:\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Retrieves the number of root hub ports.\r
\r
  @param[in]  PeiServices           The pointer to the PEI Services Table.\r
  @param[in]  This                  The pointer to this instance of the\r
                                    PEI_USB2_HOST_CONTROLLER_PPI.\r
  @param[out] PortNumber            The pointer to the number of the root hub ports.\r
\r
  @retval EFI_SUCCESS               The port number was retrieved successfully.\r
  @retval EFI_INVALID_PARAMETER     PortNumber is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiGetRootHubPortNumber (\r
  IN EFI_PEI_SERVICES               **PeiServices,\r
  IN PEI_USB2_HOST_CONTROLLER_PPI   *This,\r
  OUT UINT8                         *PortNumber\r
  )\r
{\r
  PEI_XHC_DEV           *XhcDev;\r
  XhcDev = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r
\r
  if (PortNumber == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  *PortNumber = XhcDev->HcSParams1.Data.MaxPorts;\r
  DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortNumber: PortNumber = %x\n", *PortNumber));\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Clears a feature for the specified root hub port.\r
\r
  @param  PeiServices               The pointer of EFI_PEI_SERVICES.\r
  @param  This                      The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r
  @param  PortNumber                Specifies the root hub port whose feature\r
                                    is requested to be cleared.\r
  @param  PortFeature               Indicates the feature selector associated with the\r
                                    feature clear request.\r
\r
  @retval EFI_SUCCESS               The feature specified by PortFeature was cleared\r
                                    for the USB root hub port specified by PortNumber.\r
  @retval EFI_INVALID_PARAMETER     PortNumber is invalid or PortFeature is invalid.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiClearRootHubPortFeature (\r
  IN EFI_PEI_SERVICES               **PeiServices,\r
  IN PEI_USB2_HOST_CONTROLLER_PPI   *This,\r
  IN UINT8                          PortNumber,\r
  IN EFI_USB_PORT_FEATURE           PortFeature\r
  )\r
{\r
  PEI_XHC_DEV           *Xhc;\r
  UINT32                Offset;\r
  UINT32                State;\r
  EFI_STATUS            Status;\r
\r
  Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r
  Status = EFI_SUCCESS;\r
\r
  if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {\r
    Status = EFI_INVALID_PARAMETER;\r
    goto ON_EXIT;\r
  }\r
\r
  Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r
  State = XhcPeiReadOpReg (Xhc, Offset);\r
  DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));\r
\r
  //\r
  // Mask off the port status change bits, these bits are\r
  // write clean bits\r
  //\r
  State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r
\r
  switch (PortFeature) {\r
    case EfiUsbPortEnable:\r
      //\r
      // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r
      // A port may be disabled by software writing a '1' to this flag.\r
      //\r
      State |= XHC_PORTSC_PED;\r
      State &= ~XHC_PORTSC_RESET;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      break;\r
\r
    case EfiUsbPortSuspend:\r
      State |= XHC_PORTSC_LWS;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      State &= ~XHC_PORTSC_PLS;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      break;\r
\r
    case EfiUsbPortReset:\r
      //\r
      // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:\r
      // Register bits indicate status when read, a clear bit may be set by\r
      // writing a '1'. Writing a '0' to RW1S bits has no effect.\r
      //\r
      break;\r
\r
    case EfiUsbPortPower:\r
      if (Xhc->HcCParams.Data.Ppc) {\r
        //\r
        // Port Power Control supported\r
        //\r
        State &= ~XHC_PORTSC_PP;\r
        XhcPeiWriteOpReg (Xhc, Offset, State);\r
      }\r
      break;\r
\r
    case EfiUsbPortOwner:\r
      //\r
      // XHCI root hub port don't has the owner bit, ignore the operation\r
      //\r
      break;\r
\r
    case EfiUsbPortConnectChange:\r
      //\r
      // Clear connect status change\r
      //\r
      State |= XHC_PORTSC_CSC;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      break;\r
\r
    case EfiUsbPortEnableChange:\r
      //\r
      // Clear enable status change\r
      //\r
      State |= XHC_PORTSC_PEC;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      break;\r
\r
    case EfiUsbPortOverCurrentChange:\r
      //\r
      // Clear PortOverCurrent change\r
      //\r
      State |= XHC_PORTSC_OCC;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      break;\r
\r
    case EfiUsbPortResetChange:\r
      //\r
      // Clear Port Reset change\r
      //\r
      State |= XHC_PORTSC_PRC;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      break;\r
\r
    case EfiUsbPortSuspendChange:\r
      //\r
      // Not supported or not related operation\r
      //\r
      break;\r
\r
    default:\r
      Status = EFI_INVALID_PARAMETER;\r
      break;\r
  }\r
\r
ON_EXIT:\r
  DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));\r
  return Status;\r
}\r
\r
/**\r
  Sets a feature for the specified root hub port.\r
\r
  @param  PeiServices               The pointer of EFI_PEI_SERVICES\r
  @param  This                      The pointer of PEI_USB2_HOST_CONTROLLER_PPI\r
  @param  PortNumber                Root hub port to set.\r
  @param  PortFeature               Feature to set.\r
\r
  @retval EFI_SUCCESS               The feature specified by PortFeature was set.\r
  @retval EFI_INVALID_PARAMETER     PortNumber is invalid or PortFeature is invalid.\r
  @retval EFI_TIMEOUT               The time out occurred.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiSetRootHubPortFeature (\r
  IN EFI_PEI_SERVICES               **PeiServices,\r
  IN PEI_USB2_HOST_CONTROLLER_PPI   *This,\r
  IN UINT8                          PortNumber,\r
  IN EFI_USB_PORT_FEATURE           PortFeature\r
  )\r
{\r
  PEI_XHC_DEV           *Xhc;\r
  UINT32                Offset;\r
  UINT32                State;\r
  EFI_STATUS            Status;\r
\r
  Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r
  Status = EFI_SUCCESS;\r
\r
  if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {\r
    Status = EFI_INVALID_PARAMETER;\r
    goto ON_EXIT;\r
  }\r
\r
  Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r
  State = XhcPeiReadOpReg (Xhc, Offset);\r
  DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));\r
\r
  //\r
  // Mask off the port status change bits, these bits are\r
  // write clean bits\r
  //\r
  State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r
\r
  switch (PortFeature) {\r
    case EfiUsbPortEnable:\r
      //\r
      // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r
      // A port may be disabled by software writing a '1' to this flag.\r
      //\r
      break;\r
\r
    case EfiUsbPortSuspend:\r
      State |= XHC_PORTSC_LWS;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      State &= ~XHC_PORTSC_PLS;\r
      State |= (3 << 5) ;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      break;\r
\r
    case EfiUsbPortReset:\r
      //\r
      // Make sure Host Controller not halt before reset it\r
      //\r
      if (XhcPeiIsHalt (Xhc)) {\r
        Status = XhcPeiRunHC (Xhc, XHC_GENERIC_TIMEOUT);\r
        if (EFI_ERROR (Status)) {\r
          break;\r
        }\r
      }\r
\r
      //\r
      // 4.3.1 Resetting a Root Hub Port\r
      // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.\r
      // 2) Wait for a successful Port Status Change Event for the port, where the Port Reset Change (PRC)\r
      //    bit in the PORTSC field is set to '1'.\r
      //\r
      State |= XHC_PORTSC_RESET;\r
      XhcPeiWriteOpReg (Xhc, Offset, State);\r
      XhcPeiWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);\r
      break;\r
\r
    case EfiUsbPortPower:\r
      if (Xhc->HcCParams.Data.Ppc) {\r
        //\r
        // Port Power Control supported\r
        //\r
        State |= XHC_PORTSC_PP;\r
        XhcPeiWriteOpReg (Xhc, Offset, State);\r
      }\r
      break;\r
\r
    case EfiUsbPortOwner:\r
      //\r
      // XHCI root hub port don't has the owner bit, ignore the operation\r
      //\r
      break;\r
\r
    default:\r
      Status = EFI_INVALID_PARAMETER;\r
  }\r
\r
ON_EXIT:\r
  DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));\r
  return Status;\r
}\r
\r
/**\r
  Retrieves the current status of a USB root hub port.\r
\r
  @param  PeiServices               The pointer of EFI_PEI_SERVICES.\r
  @param  This                      The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r
  @param  PortNumber                The root hub port to retrieve the state from.\r
  @param  PortStatus                Variable to receive the port state.\r
\r
  @retval EFI_SUCCESS               The status of the USB root hub port specified.\r
                                    by PortNumber was returned in PortStatus.\r
  @retval EFI_INVALID_PARAMETER     PortNumber is invalid.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiGetRootHubPortStatus (\r
  IN EFI_PEI_SERVICES               **PeiServices,\r
  IN PEI_USB2_HOST_CONTROLLER_PPI   *This,\r
  IN UINT8                          PortNumber,\r
  OUT EFI_USB_PORT_STATUS           *PortStatus\r
  )\r
{\r
  PEI_XHC_DEV               *Xhc;\r
  UINT32                    Offset;\r
  UINT32                    State;\r
  UINTN                     Index;\r
  UINTN                     MapSize;\r
  USB_DEV_ROUTE             ParentRouteChart;\r
\r
  if (PortStatus == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r
\r
  if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Clear port status.\r
  //\r
  PortStatus->PortStatus        = 0;\r
  PortStatus->PortChangeStatus  = 0;\r
\r
  Offset                        = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r
  State                         = XhcPeiReadOpReg (Xhc, Offset);\r
  DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x State: %x\n", PortNumber, State));\r
\r
  //\r
  // According to XHCI 1.0 spec, bit 10~13 of the root port status register identifies the speed of the attached device.\r
  //\r
  switch ((State & XHC_PORTSC_PS) >> 10) {\r
    case 2:\r
      PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r
      break;\r
\r
    case 3:\r
      PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r
      break;\r
\r
    case 4:\r
      PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;\r
      break;\r
\r
    default:\r
      break;\r
  }\r
\r
  //\r
  // Convert the XHCI port/port change state to UEFI status\r
  //\r
  MapSize = sizeof (mUsbPortStateMap) / sizeof (USB_PORT_STATE_MAP);\r
\r
  for (Index = 0; Index < MapSize; Index++) {\r
    if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {\r
      PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);\r
    }\r
  }\r
  //\r
  // Bit5~8 reflects its current link state.\r
  //\r
  if ((State & XHC_PORTSC_PLS) >> 5 == 3) {\r
    PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;\r
  }\r
\r
  MapSize = sizeof (mUsbPortChangeMap) / sizeof (USB_PORT_STATE_MAP);\r
\r
  for (Index = 0; Index < MapSize; Index++) {\r
    if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {\r
      PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);\r
    }\r
  }\r
\r
  MapSize = sizeof (mUsbClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);\r
\r
  for (Index = 0; Index < MapSize; Index++) {\r
    if (XHC_BIT_IS_SET (State, mUsbClearPortChangeMap[Index].HwState)) {\r
      XhcPeiClearRootHubPortFeature (PeiServices, This, PortNumber, (EFI_USB_PORT_FEATURE)mUsbClearPortChangeMap[Index].Selector);\r
    }\r
  }\r
\r
  //\r
  // Poll the root port status register to enable/disable corresponding device slot if there is a device attached/detached.\r
  // For those devices behind hub, we get its attach/detach event by hooking Get_Port_Status request at control transfer for those hub.\r
  //\r
  ParentRouteChart.Dword = 0;\r
  XhcPeiPollPortStatusChange (Xhc, ParentRouteChart, PortNumber, PortStatus);\r
\r
  DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: PortChangeStatus: %x PortStatus: %x\n", PortStatus->PortChangeStatus, PortStatus->PortStatus));\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  @param FileHandle     Handle of the file being invoked.\r
  @param PeiServices    Describes the list of possible PEI Services.\r
\r
  @retval EFI_SUCCESS   PPI successfully installed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeimEntry (\r
  IN EFI_PEI_FILE_HANDLE    FileHandle,\r
  IN CONST EFI_PEI_SERVICES **PeiServices\r
  )\r
{\r
  PEI_USB_CONTROLLER_PPI      *UsbControllerPpi;\r
  EFI_STATUS                  Status;\r
  UINT8                       Index;\r
  UINTN                       ControllerType;\r
  UINTN                       BaseAddress;\r
  UINTN                       MemPages;\r
  PEI_XHC_DEV                 *XhcDev;\r
  EFI_PHYSICAL_ADDRESS        TempPtr;\r
  UINT32                      PageSize;\r
\r
  //\r
  // Shadow this PEIM to run from memory.\r
  //\r
  if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  Status = PeiServicesLocatePpi (\r
             &gPeiUsbControllerPpiGuid,\r
             0,\r
             NULL,\r
             (VOID **) &UsbControllerPpi\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  Index = 0;\r
  while (TRUE) {\r
    Status = UsbControllerPpi->GetUsbController (\r
                                 (EFI_PEI_SERVICES **) PeiServices,\r
                                 UsbControllerPpi,\r
                                 Index,\r
                                 &ControllerType,\r
                                 &BaseAddress\r
                                 );\r
    //\r
    // When status is error, it means no controller is found.\r
    //\r
    if (EFI_ERROR (Status)) {\r
      break;\r
    }\r
\r
    //\r
    // This PEIM is for XHC type controller.\r
    //\r
    if (ControllerType != PEI_XHCI_CONTROLLER) {\r
      Index++;\r
      continue;\r
    }\r
\r
    MemPages = EFI_SIZE_TO_PAGES (sizeof (PEI_XHC_DEV));\r
    Status = PeiServicesAllocatePages (\r
               EfiBootServicesData,\r
               MemPages,\r
               &TempPtr\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
    ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (MemPages));\r
    XhcDev = (PEI_XHC_DEV *) ((UINTN) TempPtr);\r
\r
    XhcDev->Signature = USB_XHC_DEV_SIGNATURE;\r
    XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;\r
    XhcDev->CapLength           = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0FF);\r
    XhcDev->HcSParams1.Dword    = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS1_OFFSET);\r
    XhcDev->HcSParams2.Dword    = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS2_OFFSET);\r
    XhcDev->HcCParams.Dword     = XhcPeiReadCapRegister (XhcDev, XHC_HCCPARAMS_OFFSET);\r
    XhcDev->DBOff               = XhcPeiReadCapRegister (XhcDev, XHC_DBOFF_OFFSET);\r
    XhcDev->RTSOff              = XhcPeiReadCapRegister (XhcDev, XHC_RTSOFF_OFFSET);\r
\r
    //\r
    // This PageSize field defines the page size supported by the xHC implementation.\r
    // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,\r
    // if bit 0 is Set, the xHC supports 4k byte page sizes.\r
    //\r
    PageSize         = XhcPeiReadOpReg (XhcDev, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;\r
    XhcDev->PageSize = 1 << (HighBitSet32 (PageSize) + 12);\r
\r
    DEBUG ((EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress));\r
    DEBUG ((EFI_D_INFO, "XhciPei: CapLength:                    %x\n", XhcDev->CapLength));\r
    DEBUG ((EFI_D_INFO, "XhciPei: HcSParams1:                   %x\n", XhcDev->HcSParams1.Dword));\r
    DEBUG ((EFI_D_INFO, "XhciPei: HcSParams2:                   %x\n", XhcDev->HcSParams2.Dword));\r
    DEBUG ((EFI_D_INFO, "XhciPei: HcCParams:                    %x\n", XhcDev->HcCParams.Dword));\r
    DEBUG ((EFI_D_INFO, "XhciPei: DBOff:                        %x\n", XhcDev->DBOff));\r
    DEBUG ((EFI_D_INFO, "XhciPei: RTSOff:                       %x\n", XhcDev->RTSOff));\r
    DEBUG ((EFI_D_INFO, "XhciPei: PageSize:                     %x\n", XhcDev->PageSize));\r
\r
    XhcPeiResetHC (XhcDev, XHC_RESET_TIMEOUT);\r
    ASSERT (XhcPeiIsHalt (XhcDev));\r
\r
    //\r
    // Initialize the schedule\r
    //\r
    XhcPeiInitSched (XhcDev);\r
\r
    //\r
    // Start the Host Controller\r
    //\r
    XhcPeiRunHC (XhcDev, XHC_GENERIC_TIMEOUT);\r
\r
    //\r
    // Wait for root port state stable\r
    //\r
    MicroSecondDelay (XHC_ROOT_PORT_STATE_STABLE);\r
\r
    XhcDev->Usb2HostControllerPpi.ControlTransfer           = XhcPeiControlTransfer;\r
    XhcDev->Usb2HostControllerPpi.BulkTransfer              = XhcPeiBulkTransfer;\r
    XhcDev->Usb2HostControllerPpi.GetRootHubPortNumber      = XhcPeiGetRootHubPortNumber;\r
    XhcDev->Usb2HostControllerPpi.GetRootHubPortStatus      = XhcPeiGetRootHubPortStatus;\r
    XhcDev->Usb2HostControllerPpi.SetRootHubPortFeature     = XhcPeiSetRootHubPortFeature;\r
    XhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature   = XhcPeiClearRootHubPortFeature;\r
\r
    XhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
    XhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;\r
    XhcDev->PpiDescriptor.Ppi = &XhcDev->Usb2HostControllerPpi;\r
\r
    PeiServicesInstallPpi (&XhcDev->PpiDescriptor);\r
\r
    Index++;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r