[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciReg.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_PEI_XHCI_REG_H_\r
#define _EFI_PEI_XHCI_REG_H_\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET            0x00    // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET           0x02    // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET           0x04    // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET           0x08    // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET           0x0c    // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET            0x10    // Capability Parameters\r
#define XHC_DBOFF_OFFSET                0x14    // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET               0x18    // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET               0x0000  // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET               0x0004  // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET             0x0008  // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET               0x0014  // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET                 0x0018  // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET               0x0030  // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET               0x0038  // Configure Register Offset\r
#define XHC_PORTSC_OFFSET               0x0400  // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET              0x00    // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET                 0x20    // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET                 0x24    // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET               0x28    // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET               0x30    // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET                 0x38    // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN                  BIT0    // Run/Stop\r
#define XHC_USBCMD_RESET                BIT1    // Host Controller Reset\r
#define XHC_USBCMD_INTE                 BIT2    // Interrupter Enable\r
#define XHC_USBCMD_HSEE                 BIT3    // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT                 BIT0    // Host Controller Halted\r
#define XHC_USBSTS_HSE                  BIT2    // Host System Error\r
#define XHC_USBSTS_EINT                 BIT3    // Event Interrupt\r
#define XHC_USBSTS_PCD                  BIT4    // Port Change Detect\r
#define XHC_USBSTS_SSS                  BIT8    // Save State Status\r
#define XHC_USBSTS_RSS                  BIT9    // Restore State Status\r
#define XHC_USBSTS_SRE                  BIT10   // Save/Restore Error\r
#define XHC_USBSTS_CNR                  BIT11   // Host Controller Not Ready\r
#define XHC_USBSTS_HCE                  BIT12   // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK               0xFFFF  // Page Size\r
\r
#define XHC_CRCR_RCS                    BIT0    // Ring Cycle State\r
#define XHC_CRCR_CS                     BIT1    // Command Stop\r
#define XHC_CRCR_CA                     BIT2    // Command Abort\r
#define XHC_CRCR_CRR                    BIT3    // Command Ring Running\r
\r
#define XHC_CONFIG_MASK                 0xFF    // Max Device Slots Enabled\r
\r
#define XHC_PORTSC_CCS                  BIT0    // Current Connect Status\r
#define XHC_PORTSC_PED                  BIT1    // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA                  BIT3    // Over-current Active\r
#define XHC_PORTSC_RESET                BIT4    // Port Reset\r
#define XHC_PORTSC_PLS                  (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
#define XHC_PORTSC_PP                   BIT9    // Port Power\r
#define XHC_PORTSC_PS                   (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
#define XHC_PORTSC_LWS                  BIT16   // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC                  BIT17   // Connect Status Change\r
#define XHC_PORTSC_PEC                  BIT18   // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC                  BIT19   // Warm Port Reset Change\r
#define XHC_PORTSC_OCC                  BIT20   // Over-Current Change\r
#define XHC_PORTSC_PRC                  BIT21   // Port Reset Change\r
#define XHC_PORTSC_PLC                  BIT22   // Port Link State Change\r
#define XHC_PORTSC_CEC                  BIT23   // Port Config Error Change\r
#define XHC_PORTSC_CAS                  BIT24   // Cold Attach Status\r
\r
#define XHC_HUB_PORTSC_CCS              BIT0    // Hub's Current Connect Status\r
#define XHC_HUB_PORTSC_PED              BIT1    // Hub's Port Enabled/Disabled\r
#define XHC_HUB_PORTSC_OCA              BIT3    // Hub's Over-current Active\r
#define XHC_HUB_PORTSC_RESET            BIT4    // Hub's Port Reset\r
#define XHC_HUB_PORTSC_PP               BIT9    // Hub's Port Power\r
#define XHC_HUB_PORTSC_CSC              BIT16   // Hub's Connect Status Change\r
#define XHC_HUB_PORTSC_PEC              BIT17   // Hub's Port Enabled/Disabled Change\r
#define XHC_HUB_PORTSC_OCC              BIT19   // Hub's Over-Current Change\r
#define XHC_HUB_PORTSC_PRC              BIT20   // Hub's Port Reset Change\r
#define XHC_HUB_PORTSC_BHRC             BIT21   // Hub's Port Warm Reset Change\r
\r
#define XHC_IMAN_IP                     BIT0    // Interrupt Pending\r
#define XHC_IMAN_IE                     BIT1    // Interrupt Enable\r
\r
#define XHC_IMODI_MASK                  0x0000FFFF  // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK                  0xFFFF0000  // Interrupt Moderation Counter\r
\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8                 MaxSlots;       // Number of Device Slots\r
  UINT16                MaxIntrs:11;    // Number of Interrupters\r
  UINT16                Rsvd:5;\r
  UINT8                 MaxPorts;       // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                Dword;\r
  HCSPARAMS1            Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32                Ist:4;          // Isochronous Scheduling Threshold\r
  UINT32                Erst:4;         // Event Ring Segment Table Max\r
  UINT32                Rsvd:13;\r
  UINT32                ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
  UINT32                Spr:1;          // Scratchpad Restore\r
  UINT32                ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                Dword;\r
  HCSPARAMS2            Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16                Ac64:1;        // 64-bit Addressing Capability\r
  UINT16                Bnc:1;         // BW Negotiation Capability\r
  UINT16                Csz:1;         // Context Size\r
  UINT16                Ppc:1;         // Port Power Control\r
  UINT16                Pind:1;        // Port Indicators\r
  UINT16                Lhrc:1;        // Light HC Reset Capability\r
  UINT16                Ltc:1;         // Latency Tolerance Messaging Capability\r
  UINT16                Nss:1;         // No Secondary SID Support\r
  UINT16                Pae:1;         // Parse All Event Data\r
  UINT16                Rsvd:3;\r
  UINT16                MaxPsaSize:4;  // Maximum Primary Stream Array Size\r
  UINT16                ExtCapReg;     // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                Dword;\r
  HCCPARAMS             Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// XHCi Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   Pi;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
\r
typedef struct {\r
  UINT8                     Length;\r
  UINT8                     DescType;\r
  UINT8                     NumPorts;\r
  UINT16                    HubCharacter;\r
  UINT8                     PwrOn2PwrGood;\r
  UINT8                     HubContrCurrent;\r
  UINT8                     Filler[16];\r
} EFI_USB_HUB_DESCRIPTOR;\r
#pragma pack()\r
\r
//\r
//  Hub Class Feature Selector for Clear Port Feature Request\r
//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
//\r
typedef enum {\r
  Usb3PortBHPortReset          = 28,\r
  Usb3PortBHPortResetChange    = 29\r
} XHC_PORT_FEATURE;\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Structure to map the hardware port states to feature selector for clear port feature request.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  Selector;\r
} USB_CLEAR_PORT_MAP;\r
\r
/**\r
  Read XHCI Operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
\r
  @retval the register content read.\r
\r
**/\r
UINT32\r
XhcPeiReadOpReg (\r
  IN  PEI_XHC_DEV       *Xhc,\r
  IN  UINT32            Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
  @param Data           The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteOpReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcPeiClearOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit of the register to wait for.\r
  @param  WaitToSet     Wait the bit to set or clear.\r
  @param  Timeout       The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS   The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT   The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcPeiWaitOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit,\r
  IN BOOLEAN            WaitToSet,\r
  IN UINT32             Timeout\r
  );\r
\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the door bell register.\r
  @param  Data          The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteDoorBellReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcPeiReadRuntimeReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN  UINT32            Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Data          The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteRuntimeReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetRuntimeRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiClearRuntimeRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Check whether Xhc is halted.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          The controller is halted.\r
  @retval FALSE         The controller isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsHalt (\r
  IN PEI_XHC_DEV        *Xhc\r
  );\r
\r
/**\r
  Check whether system error occurred.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          System error happened.\r
  @retval FALSE         No system error.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsSysError (\r
  IN PEI_XHC_DEV        *Xhc\r
  );\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_TIMEOUT   The transfer failed due to time out.\r
  @retval Others        Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
XhcPeiResetHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_TIMEOUT   Failed to halt the controller before Timeout.\r
  @retval EFI_SUCCESS   The XHCI is halt.\r
\r
**/\r
EFI_STATUS\r
XhcPeiHaltHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Set the XHCI to run.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_SUCCESS   The XHCI is running.\r
  @retval Others        Failed to set the XHCI to run.\r
\r
**/\r
EFI_STATUS\r
XhcPeiRunHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
#endif\r
Commit	Line	Data
d987459f SZ	1	/** @file\r
	2	Private Header file for Usb Host Controller PEIM\r
	3	\r
4a723d3d	4	Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
d987459f	5	\r
9d510e61	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
d987459f SZ	7	\r
	8	**/\r
	9	\r
	10	#ifndef _EFI_PEI_XHCI_REG_H_\r
	11	#define _EFI_PEI_XHCI_REG_H_\r
	12	\r
	13	//\r
	14	// Capability registers offset\r
	15	//\r
	16	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	17	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	18	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	19	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	20	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	21	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	22	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	23	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
	24	\r
	25	//\r
	26	// Operational registers offset\r
	27	//\r
	28	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	29	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	30	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	31	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	32	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	33	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	34	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	35	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
	36	\r
	37	//\r
	38	// Runtime registers offset\r
	39	//\r
	40	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	41	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
	42	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
	43	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
	44	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
	45	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
	46	\r
	47	//\r
	48	// Register Bit Definition\r
	49	//\r
	50	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	51	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	52	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	53	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	54	\r
	55	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	56	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	57	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
	58	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
	59	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
	60	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
	61	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
	62	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
	63	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
	64	\r
	65	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
	66	\r
	67	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
	68	#define XHC_CRCR_CS BIT1 // Command Stop\r
	69	#define XHC_CRCR_CA BIT2 // Command Abort\r
	70	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
71	\r
72	#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled\r
73	\r
74	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
75	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
76	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
77	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
4a723d3d	78	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
d987459f	79	#define XHC_PORTSC_PP BIT9 // Port Power\r
4a723d3d	80	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12\|BIT13) // Port Speed\r
d987459f SZ	81	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
	82	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
	83	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
	84	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
	85	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
	86	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
	87	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
	88	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
	89	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
	90	\r
	91	#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
	92	#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
	93	#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
	94	#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
	95	#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
	96	#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
	97	#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
	98	#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
	99	#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
	100	#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
	101	\r
	102	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
	103	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
	104	\r
	105	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
	106	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
	107	\r
	108	\r
	109	#pragma pack (1)\r
	110	typedef struct {\r
	111	UINT8 MaxSlots; // Number of Device Slots\r
	112	UINT16 MaxIntrs:11; // Number of Interrupters\r
	113	UINT16 Rsvd:5;\r
	114	UINT8 MaxPorts; // Number of Ports\r
	115	} HCSPARAMS1;\r
	116	\r
	117	//\r
	118	// Structural Parameters 1 Register Bitmap Definition\r
	119	//\r
	120	typedef union {\r
	121	UINT32 Dword;\r
	122	HCSPARAMS1 Data;\r
	123	} XHC_HCSPARAMS1;\r
	124	\r
	125	typedef struct {\r
	126	UINT32 Ist:4; // Isochronous Scheduling Threshold\r
	127	UINT32 Erst:4; // Event Ring Segment Table Max\r
	128	UINT32 Rsvd:13;\r
	129	UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
	130	UINT32 Spr:1; // Scratchpad Restore\r
	131	UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
	132	} HCSPARAMS2;\r
	133	\r
	134	//\r
	135	// Structural Parameters 2 Register Bitmap Definition\r
	136	//\r
	137	typedef union {\r
	138	UINT32 Dword;\r
	139	HCSPARAMS2 Data;\r
	140	} XHC_HCSPARAMS2;\r
	141	\r
	142	typedef struct {\r
	143	UINT16 Ac64:1; // 64-bit Addressing Capability\r
	144	UINT16 Bnc:1; // BW Negotiation Capability\r
145	UINT16 Csz:1; // Context Size\r
146	UINT16 Ppc:1; // Port Power Control\r
147	UINT16 Pind:1; // Port Indicators\r
148	UINT16 Lhrc:1; // Light HC Reset Capability\r
149	UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
150	UINT16 Nss:1; // No Secondary SID Support\r
151	UINT16 Pae:1; // Parse All Event Data\r
152	UINT16 Rsvd:3;\r
153	UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
154	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
155	} HCCPARAMS;\r
156	\r
157	//\r
158	// Capability Parameters Register Bitmap Definition\r
159	//\r
160	typedef union {\r
161	UINT32 Dword;\r
162	HCCPARAMS Data;\r
163	} XHC_HCCPARAMS;\r
164	\r
165	#pragma pack ()\r
166	\r
167	//\r
168	// XHCi Data and Ctrl Structures\r
169	//\r
170	#pragma pack(1)\r
171	typedef struct {\r
172	UINT8 Pi;\r
173	UINT8 SubClassCode;\r
174	UINT8 BaseCode;\r
175	} USB_CLASSC;\r
176	\r
177	typedef struct {\r
178	UINT8 Length;\r
179	UINT8 DescType;\r
180	UINT8 NumPorts;\r
181	UINT16 HubCharacter;\r
182	UINT8 PwrOn2PwrGood;\r
183	UINT8 HubContrCurrent;\r
184	UINT8 Filler[16];\r
185	} EFI_USB_HUB_DESCRIPTOR;\r
186	#pragma pack()\r
187	\r
188	//\r
189	// Hub Class Feature Selector for Clear Port Feature Request\r
190	// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
191	// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
192	//\r
193	typedef enum {\r
194	Usb3PortBHPortReset = 28,\r
195	Usb3PortBHPortResetChange = 29\r
196	} XHC_PORT_FEATURE;\r
197	\r
198	//\r
199	// Structure to map the hardware port states to the\r
200	// UEFI's port states.\r
201	//\r
202	typedef struct {\r
203	UINT32 HwState;\r
204	UINT16 UefiState;\r
205	} USB_PORT_STATE_MAP;\r
206	\r
207	//\r
208	// Structure to map the hardware port states to feature selector for clear port feature request.\r
209	//\r
210	typedef struct {\r
211	UINT32 HwState;\r
212	UINT16 Selector;\r
213	} USB_CLEAR_PORT_MAP;\r
214	\r
215	/**\r
216	Read XHCI Operation register.\r
217	\r
218	@param Xhc The XHCI device.\r
219	@param Offset The operation register offset.\r
220	\r
221	@retval the register content read.\r
222	\r
223	**/\r
224	UINT32\r
225	XhcPeiReadOpReg (\r
226	IN PEI_XHC_DEV *Xhc,\r
227	IN UINT32 Offset\r
228	);\r
229	\r
230	/**\r
231	Write the data to the XHCI operation register.\r
232	\r
233	@param Xhc The XHCI device.\r
234	@param Offset The operation register offset.\r
235	@param Data The data to write.\r
236	\r
237	**/\r
238	VOID\r
239	XhcPeiWriteOpReg (\r
240	IN PEI_XHC_DEV *Xhc,\r
241	IN UINT32 Offset,\r
242	IN UINT32 Data\r
243	);\r
244	\r
245	/**\r
246	Set one bit of the operational register while keeping other bits.\r
247	\r
248	@param Xhc The XHCI device.\r
249	@param Offset The offset of the operational register.\r
250	@param Bit The bit mask of the register to set.\r
251	\r
252	**/\r
253	VOID\r
254	XhcPeiSetOpRegBit (\r
255	IN PEI_XHC_DEV *Xhc,\r
256	IN UINT32 Offset,\r
257	IN UINT32 Bit\r
258	);\r
259	\r
260	/**\r
261	Clear one bit of the operational register while keeping other bits.\r
262	\r
263	@param Xhc The XHCI device.\r
264	@param Offset The offset of the operational register.\r
265	@param Bit The bit mask of the register to clear.\r
266	\r
267	**/\r
268	VOID\r
269	XhcPeiClearOpRegBit (\r
270	IN PEI_XHC_DEV *Xhc,\r
271	IN UINT32 Offset,\r
272	IN UINT32 Bit\r
273	);\r
274	\r
275	/**\r
276	Wait the operation register's bit as specified by Bit\r
277	to be set (or clear).\r
278	\r
279	@param Xhc The XHCI device.\r
280	@param Offset The offset of the operational register.\r
281	@param Bit The bit of the register to wait for.\r
282	@param WaitToSet Wait the bit to set or clear.\r
2f6ef874	283	@param Timeout The time to wait before abort (in millisecond, ms).\r
d987459f SZ	284	\r
	285	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
	286	@retval EFI_TIMEOUT The time out occurred.\r
	287	\r
	288	**/\r
	289	EFI_STATUS\r
	290	XhcPeiWaitOpRegBit (\r
	291	IN PEI_XHC_DEV *Xhc,\r
	292	IN UINT32 Offset,\r
	293	IN UINT32 Bit,\r
	294	IN BOOLEAN WaitToSet,\r
	295	IN UINT32 Timeout\r
	296	);\r
	297	\r
d987459f SZ	298	\r
	299	/**\r
	300	Write the data to the XHCI door bell register.\r
	301	\r
	302	@param Xhc The XHCI device.\r
	303	@param Offset The offset of the door bell register.\r
	304	@param Data The data to write.\r
	305	\r
	306	**/\r
	307	VOID\r
	308	XhcPeiWriteDoorBellReg (\r
	309	IN PEI_XHC_DEV *Xhc,\r
	310	IN UINT32 Offset,\r
	311	IN UINT32 Data\r
	312	);\r
	313	\r
	314	/**\r
	315	Read XHCI runtime register.\r
	316	\r
	317	@param Xhc The XHCI device.\r
	318	@param Offset The offset of the runtime register.\r
	319	\r
	320	@return The register content read\r
	321	\r
	322	**/\r
	323	UINT32\r
	324	XhcPeiReadRuntimeReg (\r
	325	IN PEI_XHC_DEV *Xhc,\r
	326	IN UINT32 Offset\r
	327	);\r
	328	\r
	329	/**\r
	330	Write the data to the XHCI runtime register.\r
	331	\r
	332	@param Xhc The XHCI device.\r
	333	@param Offset The offset of the runtime register.\r
	334	@param Data The data to write.\r
	335	\r
	336	**/\r
	337	VOID\r
	338	XhcPeiWriteRuntimeReg (\r
	339	IN PEI_XHC_DEV *Xhc,\r
	340	IN UINT32 Offset,\r
	341	IN UINT32 Data\r
	342	);\r
	343	\r
	344	/**\r
	345	Set one bit of the runtime register while keeping other bits.\r
	346	\r
	347	@param Xhc The XHCI device.\r
	348	@param Offset The offset of the runtime register.\r
	349	@param Bit The bit mask of the register to set.\r
	350	\r
	351	**/\r
	352	VOID\r
	353	XhcPeiSetRuntimeRegBit (\r
	354	IN PEI_XHC_DEV *Xhc,\r
	355	IN UINT32 Offset,\r
	356	IN UINT32 Bit\r
	357	);\r
	358	\r
	359	/**\r
	360	Clear one bit of the runtime register while keeping other bits.\r
	361	\r
362	@param Xhc The XHCI device.\r
363	@param Offset The offset of the runtime register.\r
364	@param Bit The bit mask of the register to set.\r
365	\r
366	**/\r
367	VOID\r
368	XhcPeiClearRuntimeRegBit (\r
369	IN PEI_XHC_DEV *Xhc,\r
370	IN UINT32 Offset,\r
371	IN UINT32 Bit\r
372	);\r
373	\r
374	/**\r
375	Check whether Xhc is halted.\r
376	\r
377	@param Xhc The XHCI device.\r
378	\r
379	@retval TRUE The controller is halted.\r
380	@retval FALSE The controller isn't halted.\r
381	\r
382	**/\r
383	BOOLEAN\r
384	XhcPeiIsHalt (\r
385	IN PEI_XHC_DEV *Xhc\r
386	);\r
387	\r
388	/**\r
389	Check whether system error occurred.\r
390	\r
391	@param Xhc The XHCI device.\r
392	\r
393	@retval TRUE System error happened.\r
394	@retval FALSE No system error.\r
395	\r
396	**/\r
397	BOOLEAN\r
398	XhcPeiIsSysError (\r
399	IN PEI_XHC_DEV *Xhc\r
400	);\r
401	\r
402	/**\r
403	Reset the host controller.\r
404	\r
405	@param Xhc The XHCI device.\r
406	@param Timeout Time to wait before abort (in millisecond, ms).\r
407	\r
408	@retval EFI_TIMEOUT The transfer failed due to time out.\r
409	@retval Others Failed to reset the host.\r
410	\r
411	**/\r
412	EFI_STATUS\r
413	XhcPeiResetHC (\r
414	IN PEI_XHC_DEV *Xhc,\r
415	IN UINT32 Timeout\r
416	);\r
417	\r
418	/**\r
419	Halt the host controller.\r
420	\r
421	@param Xhc The XHCI device.\r
422	@param Timeout Time to wait before abort.\r
423	\r
424	@retval EFI_TIMEOUT Failed to halt the controller before Timeout.\r
425	@retval EFI_SUCCESS The XHCI is halt.\r
426	\r
427	**/\r
428	EFI_STATUS\r
429	XhcPeiHaltHC (\r
430	IN PEI_XHC_DEV *Xhc,\r
431	IN UINT32 Timeout\r
432	);\r
433	\r
434	/**\r
435	Set the XHCI to run.\r
436	\r
437	@param Xhc The XHCI device.\r
438	@param Timeout Time to wait before abort.\r
439	\r
440	@retval EFI_SUCCESS The XHCI is running.\r
441	@retval Others Failed to set the XHCI to run.\r
442	\r
443	**/\r
444	EFI_STATUS\r
445	XhcPeiRunHC (\r
446	IN PEI_XHC_DEV *Xhc,\r
447	IN UINT32 Timeout\r
448	);\r
449	\r
450	#endif\r