[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciReg.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_PEI_XHCI_REG_H_\r
#define _EFI_PEI_XHCI_REG_H_\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET            0x00    // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET           0x02    // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET           0x04    // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET           0x08    // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET           0x0c    // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET            0x10    // Capability Parameters\r
#define XHC_DBOFF_OFFSET                0x14    // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET               0x18    // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET               0x0000  // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET               0x0004  // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET             0x0008  // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET               0x0014  // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET                 0x0018  // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET               0x0030  // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET               0x0038  // Configure Register Offset\r
#define XHC_PORTSC_OFFSET               0x0400  // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET              0x00    // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET                 0x20    // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET                 0x24    // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET               0x28    // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET               0x30    // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET                 0x38    // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN                  BIT0    // Run/Stop\r
#define XHC_USBCMD_RESET                BIT1    // Host Controller Reset\r
#define XHC_USBCMD_INTE                 BIT2    // Interrupter Enable\r
#define XHC_USBCMD_HSEE                 BIT3    // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT                 BIT0    // Host Controller Halted\r
#define XHC_USBSTS_HSE                  BIT2    // Host System Error\r
#define XHC_USBSTS_EINT                 BIT3    // Event Interrupt\r
#define XHC_USBSTS_PCD                  BIT4    // Port Change Detect\r
#define XHC_USBSTS_SSS                  BIT8    // Save State Status\r
#define XHC_USBSTS_RSS                  BIT9    // Restore State Status\r
#define XHC_USBSTS_SRE                  BIT10   // Save/Restore Error\r
#define XHC_USBSTS_CNR                  BIT11   // Host Controller Not Ready\r
#define XHC_USBSTS_HCE                  BIT12   // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK               0xFFFF  // Page Size\r
\r
#define XHC_CRCR_RCS                    BIT0    // Ring Cycle State\r
#define XHC_CRCR_CS                     BIT1    // Command Stop\r
#define XHC_CRCR_CA                     BIT2    // Command Abort\r
#define XHC_CRCR_CRR                    BIT3    // Command Ring Running\r
\r
#define XHC_CONFIG_MASK                 0xFF    // Max Device Slots Enabled\r
\r
#define XHC_PORTSC_CCS                  BIT0    // Current Connect Status\r
#define XHC_PORTSC_PED                  BIT1    // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA                  BIT3    // Over-current Active\r
#define XHC_PORTSC_RESET                BIT4    // Port Reset\r
#define XHC_PORTSC_PLS                  (BIT5|BIT6|BIT7|BIT8)   // Port Link State\r
#define XHC_PORTSC_PP                   BIT9    // Port Power\r
#define XHC_PORTSC_PS                   (BIT10|BIT11|BIT12)     // Port Speed\r
#define XHC_PORTSC_LWS                  BIT16   // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC                  BIT17   // Connect Status Change\r
#define XHC_PORTSC_PEC                  BIT18   // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC                  BIT19   // Warm Port Reset Change\r
#define XHC_PORTSC_OCC                  BIT20   // Over-Current Change\r
#define XHC_PORTSC_PRC                  BIT21   // Port Reset Change\r
#define XHC_PORTSC_PLC                  BIT22   // Port Link State Change\r
#define XHC_PORTSC_CEC                  BIT23   // Port Config Error Change\r
#define XHC_PORTSC_CAS                  BIT24   // Cold Attach Status\r
\r
#define XHC_HUB_PORTSC_CCS              BIT0    // Hub's Current Connect Status\r
#define XHC_HUB_PORTSC_PED              BIT1    // Hub's Port Enabled/Disabled\r
#define XHC_HUB_PORTSC_OCA              BIT3    // Hub's Over-current Active\r
#define XHC_HUB_PORTSC_RESET            BIT4    // Hub's Port Reset\r
#define XHC_HUB_PORTSC_PP               BIT9    // Hub's Port Power\r
#define XHC_HUB_PORTSC_CSC              BIT16   // Hub's Connect Status Change\r
#define XHC_HUB_PORTSC_PEC              BIT17   // Hub's Port Enabled/Disabled Change\r
#define XHC_HUB_PORTSC_OCC              BIT19   // Hub's Over-Current Change\r
#define XHC_HUB_PORTSC_PRC              BIT20   // Hub's Port Reset Change\r
#define XHC_HUB_PORTSC_BHRC             BIT21   // Hub's Port Warm Reset Change\r
\r
#define XHC_IMAN_IP                     BIT0    // Interrupt Pending\r
#define XHC_IMAN_IE                     BIT1    // Interrupt Enable\r
\r
#define XHC_IMODI_MASK                  0x0000FFFF  // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK                  0xFFFF0000  // Interrupt Moderation Counter\r
\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8                 MaxSlots;       // Number of Device Slots\r
  UINT16                MaxIntrs:11;    // Number of Interrupters\r
  UINT16                Rsvd:5;\r
  UINT8                 MaxPorts;       // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                Dword;\r
  HCSPARAMS1            Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32                Ist:4;          // Isochronous Scheduling Threshold\r
  UINT32                Erst:4;         // Event Ring Segment Table Max\r
  UINT32                Rsvd:13;\r
  UINT32                ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
  UINT32                Spr:1;          // Scratchpad Restore\r
  UINT32                ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                Dword;\r
  HCSPARAMS2            Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16                Ac64:1;        // 64-bit Addressing Capability\r
  UINT16                Bnc:1;         // BW Negotiation Capability\r
  UINT16                Csz:1;         // Context Size\r
  UINT16                Ppc:1;         // Port Power Control\r
  UINT16                Pind:1;        // Port Indicators\r
  UINT16                Lhrc:1;        // Light HC Reset Capability\r
  UINT16                Ltc:1;         // Latency Tolerance Messaging Capability\r
  UINT16                Nss:1;         // No Secondary SID Support\r
  UINT16                Pae:1;         // Parse All Event Data\r
  UINT16                Rsvd:3;\r
  UINT16                MaxPsaSize:4;  // Maximum Primary Stream Array Size\r
  UINT16                ExtCapReg;     // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                Dword;\r
  HCCPARAMS             Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// XHCi Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   Pi;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
\r
typedef struct {\r
  UINT8                     Length;\r
  UINT8                     DescType;\r
  UINT8                     NumPorts;\r
  UINT16                    HubCharacter;\r
  UINT8                     PwrOn2PwrGood;\r
  UINT8                     HubContrCurrent;\r
  UINT8                     Filler[16];\r
} EFI_USB_HUB_DESCRIPTOR;\r
#pragma pack()\r
\r
//\r
//  Hub Class Feature Selector for Clear Port Feature Request\r
//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
//\r
typedef enum {\r
  Usb3PortBHPortReset          = 28,\r
  Usb3PortBHPortResetChange    = 29\r
} XHC_PORT_FEATURE;\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Structure to map the hardware port states to feature selector for clear port feature request.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  Selector;\r
} USB_CLEAR_PORT_MAP;\r
\r
/**\r
  Read XHCI Operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
\r
  @retval the register content read.\r
\r
**/\r
UINT32\r
XhcPeiReadOpReg (\r
  IN  PEI_XHC_DEV       *Xhc,\r
  IN  UINT32            Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
  @param Data           The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteOpReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcPeiClearOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit of the register to wait for.\r
  @param  WaitToSet     Wait the bit to set or clear.\r
  @param  Timeout       The time to wait before abort (in microsecond, us).\r
\r
  @retval EFI_SUCCESS   The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT   The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcPeiWaitOpRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit,\r
  IN BOOLEAN            WaitToSet,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Read XHCI door bell register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the door bell register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcPeiReadDoorBellReg (\r
  IN  PEI_XHC_DEV       *Xhc,\r
  IN  UINT32            Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the door bell register.\r
  @param  Data          The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteDoorBellReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcPeiReadRuntimeReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN  UINT32            Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Data          The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteRuntimeReg (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetRuntimeRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiClearRuntimeRegBit (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Check whether Xhc is halted.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          The controller is halted.\r
  @retval FALSE         The controller isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsHalt (\r
  IN PEI_XHC_DEV        *Xhc\r
  );\r
\r
/**\r
  Check whether system error occurred.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          System error happened.\r
  @retval FALSE         No system error.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsSysError (\r
  IN PEI_XHC_DEV        *Xhc\r
  );\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_TIMEOUT   The transfer failed due to time out.\r
  @retval Others        Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
XhcPeiResetHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_TIMEOUT   Failed to halt the controller before Timeout.\r
  @retval EFI_SUCCESS   The XHCI is halt.\r
\r
**/\r
EFI_STATUS\r
XhcPeiHaltHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Set the XHCI to run.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_SUCCESS   The XHCI is running.\r
  @retval Others        Failed to set the XHCI to run.\r
\r
**/\r
EFI_STATUS\r
XhcPeiRunHC (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
#endif\r
Commit	Line	Data
d987459f SZ	1	/** @file\r
	2	Private Header file for Usb Host Controller PEIM\r
	3	\r
	4	Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions\r
	8	of the BSD License which accompanies this distribution. The\r
	9	full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	#ifndef _EFI_PEI_XHCI_REG_H_\r
	18	#define _EFI_PEI_XHCI_REG_H_\r
	19	\r
	20	//\r
	21	// Capability registers offset\r
	22	//\r
	23	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	24	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	25	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	26	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	27	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	28	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	29	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	30	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
	31	\r
	32	//\r
	33	// Operational registers offset\r
	34	//\r
	35	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	36	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	37	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	38	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	39	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	40	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	41	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	42	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
	43	\r
	44	//\r
	45	// Runtime registers offset\r
	46	//\r
	47	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	48	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
	49	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
	50	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
	51	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
	52	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
	53	\r
	54	//\r
	55	// Register Bit Definition\r
	56	//\r
	57	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	58	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	59	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	60	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	61	\r
	62	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	63	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	64	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
65	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
66	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
67	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
68	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
69	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
70	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
71	\r
72	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
73	\r
74	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
75	#define XHC_CRCR_CS BIT1 // Command Stop\r
76	#define XHC_CRCR_CA BIT2 // Command Abort\r
77	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
78	\r
79	#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled\r
80	\r
81	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
82	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
83	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
84	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
85	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
86	#define XHC_PORTSC_PP BIT9 // Port Power\r
87	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12) // Port Speed\r
88	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
89	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
90	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
91	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
92	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
93	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
94	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
95	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
96	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
97	\r
98	#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
99	#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
100	#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
101	#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
102	#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
103	#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
104	#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
105	#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
106	#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
107	#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
108	\r
109	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
110	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
111	\r
112	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
113	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
114	\r
115	\r
116	#pragma pack (1)\r
117	typedef struct {\r
118	UINT8 MaxSlots; // Number of Device Slots\r
119	UINT16 MaxIntrs:11; // Number of Interrupters\r
120	UINT16 Rsvd:5;\r
121	UINT8 MaxPorts; // Number of Ports\r
122	} HCSPARAMS1;\r
123	\r
124	//\r
125	// Structural Parameters 1 Register Bitmap Definition\r
126	//\r
127	typedef union {\r
128	UINT32 Dword;\r
129	HCSPARAMS1 Data;\r
130	} XHC_HCSPARAMS1;\r
131	\r
132	typedef struct {\r
133	UINT32 Ist:4; // Isochronous Scheduling Threshold\r
134	UINT32 Erst:4; // Event Ring Segment Table Max\r
135	UINT32 Rsvd:13;\r
136	UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
137	UINT32 Spr:1; // Scratchpad Restore\r
138	UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
139	} HCSPARAMS2;\r
140	\r
141	//\r
142	// Structural Parameters 2 Register Bitmap Definition\r
143	//\r
144	typedef union {\r
145	UINT32 Dword;\r
146	HCSPARAMS2 Data;\r
147	} XHC_HCSPARAMS2;\r
148	\r
149	typedef struct {\r
150	UINT16 Ac64:1; // 64-bit Addressing Capability\r
151	UINT16 Bnc:1; // BW Negotiation Capability\r
152	UINT16 Csz:1; // Context Size\r
153	UINT16 Ppc:1; // Port Power Control\r
154	UINT16 Pind:1; // Port Indicators\r
155	UINT16 Lhrc:1; // Light HC Reset Capability\r
156	UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
157	UINT16 Nss:1; // No Secondary SID Support\r
158	UINT16 Pae:1; // Parse All Event Data\r
159	UINT16 Rsvd:3;\r
160	UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
161	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
162	} HCCPARAMS;\r
163	\r
164	//\r
165	// Capability Parameters Register Bitmap Definition\r
166	//\r
167	typedef union {\r
168	UINT32 Dword;\r
169	HCCPARAMS Data;\r
170	} XHC_HCCPARAMS;\r
171	\r
172	#pragma pack ()\r
173	\r
174	//\r
175	// XHCi Data and Ctrl Structures\r
176	//\r
177	#pragma pack(1)\r
178	typedef struct {\r
179	UINT8 Pi;\r
180	UINT8 SubClassCode;\r
181	UINT8 BaseCode;\r
182	} USB_CLASSC;\r
183	\r
184	typedef struct {\r
185	UINT8 Length;\r
186	UINT8 DescType;\r
187	UINT8 NumPorts;\r
188	UINT16 HubCharacter;\r
189	UINT8 PwrOn2PwrGood;\r
190	UINT8 HubContrCurrent;\r
191	UINT8 Filler[16];\r
192	} EFI_USB_HUB_DESCRIPTOR;\r
193	#pragma pack()\r
194	\r
195	//\r
196	// Hub Class Feature Selector for Clear Port Feature Request\r
197	// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
198	// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
199	//\r
200	typedef enum {\r
201	Usb3PortBHPortReset = 28,\r
202	Usb3PortBHPortResetChange = 29\r
203	} XHC_PORT_FEATURE;\r
204	\r
205	//\r
206	// Structure to map the hardware port states to the\r
207	// UEFI's port states.\r
208	//\r
209	typedef struct {\r
210	UINT32 HwState;\r
211	UINT16 UefiState;\r
212	} USB_PORT_STATE_MAP;\r
213	\r
214	//\r
215	// Structure to map the hardware port states to feature selector for clear port feature request.\r
216	//\r
217	typedef struct {\r
218	UINT32 HwState;\r
219	UINT16 Selector;\r
220	} USB_CLEAR_PORT_MAP;\r
221	\r
222	/**\r
223	Read XHCI Operation register.\r
224	\r
225	@param Xhc The XHCI device.\r
226	@param Offset The operation register offset.\r
227	\r
228	@retval the register content read.\r
229	\r
230	**/\r
231	UINT32\r
232	XhcPeiReadOpReg (\r
233	IN PEI_XHC_DEV *Xhc,\r
234	IN UINT32 Offset\r
235	);\r
236	\r
237	/**\r
238	Write the data to the XHCI operation register.\r
239	\r
240	@param Xhc The XHCI device.\r
241	@param Offset The operation register offset.\r
242	@param Data The data to write.\r
243	\r
244	**/\r
245	VOID\r
246	XhcPeiWriteOpReg (\r
247	IN PEI_XHC_DEV *Xhc,\r
248	IN UINT32 Offset,\r
249	IN UINT32 Data\r
250	);\r
251	\r
252	/**\r
253	Set one bit of the operational register while keeping other bits.\r
254	\r
255	@param Xhc The XHCI device.\r
256	@param Offset The offset of the operational register.\r
257	@param Bit The bit mask of the register to set.\r
258	\r
259	**/\r
260	VOID\r
261	XhcPeiSetOpRegBit (\r
262	IN PEI_XHC_DEV *Xhc,\r
263	IN UINT32 Offset,\r
264	IN UINT32 Bit\r
265	);\r
266	\r
267	/**\r
268	Clear one bit of the operational register while keeping other bits.\r
269	\r
270	@param Xhc The XHCI device.\r
271	@param Offset The offset of the operational register.\r
272	@param Bit The bit mask of the register to clear.\r
273	\r
274	**/\r
275	VOID\r
276	XhcPeiClearOpRegBit (\r
277	IN PEI_XHC_DEV *Xhc,\r
278	IN UINT32 Offset,\r
279	IN UINT32 Bit\r
280	);\r
281	\r
282	/**\r
283	Wait the operation register's bit as specified by Bit\r
284	to be set (or clear).\r
285	\r
286	@param Xhc The XHCI device.\r
287	@param Offset The offset of the operational register.\r
288	@param Bit The bit of the register to wait for.\r
289	@param WaitToSet Wait the bit to set or clear.\r
290	@param Timeout The time to wait before abort (in microsecond, us).\r
291	\r
292	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
293	@retval EFI_TIMEOUT The time out occurred.\r
294	\r
295	**/\r
296	EFI_STATUS\r
297	XhcPeiWaitOpRegBit (\r
298	IN PEI_XHC_DEV *Xhc,\r
299	IN UINT32 Offset,\r
300	IN UINT32 Bit,\r
301	IN BOOLEAN WaitToSet,\r
302	IN UINT32 Timeout\r
303	);\r
304	\r
305	/**\r
306	Read XHCI door bell register.\r
307	\r
308	@param Xhc The XHCI device.\r
309	@param Offset The offset of the door bell register.\r
310	\r
311	@return The register content read\r
312	\r
313	**/\r
314	UINT32\r
315	XhcPeiReadDoorBellReg (\r
316	IN PEI_XHC_DEV *Xhc,\r
317	IN UINT32 Offset\r
318	);\r
319	\r
320	/**\r
321	Write the data to the XHCI door bell register.\r
322	\r
323	@param Xhc The XHCI device.\r
324	@param Offset The offset of the door bell register.\r
325	@param Data The data to write.\r
326	\r
327	**/\r
328	VOID\r
329	XhcPeiWriteDoorBellReg (\r
330	IN PEI_XHC_DEV *Xhc,\r
331	IN UINT32 Offset,\r
332	IN UINT32 Data\r
333	);\r
334	\r
335	/**\r
336	Read XHCI runtime register.\r
337	\r
338	@param Xhc The XHCI device.\r
339	@param Offset The offset of the runtime register.\r
340	\r
341	@return The register content read\r
342	\r
343	**/\r
344	UINT32\r
345	XhcPeiReadRuntimeReg (\r
346	IN PEI_XHC_DEV *Xhc,\r
347	IN UINT32 Offset\r
348	);\r
349	\r
350	/**\r
351	Write the data to the XHCI runtime register.\r
352	\r
353	@param Xhc The XHCI device.\r
354	@param Offset The offset of the runtime register.\r
355	@param Data The data to write.\r
356	\r
357	**/\r
358	VOID\r
359	XhcPeiWriteRuntimeReg (\r
360	IN PEI_XHC_DEV *Xhc,\r
361	IN UINT32 Offset,\r
362	IN UINT32 Data\r
363	);\r
364	\r
365	/**\r
366	Set one bit of the runtime register while keeping other bits.\r
367	\r
368	@param Xhc The XHCI device.\r
369	@param Offset The offset of the runtime register.\r
370	@param Bit The bit mask of the register to set.\r
371	\r
372	**/\r
373	VOID\r
374	XhcPeiSetRuntimeRegBit (\r
375	IN PEI_XHC_DEV *Xhc,\r
376	IN UINT32 Offset,\r
377	IN UINT32 Bit\r
378	);\r
379	\r
380	/**\r
381	Clear one bit of the runtime register while keeping other bits.\r
382	\r
383	@param Xhc The XHCI device.\r
384	@param Offset The offset of the runtime register.\r
385	@param Bit The bit mask of the register to set.\r
386	\r
387	**/\r
388	VOID\r
389	XhcPeiClearRuntimeRegBit (\r
390	IN PEI_XHC_DEV *Xhc,\r
391	IN UINT32 Offset,\r
392	IN UINT32 Bit\r
393	);\r
394	\r
395	/**\r
396	Check whether Xhc is halted.\r
397	\r
398	@param Xhc The XHCI device.\r
399	\r
400	@retval TRUE The controller is halted.\r
401	@retval FALSE The controller isn't halted.\r
402	\r
403	**/\r
404	BOOLEAN\r
405	XhcPeiIsHalt (\r
406	IN PEI_XHC_DEV *Xhc\r
407	);\r
408	\r
409	/**\r
410	Check whether system error occurred.\r
411	\r
412	@param Xhc The XHCI device.\r
413	\r
414	@retval TRUE System error happened.\r
415	@retval FALSE No system error.\r
416	\r
417	**/\r
418	BOOLEAN\r
419	XhcPeiIsSysError (\r
420	IN PEI_XHC_DEV *Xhc\r
421	);\r
422	\r
423	/**\r
424	Reset the host controller.\r
425	\r
426	@param Xhc The XHCI device.\r
427	@param Timeout Time to wait before abort (in millisecond, ms).\r
428	\r
429	@retval EFI_TIMEOUT The transfer failed due to time out.\r
430	@retval Others Failed to reset the host.\r
431	\r
432	**/\r
433	EFI_STATUS\r
434	XhcPeiResetHC (\r
435	IN PEI_XHC_DEV *Xhc,\r
436	IN UINT32 Timeout\r
437	);\r
438	\r
439	/**\r
440	Halt the host controller.\r
441	\r
442	@param Xhc The XHCI device.\r
443	@param Timeout Time to wait before abort.\r
444	\r
445	@retval EFI_TIMEOUT Failed to halt the controller before Timeout.\r
446	@retval EFI_SUCCESS The XHCI is halt.\r
447	\r
448	**/\r
449	EFI_STATUS\r
450	XhcPeiHaltHC (\r
451	IN PEI_XHC_DEV *Xhc,\r
452	IN UINT32 Timeout\r
453	);\r
454	\r
455	/**\r
456	Set the XHCI to run.\r
457	\r
458	@param Xhc The XHCI device.\r
459	@param Timeout Time to wait before abort.\r
460	\r
461	@retval EFI_SUCCESS The XHCI is running.\r
462	@retval Others Failed to set the XHCI to run.\r
463	\r
464	**/\r
465	EFI_STATUS\r
466	XhcPeiRunHC (\r
467	IN PEI_XHC_DEV *Xhc,\r
468	IN UINT32 Timeout\r
469	);\r
470	\r
471	#endif\r