[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciReg.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_PEI_XHCI_REG_H_\r
#define _EFI_PEI_XHCI_REG_H_\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET   0x00             // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET  0x02             // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET  0x04             // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET  0x08             // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET  0x0c             // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET   0x10             // Capability Parameters\r
#define XHC_DBOFF_OFFSET       0x14             // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET      0x18             // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET    0x0000             // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET    0x0004             // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET  0x0008             // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET    0x0014             // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET      0x0018             // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET    0x0030             // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET    0x0038             // Configure Register Offset\r
#define XHC_PORTSC_OFFSET    0x0400             // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET  0x00                // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET     0x20                // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET     0x24                // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET   0x28                // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET   0x30                // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET     0x38                // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN    BIT0                  // Run/Stop\r
#define XHC_USBCMD_RESET  BIT1                  // Host Controller Reset\r
#define XHC_USBCMD_INTE   BIT2                  // Interrupter Enable\r
#define XHC_USBCMD_HSEE   BIT3                  // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT  BIT0                   // Host Controller Halted\r
#define XHC_USBSTS_HSE   BIT2                   // Host System Error\r
#define XHC_USBSTS_EINT  BIT3                   // Event Interrupt\r
#define XHC_USBSTS_PCD   BIT4                   // Port Change Detect\r
#define XHC_USBSTS_SSS   BIT8                   // Save State Status\r
#define XHC_USBSTS_RSS   BIT9                   // Restore State Status\r
#define XHC_USBSTS_SRE   BIT10                  // Save/Restore Error\r
#define XHC_USBSTS_CNR   BIT11                  // Host Controller Not Ready\r
#define XHC_USBSTS_HCE   BIT12                  // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK  0xFFFF               // Page Size\r
\r
#define XHC_CRCR_RCS  BIT0                      // Ring Cycle State\r
#define XHC_CRCR_CS   BIT1                      // Command Stop\r
#define XHC_CRCR_CA   BIT2                      // Command Abort\r
#define XHC_CRCR_CRR  BIT3                      // Command Ring Running\r
\r
#define XHC_CONFIG_MASK  0xFF                   // Max Device Slots Enabled\r
\r
#define XHC_PORTSC_CCS    BIT0                      // Current Connect Status\r
#define XHC_PORTSC_PED    BIT1                      // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA    BIT3                      // Over-current Active\r
#define XHC_PORTSC_RESET  BIT4                      // Port Reset\r
#define XHC_PORTSC_PLS    (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
#define XHC_PORTSC_PP     BIT9                      // Port Power\r
#define XHC_PORTSC_PS     (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
#define XHC_PORTSC_LWS    BIT16                     // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC    BIT17                     // Connect Status Change\r
#define XHC_PORTSC_PEC    BIT18                     // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC    BIT19                     // Warm Port Reset Change\r
#define XHC_PORTSC_OCC    BIT20                     // Over-Current Change\r
#define XHC_PORTSC_PRC    BIT21                     // Port Reset Change\r
#define XHC_PORTSC_PLC    BIT22                     // Port Link State Change\r
#define XHC_PORTSC_CEC    BIT23                     // Port Config Error Change\r
#define XHC_PORTSC_CAS    BIT24                     // Cold Attach Status\r
\r
#define XHC_HUB_PORTSC_CCS    BIT0              // Hub's Current Connect Status\r
#define XHC_HUB_PORTSC_PED    BIT1              // Hub's Port Enabled/Disabled\r
#define XHC_HUB_PORTSC_OCA    BIT3              // Hub's Over-current Active\r
#define XHC_HUB_PORTSC_RESET  BIT4              // Hub's Port Reset\r
#define XHC_HUB_PORTSC_PP     BIT9              // Hub's Port Power\r
#define XHC_HUB_PORTSC_CSC    BIT16             // Hub's Connect Status Change\r
#define XHC_HUB_PORTSC_PEC    BIT17             // Hub's Port Enabled/Disabled Change\r
#define XHC_HUB_PORTSC_OCC    BIT19             // Hub's Over-Current Change\r
#define XHC_HUB_PORTSC_PRC    BIT20             // Hub's Port Reset Change\r
#define XHC_HUB_PORTSC_BHRC   BIT21             // Hub's Port Warm Reset Change\r
\r
#define XHC_IMAN_IP  BIT0                       // Interrupt Pending\r
#define XHC_IMAN_IE  BIT1                       // Interrupt Enable\r
\r
#define XHC_IMODI_MASK  0x0000FFFF                  // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK  0xFFFF0000                  // Interrupt Moderation Counter\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8     MaxSlots;                   // Number of Device Slots\r
  UINT16    MaxIntrs : 11;              // Number of Interrupters\r
  UINT16    Rsvd     : 5;\r
  UINT8     MaxPorts;                   // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32        Dword;\r
  HCSPARAMS1    Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32    Ist          : 4;           // Isochronous Scheduling Threshold\r
  UINT32    Erst         : 4;           // Event Ring Segment Table Max\r
  UINT32    Rsvd         : 13;\r
  UINT32    ScratchBufHi : 5;           // Max Scratchpad Buffers Hi\r
  UINT32    Spr          : 1;           // Scratchpad Restore\r
  UINT32    ScratchBufLo : 5;           // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32        Dword;\r
  HCSPARAMS2    Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16    Ac64       : 1;            // 64-bit Addressing Capability\r
  UINT16    Bnc        : 1;            // BW Negotiation Capability\r
  UINT16    Csz        : 1;            // Context Size\r
  UINT16    Ppc        : 1;            // Port Power Control\r
  UINT16    Pind       : 1;            // Port Indicators\r
  UINT16    Lhrc       : 1;            // Light HC Reset Capability\r
  UINT16    Ltc        : 1;            // Latency Tolerance Messaging Capability\r
  UINT16    Nss        : 1;            // No Secondary SID Support\r
  UINT16    Pae        : 1;            // Parse All Event Data\r
  UINT16    Rsvd       : 3;\r
  UINT16    MaxPsaSize : 4;            // Maximum Primary Stream Array Size\r
  UINT16    ExtCapReg;                 // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32       Dword;\r
  HCCPARAMS    Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// XHCi Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8    Pi;\r
  UINT8    SubClassCode;\r
  UINT8    BaseCode;\r
} USB_CLASSC;\r
\r
typedef struct {\r
  UINT8     Length;\r
  UINT8     DescType;\r
  UINT8     NumPorts;\r
  UINT16    HubCharacter;\r
  UINT8     PwrOn2PwrGood;\r
  UINT8     HubContrCurrent;\r
  UINT8     Filler[16];\r
} EFI_USB_HUB_DESCRIPTOR;\r
#pragma pack()\r
\r
//\r
//  Hub Class Feature Selector for Clear Port Feature Request\r
//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
//\r
typedef enum {\r
  Usb3PortBHPortReset       = 28,\r
  Usb3PortBHPortResetChange = 29\r
} XHC_PORT_FEATURE;\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32    HwState;\r
  UINT16    UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Structure to map the hardware port states to feature selector for clear port feature request.\r
//\r
typedef struct {\r
  UINT32    HwState;\r
  UINT16    Selector;\r
} USB_CLEAR_PORT_MAP;\r
\r
/**\r
  Read XHCI Operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
\r
  @retval the register content read.\r
\r
**/\r
UINT32\r
XhcPeiReadOpReg (\r
  IN  PEI_XHC_DEV  *Xhc,\r
  IN  UINT32       Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI operation register.\r
\r
  @param Xhc            The XHCI device.\r
  @param Offset         The operation register offset.\r
  @param Data           The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteOpReg (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetOpRegBit (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcPeiClearOpRegBit (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the operational register.\r
  @param  Bit           The bit of the register to wait for.\r
  @param  WaitToSet     Wait the bit to set or clear.\r
  @param  Timeout       The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS   The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT   The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcPeiWaitOpRegBit (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Bit,\r
  IN BOOLEAN      WaitToSet,\r
  IN UINT32       Timeout\r
  );\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the door bell register.\r
  @param  Data          The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteDoorBellReg (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Data\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcPeiReadRuntimeReg (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN  UINT32      Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Data          The data to write.\r
\r
**/\r
VOID\r
XhcPeiWriteRuntimeReg (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiSetRuntimeRegBit (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Offset        The offset of the runtime register.\r
  @param  Bit           The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcPeiClearRuntimeRegBit (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Offset,\r
  IN UINT32       Bit\r
  );\r
\r
/**\r
  Check whether Xhc is halted.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          The controller is halted.\r
  @retval FALSE         The controller isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsHalt (\r
  IN PEI_XHC_DEV  *Xhc\r
  );\r
\r
/**\r
  Check whether system error occurred.\r
\r
  @param  Xhc           The XHCI device.\r
\r
  @retval TRUE          System error happened.\r
  @retval FALSE         No system error.\r
\r
**/\r
BOOLEAN\r
XhcPeiIsSysError (\r
  IN PEI_XHC_DEV  *Xhc\r
  );\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_TIMEOUT   The transfer failed due to time out.\r
  @retval Others        Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
XhcPeiResetHC (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Timeout\r
  );\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_TIMEOUT   Failed to halt the controller before Timeout.\r
  @retval EFI_SUCCESS   The XHCI is halt.\r
\r
**/\r
EFI_STATUS\r
XhcPeiHaltHC (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Timeout\r
  );\r
\r
/**\r
  Set the XHCI to run.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Timeout       Time to wait before abort.\r
\r
  @retval EFI_SUCCESS   The XHCI is running.\r
  @retval Others        Failed to set the XHCI to run.\r
\r
**/\r
EFI_STATUS\r
XhcPeiRunHC (\r
  IN PEI_XHC_DEV  *Xhc,\r
  IN UINT32       Timeout\r
  );\r
\r
#endif\r
Commit	Line	Data
d987459f SZ	1	/** @file\r
	2	Private Header file for Usb Host Controller PEIM\r
	3	\r
4a723d3d	4	Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
d987459f	5	\r
9d510e61	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
d987459f SZ	7	\r
	8	**/\r
	9	\r
	10	#ifndef _EFI_PEI_XHCI_REG_H_\r
	11	#define _EFI_PEI_XHCI_REG_H_\r
	12	\r
	13	//\r
	14	// Capability registers offset\r
	15	//\r
1436aea4 MK	16	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	17	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	18	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	19	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	20	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	21	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	22	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	23	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
d987459f SZ	24	\r
	25	//\r
	26	// Operational registers offset\r
	27	//\r
1436aea4 MK	28	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	29	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	30	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	31	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	32	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	33	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	34	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	35	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
d987459f SZ	36	\r
	37	//\r
	38	// Runtime registers offset\r
	39	//\r
1436aea4 MK	40	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	41	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
	42	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
	43	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
	44	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
	45	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
d987459f SZ	46	\r
	47	//\r
	48	// Register Bit Definition\r
	49	//\r
1436aea4 MK	50	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	51	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	52	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	53	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	54	\r
	55	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	56	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	57	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
	58	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
	59	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
	60	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
	61	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
	62	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
	63	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
	64	\r
	65	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
	66	\r
	67	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
	68	#define XHC_CRCR_CS BIT1 // Command Stop\r
	69	#define XHC_CRCR_CA BIT2 // Command Abort\r
	70	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
	71	\r
	72	#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled\r
	73	\r
	74	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
	75	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
	76	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
	77	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
	78	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
	79	#define XHC_PORTSC_PP BIT9 // Port Power\r
	80	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12\|BIT13) // Port Speed\r
	81	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
	82	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
	83	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
	84	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
	85	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
	86	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
	87	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
	88	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
	89	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
	90	\r
	91	#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
	92	#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
	93	#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
	94	#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
	95	#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
	96	#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
	97	#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
	98	#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
	99	#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
	100	#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
	101	\r
	102	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
	103	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
	104	\r
	105	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
	106	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
d987459f SZ	107	\r
	108	#pragma pack (1)\r
	109	typedef struct {\r
1436aea4 MK	110	UINT8 MaxSlots; // Number of Device Slots\r
	111	UINT16 MaxIntrs : 11; // Number of Interrupters\r
	112	UINT16 Rsvd : 5;\r
	113	UINT8 MaxPorts; // Number of Ports\r
d987459f SZ	114	} HCSPARAMS1;\r
	115	\r
	116	//\r
	117	// Structural Parameters 1 Register Bitmap Definition\r
	118	//\r
	119	typedef union {\r
1436aea4 MK	120	UINT32 Dword;\r
1436aea4 MK	121	HCSPARAMS1 Data;\r
d987459f SZ	122	} XHC_HCSPARAMS1;\r
	123	\r
	124	typedef struct {\r
1436aea4 MK	125	UINT32 Ist : 4; // Isochronous Scheduling Threshold\r
	126	UINT32 Erst : 4; // Event Ring Segment Table Max\r
	127	UINT32 Rsvd : 13;\r
	128	UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi\r
	129	UINT32 Spr : 1; // Scratchpad Restore\r
	130	UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo\r
d987459f SZ	131	} HCSPARAMS2;\r
	132	\r
	133	//\r
	134	// Structural Parameters 2 Register Bitmap Definition\r
	135	//\r
	136	typedef union {\r
1436aea4 MK	137	UINT32 Dword;\r
1436aea4 MK	138	HCSPARAMS2 Data;\r
d987459f SZ	139	} XHC_HCSPARAMS2;\r
	140	\r
	141	typedef struct {\r
1436aea4 MK	142	UINT16 Ac64 : 1; // 64-bit Addressing Capability\r
	143	UINT16 Bnc : 1; // BW Negotiation Capability\r
	144	UINT16 Csz : 1; // Context Size\r
	145	UINT16 Ppc : 1; // Port Power Control\r
	146	UINT16 Pind : 1; // Port Indicators\r
	147	UINT16 Lhrc : 1; // Light HC Reset Capability\r
	148	UINT16 Ltc : 1; // Latency Tolerance Messaging Capability\r
	149	UINT16 Nss : 1; // No Secondary SID Support\r
	150	UINT16 Pae : 1; // Parse All Event Data\r
	151	UINT16 Rsvd : 3;\r
	152	UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size\r
	153	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
d987459f SZ	154	} HCCPARAMS;\r
	155	\r
	156	//\r
	157	// Capability Parameters Register Bitmap Definition\r
	158	//\r
	159	typedef union {\r
1436aea4 MK	160	UINT32 Dword;\r
1436aea4 MK	161	HCCPARAMS Data;\r
d987459f SZ	162	} XHC_HCCPARAMS;\r
	163	\r
	164	#pragma pack ()\r
	165	\r
	166	//\r
	167	// XHCi Data and Ctrl Structures\r
	168	//\r
	169	#pragma pack(1)\r
	170	typedef struct {\r
1436aea4 MK	171	UINT8 Pi;\r
	172	UINT8 SubClassCode;\r
	173	UINT8 BaseCode;\r
d987459f SZ	174	} USB_CLASSC;\r
	175	\r
	176	typedef struct {\r
1436aea4 MK	177	UINT8 Length;\r
	178	UINT8 DescType;\r
	179	UINT8 NumPorts;\r
	180	UINT16 HubCharacter;\r
	181	UINT8 PwrOn2PwrGood;\r
	182	UINT8 HubContrCurrent;\r
	183	UINT8 Filler[16];\r
d987459f SZ	184	} EFI_USB_HUB_DESCRIPTOR;\r
	185	#pragma pack()\r
	186	\r
	187	//\r
	188	// Hub Class Feature Selector for Clear Port Feature Request\r
	189	// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
	190	// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
	191	//\r
	192	typedef enum {\r
1436aea4 MK	193	Usb3PortBHPortReset = 28,\r
1436aea4 MK	194	Usb3PortBHPortResetChange = 29\r
d987459f SZ	195	} XHC_PORT_FEATURE;\r
	196	\r
	197	//\r
	198	// Structure to map the hardware port states to the\r
	199	// UEFI's port states.\r
	200	//\r
	201	typedef struct {\r
1436aea4 MK	202	UINT32 HwState;\r
1436aea4 MK	203	UINT16 UefiState;\r
d987459f SZ	204	} USB_PORT_STATE_MAP;\r
	205	\r
	206	//\r
	207	// Structure to map the hardware port states to feature selector for clear port feature request.\r
	208	//\r
	209	typedef struct {\r
1436aea4 MK	210	UINT32 HwState;\r
1436aea4 MK	211	UINT16 Selector;\r
d987459f SZ	212	} USB_CLEAR_PORT_MAP;\r
	213	\r
	214	/**\r
	215	Read XHCI Operation register.\r
	216	\r
	217	@param Xhc The XHCI device.\r
	218	@param Offset The operation register offset.\r
	219	\r
	220	@retval the register content read.\r
	221	\r
	222	**/\r
	223	UINT32\r
	224	XhcPeiReadOpReg (\r
1436aea4 MK	225	IN PEI_XHC_DEV *Xhc,\r
1436aea4 MK	226	IN UINT32 Offset\r
d987459f SZ	227	);\r
	228	\r
	229	/**\r
	230	Write the data to the XHCI operation register.\r
	231	\r
	232	@param Xhc The XHCI device.\r
	233	@param Offset The operation register offset.\r
	234	@param Data The data to write.\r
	235	\r
	236	**/\r
	237	VOID\r
	238	XhcPeiWriteOpReg (\r
1436aea4 MK	239	IN PEI_XHC_DEV *Xhc,\r
	240	IN UINT32 Offset,\r
	241	IN UINT32 Data\r
d987459f SZ	242	);\r
	243	\r
	244	/**\r
	245	Set one bit of the operational register while keeping other bits.\r
	246	\r
	247	@param Xhc The XHCI device.\r
	248	@param Offset The offset of the operational register.\r
	249	@param Bit The bit mask of the register to set.\r
	250	\r
	251	**/\r
	252	VOID\r
	253	XhcPeiSetOpRegBit (\r
1436aea4 MK	254	IN PEI_XHC_DEV *Xhc,\r
	255	IN UINT32 Offset,\r
	256	IN UINT32 Bit\r
d987459f SZ	257	);\r
	258	\r
	259	/**\r
	260	Clear one bit of the operational register while keeping other bits.\r
	261	\r
	262	@param Xhc The XHCI device.\r
	263	@param Offset The offset of the operational register.\r
	264	@param Bit The bit mask of the register to clear.\r
	265	\r
	266	**/\r
	267	VOID\r
	268	XhcPeiClearOpRegBit (\r
1436aea4 MK	269	IN PEI_XHC_DEV *Xhc,\r
	270	IN UINT32 Offset,\r
	271	IN UINT32 Bit\r
d987459f SZ	272	);\r
	273	\r
	274	/**\r
	275	Wait the operation register's bit as specified by Bit\r
	276	to be set (or clear).\r
	277	\r
	278	@param Xhc The XHCI device.\r
	279	@param Offset The offset of the operational register.\r
	280	@param Bit The bit of the register to wait for.\r
	281	@param WaitToSet Wait the bit to set or clear.\r
2f6ef874	282	@param Timeout The time to wait before abort (in millisecond, ms).\r
d987459f SZ	283	\r
	284	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
	285	@retval EFI_TIMEOUT The time out occurred.\r
	286	\r
	287	**/\r
	288	EFI_STATUS\r
	289	XhcPeiWaitOpRegBit (\r
1436aea4 MK	290	IN PEI_XHC_DEV *Xhc,\r
	291	IN UINT32 Offset,\r
	292	IN UINT32 Bit,\r
	293	IN BOOLEAN WaitToSet,\r
	294	IN UINT32 Timeout\r
d987459f SZ	295	);\r
d987459f SZ	296	\r
d987459f SZ	297	/**\r
	298	Write the data to the XHCI door bell register.\r
	299	\r
	300	@param Xhc The XHCI device.\r
	301	@param Offset The offset of the door bell register.\r
	302	@param Data The data to write.\r
	303	\r
	304	**/\r
	305	VOID\r
	306	XhcPeiWriteDoorBellReg (\r
1436aea4 MK	307	IN PEI_XHC_DEV *Xhc,\r
	308	IN UINT32 Offset,\r
	309	IN UINT32 Data\r
d987459f SZ	310	);\r
	311	\r
	312	/**\r
	313	Read XHCI runtime register.\r
	314	\r
	315	@param Xhc The XHCI device.\r
	316	@param Offset The offset of the runtime register.\r
	317	\r
	318	@return The register content read\r
	319	\r
	320	**/\r
	321	UINT32\r
	322	XhcPeiReadRuntimeReg (\r
1436aea4 MK	323	IN PEI_XHC_DEV *Xhc,\r
1436aea4 MK	324	IN UINT32 Offset\r
d987459f SZ	325	);\r
	326	\r
	327	/**\r
	328	Write the data to the XHCI runtime register.\r
	329	\r
	330	@param Xhc The XHCI device.\r
	331	@param Offset The offset of the runtime register.\r
	332	@param Data The data to write.\r
	333	\r
	334	**/\r
	335	VOID\r
	336	XhcPeiWriteRuntimeReg (\r
1436aea4 MK	337	IN PEI_XHC_DEV *Xhc,\r
	338	IN UINT32 Offset,\r
	339	IN UINT32 Data\r
d987459f SZ	340	);\r
	341	\r
	342	/**\r
	343	Set one bit of the runtime register while keeping other bits.\r
	344	\r
	345	@param Xhc The XHCI device.\r
	346	@param Offset The offset of the runtime register.\r
	347	@param Bit The bit mask of the register to set.\r
	348	\r
	349	**/\r
	350	VOID\r
	351	XhcPeiSetRuntimeRegBit (\r
1436aea4 MK	352	IN PEI_XHC_DEV *Xhc,\r
	353	IN UINT32 Offset,\r
	354	IN UINT32 Bit\r
d987459f SZ	355	);\r
	356	\r
	357	/**\r
	358	Clear one bit of the runtime register while keeping other bits.\r
	359	\r
	360	@param Xhc The XHCI device.\r
	361	@param Offset The offset of the runtime register.\r
	362	@param Bit The bit mask of the register to set.\r
	363	\r
	364	**/\r
	365	VOID\r
	366	XhcPeiClearRuntimeRegBit (\r
1436aea4 MK	367	IN PEI_XHC_DEV *Xhc,\r
	368	IN UINT32 Offset,\r
	369	IN UINT32 Bit\r
d987459f SZ	370	);\r
	371	\r
	372	/**\r
	373	Check whether Xhc is halted.\r
	374	\r
	375	@param Xhc The XHCI device.\r
	376	\r
	377	@retval TRUE The controller is halted.\r
	378	@retval FALSE The controller isn't halted.\r
	379	\r
	380	**/\r
	381	BOOLEAN\r
	382	XhcPeiIsHalt (\r
1436aea4	383	IN PEI_XHC_DEV *Xhc\r
d987459f SZ	384	);\r
	385	\r
	386	/**\r
	387	Check whether system error occurred.\r
	388	\r
	389	@param Xhc The XHCI device.\r
	390	\r
	391	@retval TRUE System error happened.\r
	392	@retval FALSE No system error.\r
	393	\r
	394	**/\r
	395	BOOLEAN\r
	396	XhcPeiIsSysError (\r
1436aea4	397	IN PEI_XHC_DEV *Xhc\r
d987459f SZ	398	);\r
	399	\r
	400	/**\r
	401	Reset the host controller.\r
	402	\r
	403	@param Xhc The XHCI device.\r
	404	@param Timeout Time to wait before abort (in millisecond, ms).\r
	405	\r
	406	@retval EFI_TIMEOUT The transfer failed due to time out.\r
	407	@retval Others Failed to reset the host.\r
	408	\r
	409	**/\r
	410	EFI_STATUS\r
	411	XhcPeiResetHC (\r
1436aea4 MK	412	IN PEI_XHC_DEV *Xhc,\r
1436aea4 MK	413	IN UINT32 Timeout\r
d987459f SZ	414	);\r
	415	\r
	416	/**\r
	417	Halt the host controller.\r
	418	\r
	419	@param Xhc The XHCI device.\r
	420	@param Timeout Time to wait before abort.\r
	421	\r
	422	@retval EFI_TIMEOUT Failed to halt the controller before Timeout.\r
	423	@retval EFI_SUCCESS The XHCI is halt.\r
	424	\r
	425	**/\r
	426	EFI_STATUS\r
	427	XhcPeiHaltHC (\r
1436aea4 MK	428	IN PEI_XHC_DEV *Xhc,\r
1436aea4 MK	429	IN UINT32 Timeout\r
d987459f SZ	430	);\r
	431	\r
	432	/**\r
	433	Set the XHCI to run.\r
	434	\r
	435	@param Xhc The XHCI device.\r
	436	@param Timeout Time to wait before abort.\r
	437	\r
	438	@retval EFI_SUCCESS The XHCI is running.\r
	439	@retval Others Failed to set the XHCI to run.\r
	440	\r
	441	**/\r
	442	EFI_STATUS\r
	443	XhcPeiRunHC (\r
1436aea4 MK	444	IN PEI_XHC_DEV *Xhc,\r
1436aea4 MK	445	IN UINT32 Timeout\r
d987459f SZ	446	);\r
	447	\r
	448	#endif\r