[mirror_edk2.git] / MdeModulePkg / Bus / Sd / EmmcBlockIoPei / EmmcHci.c

/** @file\r
\r
  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "EmmcBlockIoPei.h"\r
\r
/**\r
  Read/Write specified EMMC host controller mmio register.\r
\r
  @param[in]      Address      The address of the mmio register to be read/written.\r
  @param[in]      Read         A boolean to indicate it's read or write operation.\r
  @param[in]      Count        The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in, out] Data         For read operations, the destination buffer to store\r
                               the results. For write operations, the source buffer\r
                               to write data from. The caller is responsible for\r
                               having ownership of the data buffer and ensuring its\r
                               size not less than Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The Address or the Data or the Count is not valid.\r
  @retval EFI_SUCCESS           The read/write operation succeeds.\r
  @retval Others                The read/write operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcRwMmio (\r
  IN     UINTN                 Address,\r
  IN     BOOLEAN               Read,\r
  IN     UINT8                 Count,\r
  IN OUT VOID                  *Data\r
  )\r
{\r
  if ((Address == 0) || (Data == NULL))  {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  switch (Count) {\r
    case 1:\r
      if (Read) {\r
        *(UINT8*)Data = MmioRead8 (Address);\r
      } else {\r
        MmioWrite8 (Address, *(UINT8*)Data);\r
      }\r
      break;\r
    case 2:\r
      if (Read) {\r
        *(UINT16*)Data = MmioRead16 (Address);\r
      } else {\r
        MmioWrite16 (Address, *(UINT16*)Data);\r
      }\r
      break;\r
    case 4:\r
      if (Read) {\r
        *(UINT32*)Data = MmioRead32 (Address);\r
      } else {\r
        MmioWrite32 (Address, *(UINT32*)Data);\r
      }\r
      break;\r
    case 8:\r
      if (Read) {\r
        *(UINT64*)Data = MmioRead64 (Address);\r
      } else {\r
        MmioWrite64 (Address, *(UINT64*)Data);\r
      }\r
      break;\r
    default:\r
      ASSERT (FALSE);\r
      return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Do OR operation with the value of the specified EMMC host controller mmio register.\r
\r
  @param[in] Address           The address of the mmio register to be read/written.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] OrData            The pointer to the data used to do OR operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The Address or the OrData or the Count is not valid.\r
  @retval EFI_SUCCESS           The OR operation succeeds.\r
  @retval Others                The OR operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcOrMmio (\r
  IN  UINTN                    Address,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *OrData\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  UINT64                       Data;\r
  UINT64                       Or;\r
\r
  Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if (Count == 1) {\r
    Or = *(UINT8*) OrData;\r
  } else if (Count == 2) {\r
    Or = *(UINT16*) OrData;\r
  } else if (Count == 4) {\r
    Or = *(UINT32*) OrData;\r
  } else if (Count == 8) {\r
    Or = *(UINT64*) OrData;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Data  |= Or;\r
  Status = EmmcPeimHcRwMmio (Address, FALSE, Count, &Data);\r
\r
  return Status;\r
}\r
\r
/**\r
  Do AND operation with the value of the specified EMMC host controller mmio register.\r
\r
  @param[in] Address           The address of the mmio register to be read/written.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] AndData           The pointer to the data used to do AND operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The Address or the AndData or the Count is not valid.\r
  @retval EFI_SUCCESS           The AND operation succeeds.\r
  @retval Others                The AND operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcAndMmio (\r
  IN  UINTN                    Address,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *AndData\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  UINT64                       Data;\r
  UINT64                       And;\r
\r
  Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if (Count == 1) {\r
    And = *(UINT8*) AndData;\r
  } else if (Count == 2) {\r
    And = *(UINT16*) AndData;\r
  } else if (Count == 4) {\r
    And = *(UINT32*) AndData;\r
  } else if (Count == 8) {\r
    And = *(UINT64*) AndData;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Data  &= And;\r
  Status = EmmcPeimHcRwMmio (Address, FALSE, Count, &Data);\r
\r
  return Status;\r
}\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  Address       The address of the mmio register to be checked.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
\r
  @retval EFI_NOT_READY     The MMIO register hasn't set to the expected value.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcCheckMmioSet (\r
  IN  UINTN                     Address,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue\r
  )\r
{\r
  EFI_STATUS            Status;\r
  UINT64                Value;\r
\r
  //\r
  // Access PCI MMIO space to see if the value is the tested one.\r
  //\r
  Value  = 0;\r
  Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Value);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Value &= MaskValue;\r
\r
  if (Value == TestValue) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  return EFI_NOT_READY;\r
}\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  Address       The address of the mmio register to wait.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
  @param[in]  Timeout       The time out value for wait memory set, uses 1\r
                            microsecond as a unit.\r
\r
  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout\r
                            range.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcWaitMmioSet (\r
  IN  UINTN                     Address,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue,\r
  IN  UINT64                    Timeout\r
  )\r
{\r
  EFI_STATUS            Status;\r
  BOOLEAN               InfiniteWait;\r
\r
  if (Timeout == 0) {\r
    InfiniteWait = TRUE;\r
  } else {\r
    InfiniteWait = FALSE;\r
  }\r
\r
  while (InfiniteWait || (Timeout > 0)) {\r
    Status = EmmcPeimHcCheckMmioSet (\r
               Address,\r
               Count,\r
               MaskValue,\r
               TestValue\r
               );\r
    if (Status != EFI_NOT_READY) {\r
      return Status;\r
    }\r
\r
    //\r
    // Stall for 1 microsecond.\r
    //\r
    MicroSecondDelay (1);\r
\r
    Timeout--;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Software reset the specified EMMC host controller and enable all interrupts.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The software reset executes successfully.\r
  @retval Others            The software reset fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcReset (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     SwReset;\r
\r
  SwReset = 0xFF;\r
  Status  = EmmcPeimHcRwMmio (Bar + EMMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimHcReset: write full 1 fails: %r\n", Status));\r
    return Status;\r
  }\r
\r
  Status = EmmcPeimHcWaitMmioSet (\r
             Bar + EMMC_HC_SW_RST,\r
             sizeof (SwReset),\r
             0xFF,\r
             0x00,\r
             EMMC_TIMEOUT\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_INFO, "EmmcPeimHcReset: reset done with %r\n", Status));\r
    return Status;\r
  }\r
  //\r
  // Enable all interrupt after reset all.\r
  //\r
  Status = EmmcPeimHcEnableInterrupt (Bar);\r
\r
  return Status;\r
}\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcEnableInterrupt (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT16                    IntStatus;\r
\r
  //\r
  // Enable all bits in Error Interrupt Status Enable Register\r
  //\r
  IntStatus = 0xFFFF;\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Enable all bits in Normal Interrupt Status Enable Register\r
  //\r
  IntStatus = 0xFFFF;\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
\r
  return Status;\r
}\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  Bar             The mmio base address of the slot to be accessed.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcGetCapability (\r
  IN     UINTN              Bar,\r
     OUT EMMC_HC_SLOT_CAP   *Capability\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT64                    Cap;\r
\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  CopyMem (Capability, &Cap, sizeof (Cap));\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Detect whether there is a EMMC card attached at the specified EMMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  Bar           The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       There is a EMMC card attached.\r
  @retval EFI_NO_MEDIA      There is not a EMMC card attached.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcCardDetect (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT16                    Data;\r
  UINT32                    PresentState;\r
\r
  //\r
  // Check Normal Interrupt Status Register\r
  //\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if ((Data & (BIT6 | BIT7)) != 0) {\r
    //\r
    // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r
    //\r
    Data  &= BIT6 | BIT7;\r
    Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  //\r
  // Check Present State Register to see if there is a card presented.\r
  //\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if ((PresentState & BIT16) != 0) {\r
    return EFI_SUCCESS;\r
  } else {\r
    return EFI_NO_MEDIA;\r
  }\r
}\r
\r
/**\r
  Stop EMMC card clock.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
\r
  @param[in]  Bar           The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       Succeed to stop EMMC clock.\r
  @retval Others            Fail to stop EMMC clock.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcStopClock (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT32                    PresentState;\r
  UINT16                    ClockCtrl;\r
\r
  //\r
  // Ensure no SD transactions are occurring on the SD Bus by\r
  // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r
  // in the Present State register to be 0.\r
  //\r
  Status = EmmcPeimHcWaitMmioSet (\r
             Bar + EMMC_HC_PRESENT_STATE,\r
             sizeof (PresentState),\r
             BIT0 | BIT1,\r
             0,\r
             EMMC_TIMEOUT\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Set SD Clock Enable in the Clock Control register to 0\r
  //\r
  ClockCtrl = (UINT16)~BIT2;\r
  Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
  return Status;\r
}\r
\r
/**\r
  EMMC card clock supply.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcClockSupply (\r
  IN UINTN                  Bar,\r
  IN UINT64                 ClockFreq\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EMMC_HC_SLOT_CAP          Capability;\r
  UINT32                    BaseClkFreq;\r
  UINT32                    SettingFreq;\r
  UINT32                    Divisor;\r
  UINT32                    Remainder;\r
  UINT16                    ControllerVer;\r
  UINT16                    ClockCtrl;\r
\r
  //\r
  // Calculate a divisor for SD clock frequency\r
  //\r
  Status = EmmcPeimHcGetCapability (Bar, &Capability);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  ASSERT (Capability.BaseClkFreq != 0);\r
\r
  BaseClkFreq = Capability.BaseClkFreq;\r
\r
  if (ClockFreq == 0) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (ClockFreq > (BaseClkFreq * 1000)) {\r
    ClockFreq = BaseClkFreq * 1000;\r
  }\r
\r
  //\r
  // Calculate the divisor of base frequency.\r
  //\r
  Divisor     = 0;\r
  SettingFreq = BaseClkFreq * 1000;\r
  while (ClockFreq < SettingFreq) {\r
    Divisor++;\r
\r
    SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r
    Remainder   = (BaseClkFreq * 1000) % (2 * Divisor);\r
    if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r
      break;\r
    }\r
    if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r
      SettingFreq ++;\r
    }\r
  }\r
\r
  DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r
\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
  //\r
  if ((ControllerVer & 0xFF) == 2) {\r
    ASSERT (Divisor <= 0x3FF);\r
    ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
  } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
    //\r
    // Only the most significant bit can be used as divisor.\r
    //\r
    if (((Divisor - 1) & Divisor) != 0) {\r
      Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r
    }\r
    ASSERT (Divisor <= 0x80);\r
    ClockCtrl = (Divisor & 0xFF) << 8;\r
  } else {\r
    DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Stop bus clock at first\r
  //\r
  Status = EmmcPeimHcStopClock (Bar);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Supply clock frequency with specified divisor\r
  //\r
  ClockCtrl |= BIT0;\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r
    return Status;\r
  }\r
\r
  //\r
  // Wait Internal Clock Stable in the Clock Control register to be 1\r
  //\r
  Status = EmmcPeimHcWaitMmioSet (\r
             Bar + EMMC_HC_CLOCK_CTRL,\r
             sizeof (ClockCtrl),\r
             BIT1,\r
             BIT1,\r
             EMMC_TIMEOUT\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Set SD Clock Enable in the Clock Control register to 1\r
  //\r
  ClockCtrl = BIT2;\r
  Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
  return Status;\r
}\r
\r
/**\r
  EMMC bus power control.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] PowerCtrl      The value setting to the power control register.\r
\r
  @retval TRUE              There is a EMMC card attached.\r
  @retval FALSE             There is no a EMMC card attached.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcPowerControl (\r
  IN UINTN                  Bar,\r
  IN UINT8                  PowerCtrl\r
  )\r
{\r
  EFI_STATUS                Status;\r
\r
  //\r
  // Clr SD Bus Power\r
  //\r
  PowerCtrl &= (UINT8)~BIT0;\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
  //\r
  PowerCtrl |= BIT0;\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
\r
  return Status;\r
}\r
\r
/**\r
  Set the EMMC bus width.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] BusWidth       The bus width used by the EMMC device, it must be 1, 4 or 8.\r
\r
  @retval EFI_SUCCESS       The bus width is set successfully.\r
  @retval Others            The bus width isn't set successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcSetBusWidth (\r
  IN UINTN                  Bar,\r
  IN UINT16                 BusWidth\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     HostCtrl1;\r
\r
  if (BusWidth == 1) {\r
    HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r
    Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
  } else if (BusWidth == 4) {\r
    Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    HostCtrl1 |= BIT1;\r
    HostCtrl1 &= (UINT8)~BIT5;\r
    Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
  } else if (BusWidth == 8) {\r
    Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    HostCtrl1 &= (UINT8)~BIT1;\r
    HostCtrl1 |= BIT5;\r
    Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
  } else {\r
    ASSERT (FALSE);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Supply EMMC card with lowest clock frequency at initialization.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitClockFreq (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EMMC_HC_SLOT_CAP          Capability;\r
  UINT32                    InitFreq;\r
\r
  //\r
  // Calculate a divisor for SD clock frequency\r
  //\r
  Status = EmmcPeimHcGetCapability (Bar, &Capability);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if (Capability.BaseClkFreq == 0) {\r
    //\r
    // Don't support get Base Clock Frequency information via another method\r
    //\r
    return EFI_UNSUPPORTED;\r
  }\r
  //\r
  // Supply 400KHz clock frequency at initialization phase.\r
  //\r
  InitFreq = 400;\r
  Status = EmmcPeimHcClockSupply (Bar, InitFreq);\r
  return Status;\r
}\r
\r
/**\r
  Supply EMMC card with maximum voltage at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The voltage is supplied successfully.\r
  @retval Others            The voltage isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitPowerVoltage (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EMMC_HC_SLOT_CAP        Capability;\r
  UINT8                     MaxVoltage;\r
  UINT8                     HostCtrl2;\r
\r
  //\r
  // Get the support voltage of the Host Controller\r
  //\r
  Status = EmmcPeimHcGetCapability (Bar, &Capability);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Calculate supported maximum voltage according to SD Bus Voltage Select\r
  //\r
  if (Capability.Voltage33 != 0) {\r
    //\r
    // Support 3.3V\r
    //\r
    MaxVoltage = 0x0E;\r
  } else if (Capability.Voltage30 != 0) {\r
    //\r
    // Support 3.0V\r
    //\r
    MaxVoltage = 0x0C;\r
  } else if (Capability.Voltage18 != 0) {\r
    //\r
    // Support 1.8V\r
    //\r
    MaxVoltage = 0x0A;\r
    HostCtrl2  = BIT3;\r
    Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    MicroSecondDelay (5000);\r
  } else {\r
    ASSERT (FALSE);\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
  //\r
  Status = EmmcPeimHcPowerControl (Bar, MaxVoltage);\r
\r
  return Status;\r
}\r
\r
/**\r
  Initialize the Timeout Control register with most conservative value at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The timeout control register is configured successfully.\r
  @retval Others            The timeout control register isn't configured successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitTimeoutCtrl (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     Timeout;\r
\r
  Timeout = 0x0E;\r
  Status  = EmmcPeimHcRwMmio (Bar + EMMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r
\r
  return Status;\r
}\r
\r
/**\r
  Initial EMMC host controller with lowest clock frequency, max power and max timeout value\r
  at initialization.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The host controller is initialized successfully.\r
  @retval Others            The host controller isn't initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitHost (\r
  IN UINTN                  Bar\r
  )\r
{\r
  EFI_STATUS       Status;\r
\r
  Status = EmmcPeimHcInitClockFreq (Bar);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = EmmcPeimHcInitPowerVoltage (Bar);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = EmmcPeimHcInitTimeoutCtrl (Bar);\r
  return Status;\r
}\r
\r
/**\r
  Turn on/off LED.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] On             The boolean to turn on/off LED.\r
\r
  @retval EFI_SUCCESS       The LED is turned on/off successfully.\r
  @retval Others            The LED isn't turned on/off successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcLedOnOff (\r
  IN UINTN                  Bar,\r
  IN BOOLEAN                On\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINT8                     HostCtrl1;\r
\r
  if (On) {\r
    HostCtrl1 = BIT0;\r
    Status    = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
  } else {\r
    HostCtrl1 = (UINT8)~BIT0;\r
    Status    = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Build ADMA descriptor table for transfer.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.\r
\r
  @param[in] Trb            The pointer to the EMMC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The ADMA descriptor table is created successfully.\r
  @retval Others            The ADMA descriptor table isn't created successfully.\r
\r
**/\r
EFI_STATUS\r
BuildAdmaDescTable (\r
  IN EMMC_TRB               *Trb\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS      Data;\r
  UINT64                    DataLen;\r
  UINT64                    Entries;\r
  UINT32                    Index;\r
  UINT64                    Remaining;\r
  UINT32                    Address;\r
\r
  Data    = Trb->DataPhy;\r
  DataLen = Trb->DataLen;\r
  //\r
  // Only support 32bit ADMA Descriptor Table\r
  //\r
  if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  //\r
  // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
  // for 32-bit address descriptor table.\r
  //\r
  if ((Data & (BIT0 | BIT1)) != 0) {\r
    DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r
  }\r
\r
  Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);\r
\r
  Trb->AdmaDescSize = (UINTN)MultU64x32 (Entries, sizeof (EMMC_HC_ADMA_DESC_LINE));\r
  Trb->AdmaDesc     = EmmcPeimAllocateMem (Trb->Slot->Private->Pool, Trb->AdmaDescSize);\r
  if (Trb->AdmaDesc == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  Remaining = DataLen;\r
  Address   = (UINT32)Data;\r
  for (Index = 0; Index < Entries; Index++) {\r
    if (Remaining <= ADMA_MAX_DATA_PER_LINE) {\r
      Trb->AdmaDesc[Index].Valid = 1;\r
      Trb->AdmaDesc[Index].Act   = 2;\r
      Trb->AdmaDesc[Index].Length  = (UINT16)Remaining;\r
      Trb->AdmaDesc[Index].Address = Address;\r
      break;\r
    } else {\r
      Trb->AdmaDesc[Index].Valid = 1;\r
      Trb->AdmaDesc[Index].Act   = 2;\r
      Trb->AdmaDesc[Index].Length  = 0;\r
      Trb->AdmaDesc[Index].Address = Address;\r
    }\r
\r
    Remaining -= ADMA_MAX_DATA_PER_LINE;\r
    Address   += ADMA_MAX_DATA_PER_LINE;\r
  }\r
\r
  //\r
  // Set the last descriptor line as end of descriptor table\r
  //\r
  Trb->AdmaDesc[Index].End = 1;\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Create a new TRB for the EMMC cmd request.\r
\r
  @param[in] Slot           The slot number of the EMMC card to send the command to.\r
  @param[in] Packet         A pointer to the SD command data structure.\r
\r
  @return Created Trb or NULL.\r
\r
**/\r
EMMC_TRB *\r
EmmcPeimCreateTrb (\r
  IN EMMC_PEIM_HC_SLOT          *Slot,\r
  IN EMMC_COMMAND_PACKET        *Packet\r
  )\r
{\r
  EMMC_TRB                      *Trb;\r
  EFI_STATUS                    Status;\r
  EMMC_HC_SLOT_CAP              Capability;\r
  EDKII_IOMMU_OPERATION         MapOp;\r
  UINTN                         MapLength;\r
\r
  //\r
  // Calculate a divisor for SD clock frequency\r
  //\r
  Status = EmmcPeimHcGetCapability (Slot->EmmcHcBase, &Capability);\r
  if (EFI_ERROR (Status)) {\r
    return NULL;\r
  }\r
\r
  Trb = AllocateZeroPool (sizeof (EMMC_TRB));\r
  if (Trb == NULL) {\r
    return NULL;\r
  }\r
\r
  Trb->Slot      = Slot;\r
  Trb->BlockSize = 0x200;\r
  Trb->Packet    = Packet;\r
  Trb->Timeout   = Packet->Timeout;\r
\r
  if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r
    Trb->Data    = Packet->InDataBuffer;\r
    Trb->DataLen = Packet->InTransferLength;\r
    Trb->Read    = TRUE;\r
  } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r
    Trb->Data    = Packet->OutDataBuffer;\r
    Trb->DataLen = Packet->OutTransferLength;\r
    Trb->Read    = FALSE;\r
  } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r
    Trb->Data    = NULL;\r
    Trb->DataLen = 0;\r
  } else {\r
    goto Error;\r
  }\r
\r
  if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r
    Trb->BlockSize = (UINT16)Trb->DataLen;\r
  }\r
\r
  if (Packet->EmmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK) {\r
    Trb->Mode = EmmcPioMode;\r
  } else {\r
    if (Trb->Read) {\r
      MapOp = EdkiiIoMmuOperationBusMasterWrite;\r
    } else {\r
      MapOp = EdkiiIoMmuOperationBusMasterRead;\r
    }\r
\r
    if (Trb->DataLen != 0) {\r
      MapLength = Trb->DataLen;\r
      Status = IoMmuMap (MapOp, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);\r
\r
      if (EFI_ERROR (Status) || (MapLength != Trb->DataLen)) {\r
        DEBUG ((DEBUG_ERROR, "EmmcPeimCreateTrb: Fail to map data buffer.\n"));\r
        goto Error;\r
      }\r
    }\r
\r
    if (Trb->DataLen == 0) {\r
      Trb->Mode = EmmcNoData;\r
    } else if (Capability.Adma2 != 0) {\r
      Trb->Mode = EmmcAdmaMode;\r
      Status = BuildAdmaDescTable (Trb);\r
      if (EFI_ERROR (Status)) {\r
        goto Error;\r
      }\r
    } else if (Capability.Sdma != 0) {\r
      Trb->Mode = EmmcSdmaMode;\r
    } else {\r
      Trb->Mode = EmmcPioMode;\r
    }\r
  }\r
  return Trb;\r
\r
Error:\r
  EmmcPeimFreeTrb (Trb);\r
  return NULL;\r
}\r
\r
/**\r
  Free the resource used by the TRB.\r
\r
  @param[in] Trb        The pointer to the EMMC_TRB instance.\r
\r
**/\r
VOID\r
EmmcPeimFreeTrb (\r
  IN EMMC_TRB           *Trb\r
  )\r
{\r
  if ((Trb != NULL) && (Trb->DataMap != NULL)) {\r
    IoMmuUnmap (Trb->DataMap);\r
  }\r
\r
  if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {\r
    EmmcPeimFreeMem (Trb->Slot->Private->Pool, Trb->AdmaDesc, Trb->AdmaDescSize);\r
  }\r
\r
  if (Trb != NULL) {\r
    FreePool (Trb);\r
  }\r
  return;\r
}\r
\r
/**\r
  Check if the env is ready for execute specified TRB.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] Trb            The pointer to the EMMC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The env is ready for TRB execution.\r
  @retval EFI_NOT_READY     The env is not ready for TRB execution.\r
  @retval Others            Some erros happen.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimCheckTrbEnv (\r
  IN UINTN                  Bar,\r
  IN EMMC_TRB               *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EMMC_COMMAND_PACKET                 *Packet;\r
  UINT32                              PresentState;\r
\r
  Packet = Trb->Packet;\r
\r
  if ((Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) ||\r
      (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR1b) ||\r
      (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR5b)) {\r
    //\r
    // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r
    // the Present State register to be 0\r
    //\r
    PresentState = BIT0 | BIT1;\r
  } else {\r
    //\r
    // Wait Command Inhibit (CMD) in the Present State register\r
    // to be 0\r
    //\r
    PresentState = BIT0;\r
  }\r
\r
  Status = EmmcPeimHcCheckMmioSet (\r
             Bar + EMMC_HC_PRESENT_STATE,\r
             sizeof (PresentState),\r
             PresentState,\r
             0\r
             );\r
\r
  return Status;\r
}\r
\r
/**\r
  Wait for the env to be ready for execute specified TRB.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] Trb            The pointer to the EMMC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The env is ready for TRB execution.\r
  @retval EFI_TIMEOUT       The env is not ready for TRB execution in time.\r
  @retval Others            Some erros happen.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimWaitTrbEnv (\r
  IN UINTN                  Bar,\r
  IN EMMC_TRB               *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EMMC_COMMAND_PACKET                 *Packet;\r
  UINT64                              Timeout;\r
  BOOLEAN                             InfiniteWait;\r
\r
  //\r
  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
  //\r
  Packet  = Trb->Packet;\r
  Timeout = Packet->Timeout;\r
  if (Timeout == 0) {\r
    InfiniteWait = TRUE;\r
  } else {\r
    InfiniteWait = FALSE;\r
  }\r
\r
  while (InfiniteWait || (Timeout > 0)) {\r
    //\r
    // Check Trb execution result by reading Normal Interrupt Status register.\r
    //\r
    Status = EmmcPeimCheckTrbEnv (Bar, Trb);\r
    if (Status != EFI_NOT_READY) {\r
      return Status;\r
    }\r
    //\r
    // Stall for 1 microsecond.\r
    //\r
    MicroSecondDelay (1);\r
\r
    Timeout--;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Execute the specified TRB.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] Trb            The pointer to the EMMC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The TRB is sent to host controller successfully.\r
  @retval Others            Some erros happen when sending this request to the host controller.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimExecTrb (\r
  IN UINTN                  Bar,\r
  IN EMMC_TRB               *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EMMC_COMMAND_PACKET                 *Packet;\r
  UINT16                              Cmd;\r
  UINT16                              IntStatus;\r
  UINT32                              Argument;\r
  UINT16                              BlkCount;\r
  UINT16                              BlkSize;\r
  UINT16                              TransMode;\r
  UINT8                               HostCtrl1;\r
  UINT32                              SdmaAddr;\r
  UINT64                              AdmaAddr;\r
\r
  Packet = Trb->Packet;\r
  //\r
  // Clear all bits in Error Interrupt Status Register\r
  //\r
  IntStatus = 0xFFFF;\r
  Status    = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Clear all bits in Normal Interrupt Status Register\r
  //\r
  IntStatus = 0xFFFF;\r
  Status    = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set Host Control 1 register DMA Select field\r
  //\r
  if (Trb->Mode == EmmcAdmaMode) {\r
    HostCtrl1 = BIT4;\r
    Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  EmmcPeimHcLedOnOff (Bar, TRUE);\r
\r
  if (Trb->Mode == EmmcSdmaMode) {\r
    if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;\r
    Status   = EmmcPeimHcRwMmio (Bar + EMMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  } else if (Trb->Mode == EmmcAdmaMode) {\r
    AdmaAddr = (UINT64)(UINTN)Trb->AdmaDesc;\r
    Status   = EmmcPeimHcRwMmio (Bar + EMMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  BlkSize = Trb->BlockSize;\r
  if (Trb->Mode == EmmcSdmaMode) {\r
    //\r
    // Set SDMA boundary to be 512K bytes.\r
    //\r
    BlkSize |= 0x7000;\r
  }\r
\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  BlkCount = 0;\r
  if (Trb->Mode != EmmcNoData) {\r
    //\r
    // Calcuate Block Count.\r
    //\r
    BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);\r
  }\r
\r
  Status   = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Argument = Packet->EmmcCmdBlk->CommandArgument;\r
  Status   = EmmcPeimHcRwMmio (Bar + EMMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  TransMode = 0;\r
  if (Trb->Mode != EmmcNoData) {\r
    if (Trb->Mode != EmmcPioMode) {\r
      TransMode |= BIT0;\r
    }\r
    if (Trb->Read) {\r
      TransMode |= BIT4;\r
    }\r
    if (BlkCount > 1) {\r
      TransMode |= BIT5 | BIT1;\r
    }\r
  }\r
\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Cmd = (UINT16)LShiftU64(Packet->EmmcCmdBlk->CommandIndex, 8);\r
  if (Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) {\r
    Cmd |= BIT5;\r
  }\r
  //\r
  // Convert ResponseType to value\r
  //\r
  if (Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeBc) {\r
    switch (Packet->EmmcCmdBlk->ResponseType) {\r
      case EmmcResponceTypeR1:\r
      case EmmcResponceTypeR5:\r
      case EmmcResponceTypeR6:\r
      case EmmcResponceTypeR7:\r
        Cmd |= (BIT1 | BIT3 | BIT4);\r
        break;\r
      case EmmcResponceTypeR2:\r
        Cmd |= (BIT0 | BIT3);\r
       break;\r
      case EmmcResponceTypeR3:\r
      case EmmcResponceTypeR4:\r
        Cmd |= BIT1;\r
        break;\r
      case EmmcResponceTypeR1b:\r
      case EmmcResponceTypeR5b:\r
        Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r
        break;\r
      default:\r
        ASSERT (FALSE);\r
        break;\r
    }\r
  }\r
  //\r
  // Execute cmd\r
  //\r
  Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r
  return Status;\r
}\r
\r
/**\r
  Check the TRB execution result.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] Trb            The pointer to the EMMC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The TRB is executed successfully.\r
  @retval EFI_NOT_READY     The TRB is not completed for execution.\r
  @retval Others            Some erros happen when executing this request.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimCheckTrbResult (\r
  IN UINTN                  Bar,\r
  IN EMMC_TRB               *Trb\r
  )\r
{\r
  EFI_STATUS                          Status;\r
  EMMC_COMMAND_PACKET                 *Packet;\r
  UINT16                              IntStatus;\r
  UINT32                              Response[4];\r
  UINT32                              SdmaAddr;\r
  UINT8                               Index;\r
  UINT8                               SwReset;\r
  UINT32                              PioLength;\r
\r
  SwReset = 0;\r
  Packet  = Trb->Packet;\r
  //\r
  // Check Trb execution result by reading Normal Interrupt Status register.\r
  //\r
  Status = EmmcPeimHcRwMmio (\r
             Bar + EMMC_HC_NOR_INT_STS,\r
             TRUE,\r
             sizeof (IntStatus),\r
             &IntStatus\r
             );\r
  if (EFI_ERROR (Status)) {\r
    goto Done;\r
  }\r
  //\r
  // Check Transfer Complete bit is set or not.\r
  //\r
  if ((IntStatus & BIT1) == BIT1) {\r
    if ((IntStatus & BIT15) == BIT15) {\r
      //\r
      // Read Error Interrupt Status register to check if the error is\r
      // Data Timeout Error.\r
      // If yes, treat it as success as Transfer Complete has higher\r
      // priority than Data Timeout Error.\r
      //\r
      Status = EmmcPeimHcRwMmio (\r
                 Bar + EMMC_HC_ERR_INT_STS,\r
                 TRUE,\r
                 sizeof (IntStatus),\r
                 &IntStatus\r
                 );\r
      if (!EFI_ERROR (Status)) {\r
        if ((IntStatus & BIT4) == BIT4) {\r
          Status = EFI_SUCCESS;\r
        } else {\r
          Status = EFI_DEVICE_ERROR;\r
        }\r
      }\r
    }\r
\r
    goto Done;\r
  }\r
  //\r
  // Check if there is a error happened during cmd execution.\r
  // If yes, then do error recovery procedure to follow SD Host Controller\r
  // Simplified Spec 3.0 section 3.10.1.\r
  //\r
  if ((IntStatus & BIT15) == BIT15) {\r
    Status = EmmcPeimHcRwMmio (\r
               Bar + EMMC_HC_ERR_INT_STS,\r
               TRUE,\r
               sizeof (IntStatus),\r
               &IntStatus\r
               );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
\r
    if ((IntStatus & 0x0F) != 0) {\r
      SwReset |= BIT1;\r
    }\r
    if ((IntStatus & 0xF0) != 0) {\r
      SwReset |= BIT2;\r
    }\r
\r
    Status = EmmcPeimHcRwMmio (\r
               Bar + EMMC_HC_SW_RST,\r
               FALSE,\r
               sizeof (SwReset),\r
               &SwReset\r
               );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
    Status = EmmcPeimHcWaitMmioSet (\r
               Bar + EMMC_HC_SW_RST,\r
               sizeof (SwReset),\r
               0xFF,\r
               0,\r
               EMMC_TIMEOUT\r
               );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
\r
    Status = EFI_DEVICE_ERROR;\r
    goto Done;\r
  }\r
  //\r
  // Check if DMA interrupt is signalled for the SDMA transfer.\r
  //\r
  if ((Trb->Mode == EmmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r
    //\r
    // Clear DMA interrupt bit.\r
    //\r
    IntStatus = BIT3;\r
    Status    = EmmcPeimHcRwMmio (\r
                  Bar + EMMC_HC_NOR_INT_STS,\r
                  FALSE,\r
                  sizeof (IntStatus),\r
                  &IntStatus\r
                  );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
    //\r
    // Update SDMA Address register.\r
    //\r
    SdmaAddr = EMMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, EMMC_SDMA_BOUNDARY);\r
    Status   = EmmcPeimHcRwMmio (\r
                 Bar + EMMC_HC_SDMA_ADDR,\r
                 FALSE,\r
                 sizeof (UINT32),\r
                 &SdmaAddr\r
                 );\r
    if (EFI_ERROR (Status)) {\r
      goto Done;\r
    }\r
    Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;\r
  }\r
\r
  if ((Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeAdtc) &&\r
      (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR1b) &&\r
      (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR5b)) {\r
    if ((IntStatus & BIT0) == BIT0) {\r
      Status = EFI_SUCCESS;\r
      goto Done;\r
    }\r
  }\r
\r
  if (Packet->EmmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK) {\r
    //\r
    // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,\r
    // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.\r
    // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.\r
    //\r
    if ((IntStatus & BIT5) == BIT5) {\r
      //\r
      // Clear Buffer Read Ready interrupt at first.\r
      //\r
      IntStatus = BIT5;\r
      EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
      //\r
      // Read data out from Buffer Port register\r
      //\r
      for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {\r
        EmmcPeimHcRwMmio (Bar + EMMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);\r
      }\r
      Status = EFI_SUCCESS;\r
      goto Done;\r
    }\r
  }\r
\r
  Status = EFI_NOT_READY;\r
Done:\r
  //\r
  // Get response data when the cmd is executed successfully.\r
  //\r
  if (!EFI_ERROR (Status)) {\r
    if (Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeBc) {\r
      for (Index = 0; Index < 4; Index++) {\r
        Status = EmmcPeimHcRwMmio (\r
                   Bar + EMMC_HC_RESPONSE + Index * 4,\r
                   TRUE,\r
                   sizeof (UINT32),\r
                   &Response[Index]\r
                   );\r
        if (EFI_ERROR (Status)) {\r
          EmmcPeimHcLedOnOff (Bar, FALSE);\r
          return Status;\r
        }\r
      }\r
      CopyMem (Packet->EmmcStatusBlk, Response, sizeof (Response));\r
    }\r
  }\r
\r
  if (Status != EFI_NOT_READY) {\r
    EmmcPeimHcLedOnOff (Bar, FALSE);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Wait for the TRB execution result.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
  @param[in] Trb            The pointer to the EMMC_TRB instance.\r
\r
  @retval EFI_SUCCESS       The TRB is executed successfully.\r
  @retval Others            Some erros happen when executing this request.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimWaitTrbResult (\r
  IN UINTN                  Bar,\r
  IN EMMC_TRB               *Trb\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  EMMC_COMMAND_PACKET               *Packet;\r
  UINT64                            Timeout;\r
  BOOLEAN                           InfiniteWait;\r
\r
  Packet = Trb->Packet;\r
  //\r
  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
  //\r
  Timeout = Packet->Timeout;\r
  if (Timeout == 0) {\r
    InfiniteWait = TRUE;\r
  } else {\r
    InfiniteWait = FALSE;\r
  }\r
\r
  while (InfiniteWait || (Timeout > 0)) {\r
    //\r
    // Check Trb execution result by reading Normal Interrupt Status register.\r
    //\r
    Status = EmmcPeimCheckTrbResult (Bar, Trb);\r
    if (Status != EFI_NOT_READY) {\r
      return Status;\r
    }\r
    //\r
    // Stall for 1 microsecond.\r
    //\r
    MicroSecondDelay (1);\r
\r
    Timeout--;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Sends EMMC command to an EMMC card that is attached to the EMMC controller.\r
\r
  If Packet is successfully sent to the EMMC card, then EFI_SUCCESS is returned.\r
\r
  If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.\r
\r
  If Slot is not in a valid range for the EMMC controller, then EFI_INVALID_PARAMETER\r
  is returned.\r
\r
  If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,\r
  EFI_INVALID_PARAMETER is returned.\r
\r
  @param[in]     Slot           The slot number of the Emmc card to send the command to.\r
  @param[in,out] Packet         A pointer to the EMMC command data structure.\r
\r
  @retval EFI_SUCCESS           The EMMC Command Packet was sent by the host.\r
  @retval EFI_DEVICE_ERROR      A device error occurred while attempting to send the SD\r
                                command Packet.\r
  @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.\r
  @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and\r
                                OutDataBuffer are NULL.\r
  @retval EFI_NO_MEDIA          SD Device not present in the Slot.\r
  @retval EFI_UNSUPPORTED       The command described by the EMMC Command Packet is not\r
                                supported by the host controller.\r
  @retval EFI_BAD_BUFFER_SIZE   The InTransferLength or OutTransferLength exceeds the\r
                                limit supported by EMMC card ( i.e. if the number of bytes\r
                                exceed the Last LBA).\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimExecCmd (\r
  IN     EMMC_PEIM_HC_SLOT       *Slot,\r
  IN OUT EMMC_COMMAND_PACKET     *Packet\r
  )\r
{\r
  EFI_STATUS                      Status;\r
  EMMC_TRB                        *Trb;\r
\r
  if (Packet == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((Packet->EmmcCmdBlk == NULL) || (Packet->EmmcStatusBlk == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Trb = EmmcPeimCreateTrb (Slot, Packet);\r
  if (Trb == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  Status = EmmcPeimWaitTrbEnv (Slot->EmmcHcBase, Trb);\r
  if (EFI_ERROR (Status)) {\r
    goto Done;\r
  }\r
\r
  Status = EmmcPeimExecTrb (Slot->EmmcHcBase, Trb);\r
  if (EFI_ERROR (Status)) {\r
    goto Done;\r
  }\r
\r
  Status = EmmcPeimWaitTrbResult (Slot->EmmcHcBase, Trb);\r
  if (EFI_ERROR (Status)) {\r
    goto Done;\r
  }\r
\r
Done:\r
  EmmcPeimFreeTrb (Trb);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command GO_IDLE_STATE (CMD0 with argument of 0x00000000) to the device to\r
  make it go to Idle State.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
\r
  @retval EFI_SUCCESS       The EMMC device is reset correctly.\r
  @retval Others            The device reset fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimReset (\r
  IN EMMC_PEIM_HC_SLOT      *Slot\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeBc;\r
  EmmcCmdBlk.ResponseType = 0;\r
  EmmcCmdBlk.CommandArgument = 0;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SEND_OP_COND to the EMMC device to get the data of the OCR register.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
\r
  @param[in]      Slot      The slot number of the Emmc card to send the command to.\r
  @param[in, out] Argument  On input, the argument of SEND_OP_COND is to send to the device.\r
                            On output, the argument is the value of OCR register.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimGetOcr (\r
  IN     EMMC_PEIM_HC_SLOT      *Slot,\r
  IN OUT UINT32                 *Argument\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeBcr;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR3;\r
  EmmcCmdBlk.CommandArgument = *Argument;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
  if (!EFI_ERROR (Status)) {\r
    //\r
    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r
    //\r
    *Argument = EmmcStatusBlk.Resp0;\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Broadcast command ALL_SEND_CID to the bus to ask all the EMMC devices to send the\r
  data of their CID registers.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimGetAllCid (\r
  IN EMMC_PEIM_HC_SLOT      *Slot\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeBcr;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
  EmmcCmdBlk.CommandArgument = 0;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SET_RELATIVE_ADDR to the EMMC device to assign a Relative device\r
  Address (RCA).\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address to be assigned.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSetRca (\r
  IN EMMC_PEIM_HC_SLOT      *Slot,\r
  IN UINT32                 Rca\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SEND_CSD to the EMMC device to get the data of the CSD register.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in]  Slot          The slot number of the Emmc card to send the command to.\r
  @param[in]  Rca           The relative device address of selected device.\r
  @param[out] Csd           The buffer to store the content of the CSD register.\r
                            Note the caller should ignore the lowest byte of this\r
                            buffer as the content of this byte is meaningless even\r
                            if the operation succeeds.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimGetCsd (\r
  IN     EMMC_PEIM_HC_SLOT              *Slot,\r
  IN     UINT32                         Rca,\r
     OUT EMMC_CSD                       *Csd\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SEND_CSD;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
  EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
  if (!EFI_ERROR (Status)) {\r
    //\r
    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r
    //\r
    CopyMem (((UINT8*)Csd) + 1, &EmmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SELECT_DESELECT_CARD to the EMMC device to select/deselect it.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address of selected device.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSelect (\r
  IN EMMC_PEIM_HC_SLOT      *Slot,\r
  IN UINT32                 Rca\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SEND_EXT_CSD to the EMMC device to get the data of the EXT_CSD register.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in]  Slot          The slot number of the Emmc card to send the command to.\r
  @param[out] ExtCsd        The buffer to store the content of the EXT_CSD register.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimGetExtCsd (\r
  IN     EMMC_PEIM_HC_SLOT              *Slot,\r
     OUT EMMC_EXT_CSD                   *ExtCsd\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAdtc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  EmmcCmdBlk.CommandArgument = 0x00000000;\r
\r
  Packet.InDataBuffer     = ExtCsd;\r
  Packet.InTransferLength = sizeof (EMMC_EXT_CSD);\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
  return Status;\r
}\r
\r
/**\r
  Send command SWITCH to the EMMC device to switch the mode of operation of the\r
  selected Device or modifies the EXT_CSD registers.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Access         The access mode of SWTICH command.\r
  @param[in] Index          The offset of the field to be access.\r
  @param[in] Value          The value to be set to the specified field of EXT_CSD register.\r
  @param[in] CmdSet         The value of CmdSet field of EXT_CSD register.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitch (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT8                              Access,\r
  IN UINT8                              Index,\r
  IN UINT8                              Value,\r
  IN UINT8                              CmdSet\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SWITCH;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR1b;\r
  EmmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SEND_STATUS to the addressed EMMC device to get its status register.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in]  Slot          The slot number of the Emmc card to send the command to.\r
  @param[in]  Rca           The relative device address of addressed device.\r
  @param[out] DevStatus     The returned device status.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSendStatus (\r
  IN     EMMC_PEIM_HC_SLOT              *Slot,\r
  IN     UINT32                         Rca,\r
     OUT UINT32                         *DevStatus\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
  if (!EFI_ERROR (Status)) {\r
    *DevStatus = EmmcStatusBlk.Resp0;\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of\r
  blocks for the following block read/write cmd.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] BlockCount     The number of the logical block to access.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSetBlkCount (\r
  IN EMMC_PEIM_HC_SLOT              *Slot,\r
  IN UINT16                         BlockCount\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout       = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SET_BLOCK_COUNT;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  EmmcCmdBlk.CommandArgument = BlockCount;\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device\r
  to read/write the specified number of blocks.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Lba            The logical block address of starting access.\r
  @param[in] BlockSize      The block size of specified EMMC device partition.\r
  @param[in] Buffer         The pointer to the transfer buffer.\r
  @param[in] BufferSize     The size of transfer buffer.\r
  @param[in] IsRead         Boolean to show the operation direction.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimRwMultiBlocks (\r
  IN EMMC_PEIM_HC_SLOT              *Slot,\r
  IN EFI_LBA                        Lba,\r
  IN UINT32                         BlockSize,\r
  IN VOID                           *Buffer,\r
  IN UINTN                          BufferSize,\r
  IN BOOLEAN                        IsRead\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  //\r
  // Calculate timeout value through the below formula.\r
  // Timeout = (transfer size) / (2MB/s).\r
  // Taking 2MB/s as divisor is because it's nearest to the eMMC lowest\r
  // transfer speed (2.4MB/s).\r
  // Refer to eMMC 5.0 spec section 6.9.1 for details.\r
  //\r
  Packet.Timeout       = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;\r
\r
  if (IsRead) {\r
    Packet.InDataBuffer     = Buffer;\r
    Packet.InTransferLength = (UINT32)BufferSize;\r
\r
    EmmcCmdBlk.CommandIndex = EMMC_READ_MULTIPLE_BLOCK;\r
    EmmcCmdBlk.CommandType  = EmmcCommandTypeAdtc;\r
    EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  } else {\r
    Packet.OutDataBuffer     = Buffer;\r
    Packet.OutTransferLength = (UINT32)BufferSize;\r
\r
    EmmcCmdBlk.CommandIndex = EMMC_WRITE_MULTIPLE_BLOCK;\r
    EmmcCmdBlk.CommandType  = EmmcCommandTypeAdtc;\r
    EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  }\r
\r
  if (Slot->SectorAddressing) {\r
    EmmcCmdBlk.CommandArgument = (UINT32)Lba;\r
  } else {\r
    EmmcCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);\r
  }\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Send command SEND_TUNING_BLOCK to the EMMC device for HS200 optimal sampling point\r
  detection.\r
\r
  It may be sent up to 40 times until the host finishes the tuning procedure.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] BusWidth       The bus width to work.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSendTuningBlk (\r
  IN EMMC_PEIM_HC_SLOT      *Slot,\r
  IN UINT8                  BusWidth\r
  )\r
{\r
  EMMC_COMMAND_BLOCK                    EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                     EmmcStatusBlk;\r
  EMMC_COMMAND_PACKET                   Packet;\r
  EFI_STATUS                            Status;\r
  UINT8                                 TuningBlock[128];\r
\r
  ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
  ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
  ZeroMem (&Packet, sizeof (Packet));\r
\r
  Packet.EmmcCmdBlk    = &EmmcCmdBlk;\r
  Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
  Packet.Timeout        = EMMC_TIMEOUT;\r
\r
  EmmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;\r
  EmmcCmdBlk.CommandType  = EmmcCommandTypeAdtc;\r
  EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
  EmmcCmdBlk.CommandArgument = 0;\r
\r
  Packet.InDataBuffer = TuningBlock;\r
  if (BusWidth == 8) {\r
    Packet.InTransferLength = sizeof (TuningBlock);\r
  } else {\r
    Packet.InTransferLength = 64;\r
  }\r
\r
  Status = EmmcPeimExecCmd (Slot, &Packet);\r
\r
  return Status;\r
}\r
\r
/**\r
  Tunning the clock to get HS200 optimal sampling point.\r
\r
  Command SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the\r
  tuning procedure.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
  Simplified Spec 3.0 section Figure 2-29 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] BusWidth       The bus width to work.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimTuningClkForHs200 (\r
  IN EMMC_PEIM_HC_SLOT      *Slot,\r
  IN UINT8                  BusWidth\r
  )\r
{\r
  EFI_STATUS          Status;\r
  UINT8               HostCtrl2;\r
  UINT8               Retry;\r
\r
  //\r
  // Notify the host that the sampling clock tuning procedure starts.\r
  //\r
  HostCtrl2 = BIT6;\r
  Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.\r
  //\r
  Retry = 0;\r
  do {\r
    Status = EmmcPeimSendTuningBlk (Slot, BusWidth);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    Status = EmmcPeimHcRwMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {\r
      break;\r
    }\r
\r
    if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {\r
      return EFI_SUCCESS;\r
    }\r
  } while (++Retry < 40);\r
\r
  DEBUG ((EFI_D_ERROR, "EmmcPeimTuningClkForHs200: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));\r
  //\r
  // Abort the tuning procedure and reset the tuning circuit.\r
  //\r
  HostCtrl2 = (UINT8)~(BIT6 | BIT7);\r
  Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  return EFI_DEVICE_ERROR;\r
}\r
\r
/**\r
  Switch the bus width to specified width.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.9 and SD Host Controller\r
  Simplified Spec 3.0 section Figure 3-7 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address to be assigned.\r
  @param[in] IsDdr          If TRUE, use dual data rate data simpling method. Otherwise\r
                            use single data rate data simpling method.\r
  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchBusWidth (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT32                             Rca,\r
  IN BOOLEAN                            IsDdr,\r
  IN UINT8                              BusWidth\r
  )\r
{\r
  EFI_STATUS          Status;\r
  UINT8               Access;\r
  UINT8               Index;\r
  UINT8               Value;\r
  UINT8               CmdSet;\r
  UINT32              DevStatus;\r
\r
  //\r
  // Write Byte, the Value field is written into the byte pointed by Index.\r
  //\r
  Access = 0x03;\r
  Index  = OFFSET_OF (EMMC_EXT_CSD, BusWidth);\r
  if (BusWidth == 4) {\r
    Value = 1;\r
  } else if (BusWidth == 8) {\r
    Value = 2;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (IsDdr) {\r
    Value += 4;\r
  }\r
\r
  CmdSet = 0;\r
  Status = EmmcPeimSwitch (Slot, Access, Index, Value, CmdSet);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = EmmcPeimSendStatus (Slot, Rca, &DevStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Check the switch operation is really successful or not.\r
  //\r
  if ((DevStatus & BIT7) != 0) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  Status = EmmcPeimHcSetBusWidth (Slot->EmmcHcBase, BusWidth);\r
\r
  return Status;\r
}\r
\r
/**\r
  Switch the clock frequency to the specified value.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller\r
  Simplified Spec 3.0 section Figure 3-3 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address to be assigned.\r
  @param[in] HsTiming       The value to be written to HS_TIMING field of EXT_CSD register.\r
  @param[in] ClockFreq      The max clock frequency to be set, the unit is MHz.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchClockFreq (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT32                             Rca,\r
  IN UINT8                              HsTiming,\r
  IN UINT32                             ClockFreq\r
  )\r
{\r
  EFI_STATUS          Status;\r
  UINT8               Access;\r
  UINT8               Index;\r
  UINT8               Value;\r
  UINT8               CmdSet;\r
  UINT32              DevStatus;\r
\r
  //\r
  // Write Byte, the Value field is written into the byte pointed by Index.\r
  //\r
  Access = 0x03;\r
  Index  = OFFSET_OF (EMMC_EXT_CSD, HsTiming);\r
  Value  = HsTiming;\r
  CmdSet = 0;\r
\r
  Status = EmmcPeimSwitch (Slot, Access, Index, Value, CmdSet);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = EmmcPeimSendStatus (Slot, Rca, &DevStatus);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Check the switch operation is really successful or not.\r
  //\r
  if ((DevStatus & BIT7) != 0) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
  //\r
  // Convert the clock freq unit from MHz to KHz.\r
  //\r
  Status = EmmcPeimHcClockSupply (Slot->EmmcHcBase, ClockFreq * 1000);\r
\r
  return Status;\r
}\r
\r
/**\r
  Switch to the High Speed timing according to request.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
  Simplified Spec 3.0 section Figure 2-29 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address to be assigned.\r
  @param[in] ClockFreq      The max clock frequency to be set.\r
  @param[in] IsDdr          If TRUE, use dual data rate data simpling method. Otherwise\r
                            use single data rate data simpling method.\r
  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchToHighSpeed (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT32                             Rca,\r
  IN UINT32                             ClockFreq,\r
  IN BOOLEAN                            IsDdr,\r
  IN UINT8                              BusWidth\r
  )\r
{\r
  EFI_STATUS          Status;\r
  UINT8               HsTiming;\r
  UINT8               HostCtrl1;\r
  UINT8               HostCtrl2;\r
\r
  Status = EmmcPeimSwitchBusWidth (Slot, Rca, IsDdr, BusWidth);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set to Hight Speed timing\r
  //\r
  HostCtrl1 = BIT2;\r
  Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  HostCtrl2 = (UINT8)~0x7;\r
  Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if (IsDdr) {\r
    HostCtrl2 = BIT2;\r
  } else if (ClockFreq == 52) {\r
    HostCtrl2 = BIT0;\r
  } else {\r
    HostCtrl2 = 0;\r
  }\r
  Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  HsTiming = 1;\r
  Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
\r
  return Status;\r
}\r
\r
/**\r
  Switch to the HS200 timing according to request.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
  Simplified Spec 3.0 section Figure 2-29 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address to be assigned.\r
  @param[in] ClockFreq      The max clock frequency to be set.\r
  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchToHS200 (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT32                             Rca,\r
  IN UINT32                             ClockFreq,\r
  IN UINT8                              BusWidth\r
  )\r
{\r
  EFI_STATUS          Status;\r
  UINT8               HsTiming;\r
  UINT8               HostCtrl2;\r
  UINT16              ClockCtrl;\r
\r
  if ((BusWidth != 4) && (BusWidth != 8)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = EmmcPeimSwitchBusWidth (Slot, Rca, FALSE, BusWidth);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set to HS200/SDR104 timing\r
  //\r
  //\r
  // Stop bus clock at first\r
  //\r
  Status = EmmcPeimHcStopClock (Slot->EmmcHcBase);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  HostCtrl2 = (UINT8)~0x7;\r
  Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  HostCtrl2 = BIT0 | BIT1;\r
  Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit\r
  //\r
  Status = EmmcPeimHcWaitMmioSet (\r
             Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL,\r
             sizeof (ClockCtrl),\r
             BIT1,\r
             BIT1,\r
             EMMC_TIMEOUT\r
             );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set SD Clock Enable in the Clock Control register to 1\r
  //\r
  ClockCtrl = BIT2;\r
  Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
  HsTiming = 2;\r
  Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = EmmcPeimTuningClkForHs200 (Slot, BusWidth);\r
\r
  return Status;\r
}\r
\r
/**\r
  Switch to the HS400 timing according to request.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
  Simplified Spec 3.0 section Figure 2-29 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address to be assigned.\r
  @param[in] ClockFreq      The max clock frequency to be set.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchToHS400 (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT32                             Rca,\r
  IN UINT32                             ClockFreq\r
  )\r
{\r
  EFI_STATUS          Status;\r
  UINT8               HsTiming;\r
  UINT8               HostCtrl2;\r
\r
  Status = EmmcPeimSwitchToHS200 (Slot, Rca, ClockFreq, 8);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set to Hight Speed timing and set the clock frequency to a value less than 52MHz.\r
  //\r
  HsTiming = 1;\r
  Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, 52);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // HS400 mode must use 8 data lines.\r
  //\r
  Status = EmmcPeimSwitchBusWidth (Slot, Rca, TRUE, 8);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Set to HS400 timing\r
  //\r
  HostCtrl2 = (UINT8)~0x7;\r
  Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  HostCtrl2 = BIT0 | BIT2;\r
  Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  HsTiming = 3;\r
  Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
\r
  return Status;\r
}\r
\r
/**\r
  Switch the high speed timing according to request.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
  Simplified Spec 3.0 section Figure 2-29 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Rca            The relative device address to be assigned.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSetBusMode (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT32                             Rca\r
  )\r
{\r
  EFI_STATUS          Status;\r
  EMMC_HC_SLOT_CAP    Capability;\r
  UINT8               HsTiming;\r
  BOOLEAN             IsDdr;\r
  UINT32              ClockFreq;\r
  UINT8               BusWidth;\r
\r
  Status = EmmcPeimGetCsd (Slot, Rca, &Slot->Csd);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimGetCsd fails with %r\n", Status));\r
    return Status;\r
  }\r
\r
  if ((Slot->Csd.CSizeLow | Slot->Csd.CSizeHigh << 2) == 0xFFF) {\r
    Slot->SectorAddressing = TRUE;\r
  } else {\r
    Slot->SectorAddressing = FALSE;\r
  }\r
\r
  Status = EmmcPeimSelect (Slot, Rca);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimSelect fails with %r\n", Status));\r
    return Status;\r
  }\r
\r
  Status = EmmcPeimHcGetCapability (Slot->EmmcHcBase, &Capability);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimHcGetCapability fails with %r\n", Status));\r
    return Status;\r
  }\r
\r
  ASSERT (Capability.BaseClkFreq != 0);\r
  //\r
  // Check if the Host Controller support 8bits bus width.\r
  //\r
  if (Capability.BusWidth8 != 0) {\r
    BusWidth = 8;\r
  } else {\r
    BusWidth = 4;\r
  }\r
  //\r
  // Get Deivce_Type from EXT_CSD register.\r
  //\r
  Status = EmmcPeimGetExtCsd (Slot, &Slot->ExtCsd);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimGetExtCsd fails with %r\n", Status));\r
    return Status;\r
  }\r
  //\r
  // Calculate supported bus speed/bus width/clock frequency.\r
  //\r
  HsTiming  = 0;\r
  IsDdr     = FALSE;\r
  ClockFreq = 0;\r
  if (((Slot->ExtCsd.DeviceType & (BIT4 | BIT5))  != 0) && (Capability.Sdr104 != 0)) {\r
    HsTiming  = 2;\r
    IsDdr     = FALSE;\r
    ClockFreq = 200;\r
  } else if (((Slot->ExtCsd.DeviceType & (BIT2 | BIT3))  != 0) && (Capability.Ddr50 != 0)) {\r
    HsTiming  = 1;\r
    IsDdr     = TRUE;\r
    ClockFreq = 52;\r
  } else if (((Slot->ExtCsd.DeviceType & BIT1)  != 0) && (Capability.HighSpeed != 0)) {\r
    HsTiming  = 1;\r
    IsDdr     = FALSE;\r
    ClockFreq = 52;\r
  } else if (((Slot->ExtCsd.DeviceType & BIT0)  != 0) && (Capability.HighSpeed != 0)) {\r
    HsTiming  = 1;\r
    IsDdr     = FALSE;\r
    ClockFreq = 26;\r
  }\r
  //\r
  // Check if both of the device and the host controller support HS400 DDR mode.\r
  //\r
  if (((Slot->ExtCsd.DeviceType & (BIT6 | BIT7))  != 0) && (Capability.Hs400 != 0)) {\r
    //\r
    // The host controller supports 8bits bus.\r
    //\r
    ASSERT (BusWidth == 8);\r
    HsTiming  = 3;\r
    IsDdr     = TRUE;\r
    ClockFreq = 200;\r
  }\r
\r
  if ((ClockFreq == 0) || (HsTiming == 0)) {\r
    //\r
    // Continue using default setting.\r
    //\r
    return EFI_SUCCESS;\r
  }\r
\r
  DEBUG ((EFI_D_INFO, "HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));\r
\r
  if (HsTiming == 3) {\r
    //\r
    // Execute HS400 timing switch procedure\r
    //\r
    Status = EmmcPeimSwitchToHS400 (Slot, Rca, ClockFreq);\r
  } else if (HsTiming == 2) {\r
    //\r
    // Execute HS200 timing switch procedure\r
    //\r
    Status = EmmcPeimSwitchToHS200 (Slot, Rca, ClockFreq, BusWidth);\r
  } else {\r
    //\r
    // Execute High Speed timing switch procedure\r
    //\r
    Status = EmmcPeimSwitchToHighSpeed (Slot, Rca, ClockFreq, IsDdr, BusWidth);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Execute EMMC device identification procedure.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
\r
  @retval EFI_SUCCESS       There is a EMMC card.\r
  @retval Others            There is not a EMMC card.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimIdentification (\r
  IN EMMC_PEIM_HC_SLOT           *Slot\r
  )\r
{\r
  EFI_STATUS                     Status;\r
  UINT32                         Ocr;\r
  UINT32                         Rca;\r
  UINTN                          Retry;\r
\r
  Status = EmmcPeimReset (Slot);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimReset fails with %r\n", Status));\r
    return Status;\r
  }\r
\r
  Ocr   = 0;\r
  Retry = 0;\r
  do {\r
    Status = EmmcPeimGetOcr (Slot, &Ocr);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetOcr fails with %r\n", Status));\r
      return Status;\r
    }\r
\r
    if (Retry++ == 100) {\r
      DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetOcr fails too many times\n"));\r
      return EFI_DEVICE_ERROR;\r
    }\r
    MicroSecondDelay (10 * 1000);\r
  } while ((Ocr & BIT31) == 0);\r
\r
  Status = EmmcPeimGetAllCid (Slot);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetAllCid fails with %r\n", Status));\r
    return Status;\r
  }\r
  //\r
  // Don't support multiple devices on the slot, that is\r
  // shared bus slot feature.\r
  //\r
  Rca    = 1;\r
  Status = EmmcPeimSetRca (Slot, Rca);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimSetRca fails with %r\n", Status));\r
    return Status;\r
  }\r
  //\r
  // Enter Data Tranfer Mode.\r
  //\r
  DEBUG ((EFI_D_INFO, "Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));\r
\r
  Status = EmmcPeimSetBusMode (Slot, Rca);\r
\r
  return Status;\r
}\r
\r