[mirror_edk2.git] / MdePkg / Include / IndustryStandard / IoRemappingTable.h

/** @file\r
  ACPI IO Remapping Table (IORT) definitions.\r
\r
  Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>\r
  Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Reference(s):\r
  - IO Remapping Table, Platform Design Document, Revision E.d, Feb 2022\r
    (https://developer.arm.com/documentation/den0049/)\r
  - IO Remapping Table, Platform Design Document, Revision E.e, Sept 2022\r
      (https://developer.arm.com/documentation/den0049/)\r
\r
  @par Glossary:\r
  - Ref  : Reference\r
  - Mem  : Memory\r
  - Desc : Descriptor\r
**/\r
\r
#ifndef __IO_REMAPPING_TABLE_H__\r
#define __IO_REMAPPING_TABLE_H__\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00  0x0\r
#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_04  0x4   // Deprecated\r
#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_05  0x5\r
#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_06  0x6\r
\r
#define EFI_ACPI_IORT_TYPE_ITS_GROUP     0x0\r
#define EFI_ACPI_IORT_TYPE_NAMED_COMP    0x1\r
#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX  0x2\r
#define EFI_ACPI_IORT_TYPE_SMMUv1v2      0x3\r
#define EFI_ACPI_IORT_TYPE_SMMUv3        0x4\r
#define EFI_ACPI_IORT_TYPE_PMCG          0x5\r
#define EFI_ACPI_IORT_TYPE_RMR           0x6\r
\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA  BIT0\r
\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR   BIT0\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA   BIT1\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA   BIT2\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO  BIT3\r
\r
#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM   BIT0\r
#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS  BIT1\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1             0x0\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2             0x1\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400         0x2\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500         0x3\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401         0x4\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2  0x5\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM       BIT0\r
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK  BIT1\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL  0x0\r
#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE   0x1\r
\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE    BIT0\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE     BIT1\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN  BIT3\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_DEVICEID_VALID    BIT4\r
\r
#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC           0x0\r
#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X  0x1\r
#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX     0x2\r
\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED  0x0\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED    BIT0\r
\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_UNSUPPORTED  0x0\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_SUPPORTED    BIT1\r
\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_UNSUPPORTED  0x0\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_SUPPORTED    BIT2\r
\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_UNSUPPORTED  0x0\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_SUPPORTED    BIT1\r
\r
#define EFI_ACPI_IORT_RMR_REMAP_NOT_PERMITTED  0x0\r
#define EFI_ACPI_IORT_RMR_REMAP_PERMITTED      BIT0\r
\r
#define EFI_ACPI_IORT_RMR_ACCESS_REQ_NOT_PRIVILEGED  0x0\r
#define EFI_ACPI_IORT_RMR_ACCESS_REQ_PRIVILEGED      BIT1\r
\r
#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRNE             0x0\r
#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRE              0x1\r
#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGRE               0x2\r
#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_GRE                0x3\r
#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_NC_OUT_NC      0x4\r
#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_WB_OUT_WB_ISH  0x5\r
\r
#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE  BIT0\r
\r
#define EFI_ACPI_IORT_RMR_NODE_REVISION_02  0x2    // Deprecated\r
\r
#pragma pack(1)\r
\r
///\r
/// Table header\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         NumNodes;\r
  UINT32                         NodeOffset;\r
  UINT32                         Reserved;\r
} EFI_ACPI_6_0_IO_REMAPPING_TABLE;\r
\r
///\r
/// Definition for ID mapping table shared by all node types\r
///\r
typedef struct {\r
  UINT32    InputBase;\r
  UINT32    NumIds;\r
  UINT32    OutputBase;\r
  UINT32    OutputReference;\r
  UINT32    Flags;\r
} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;\r
\r
///\r
/// Node header definition shared by all node types\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT16    Length;\r
  UINT8     Revision;\r
  UINT32    Identifier;\r
  UINT32    NumIdMappings;\r
  UINT32    IdReference;\r
} EFI_ACPI_6_0_IO_REMAPPING_NODE;\r
\r
///\r
/// Node type 0: ITS node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE    Node;\r
\r
  UINT32                            NumItsIdentifiers;\r
  // UINT32                                  ItsIdentifiers[NumItsIdentifiers];\r
} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;\r
\r
///\r
/// Node type 1: root complex node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE    Node;\r
\r
  UINT32                            CacheCoherent;\r
  UINT8                             AllocationHints;\r
  UINT16                            Reserved;\r
  UINT8                             MemoryAccessFlags;\r
\r
  UINT32                            AtsAttribute;\r
  UINT32                            PciSegmentNumber;\r
  UINT8                             MemoryAddressSize;\r
  UINT16                            PasidCapabilities;\r
  UINT8                             Reserved1[1];\r
  UINT32                            Flags;\r
} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r
\r
///\r
/// Node type 2: named component node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE    Node;\r
\r
  UINT32                            Flags;\r
  UINT32                            CacheCoherent;\r
  UINT8                             AllocationHints;\r
  UINT16                            Reserved;\r
  UINT8                             MemoryAccessFlags;\r
  UINT8                             AddressSizeLimit;\r
  // UINT8                                   ObjectName[];\r
} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;\r
\r
///\r
/// Node type 3: SMMUv1 or SMMUv2 node\r
///\r
typedef struct {\r
  UINT32    Interrupt;\r
  UINT32    InterruptFlags;\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;\r
\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE    Node;\r
\r
  UINT64                            Base;\r
  UINT64                            Span;\r
  UINT32                            Model;\r
  UINT32                            Flags;\r
  UINT32                            GlobalInterruptArrayRef;\r
  UINT32                            NumContextInterrupts;\r
  UINT32                            ContextInterruptArrayRef;\r
  UINT32                            NumPmuInterrupts;\r
  UINT32                            PmuInterruptArrayRef;\r
\r
  UINT32                            SMMU_NSgIrpt;\r
  UINT32                            SMMU_NSgIrptFlags;\r
  UINT32                            SMMU_NSgCfgIrpt;\r
  UINT32                            SMMU_NSgCfgIrptFlags;\r
\r
  // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  ContextInterrupt[NumContextInterrupts];\r
  // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  PmuInterrupt[NumPmuInterrupts];\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r
\r
///\r
/// Node type 4: SMMUv3 node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE    Node;\r
\r
  UINT64                            Base;\r
  UINT32                            Flags;\r
  UINT32                            Reserved;\r
  UINT64                            VatosAddress;\r
  UINT32                            Model;\r
  UINT32                            Event;\r
  UINT32                            Pri;\r
  UINT32                            Gerr;\r
  UINT32                            Sync;\r
  UINT32                            ProximityDomain;\r
  UINT32                            DeviceIdMappingIndex;\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r
\r
///\r
/// Node type 5: PMCG node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE    Node;\r
\r
  UINT64                            Base;\r
  UINT32                            OverflowInterruptGsiv;\r
  UINT32                            NodeReference;\r
  UINT64                            Page1Base;\r
  // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE      OverflowInterruptMsiMapping[1];\r
} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r
\r
///\r
/// Memory Range Descriptor.\r
///\r
typedef struct {\r
  /// Base address of Reserved Memory Range,\r
  /// aligned to a page size of 64K.\r
  UINT64    Base;\r
\r
  /// Length of the Reserved Memory range.\r
  /// Must be a multiple of the page size of 64K.\r
  UINT64    Length;\r
\r
  /// Reserved, must be zero.\r
  UINT32    Reserved;\r
} EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC;\r
\r
///\r
/// Node type 6: Reserved Memory Range (RMR) node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE    Node;\r
\r
  /// RMR flags\r
  UINT32                            Flags;\r
\r
  /// Memory range descriptor count.\r
  UINT32                            NumMemRangeDesc;\r
\r
  /// Offset of the memory range descriptor array.\r
  UINT32                            MemRangeDescRef;\r
  // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE         IdMapping[1];\r
  // EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC   MemRangeDesc[1];\r
} EFI_ACPI_6_0_IO_REMAPPING_RMR_NODE;\r
\r
#pragma pack()\r
\r
#endif\r
Commit	Line	Data
75ce7ef7	1	/** @file\r
4c55f639	2	ACPI IO Remapping Table (IORT) definitions.\r
75ce7ef7 AB	3	\r
75ce7ef7 AB	4	Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>\r
4c55f639	5	Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.<BR>\r
75ce7ef7	6	\r
9344f092	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
4c55f639 SM	8	\r
	9	@par Reference(s):\r
	10	- IO Remapping Table, Platform Design Document, Revision E.d, Feb 2022\r
	11	(https://developer.arm.com/documentation/den0049/)\r
5db84c85 SK	12	- IO Remapping Table, Platform Design Document, Revision E.e, Sept 2022\r
5db84c85 SK	13	(https://developer.arm.com/documentation/den0049/)\r
4c55f639 SM	14	\r
	15	@par Glossary:\r
	16	- Ref : Reference\r
	17	- Mem : Memory\r
	18	- Desc : Descriptor\r
75ce7ef7 AB	19	**/\r
	20	\r
	21	#ifndef __IO_REMAPPING_TABLE_H__\r
	22	#define __IO_REMAPPING_TABLE_H__\r
	23	\r
	24	#include <IndustryStandard/Acpi.h>\r
	25	\r
4c55f639 SM	26	#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00 0x0\r
	27	#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_04 0x4 // Deprecated\r
	28	#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_05 0x5\r
5db84c85	29	#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_06 0x6\r
75ce7ef7	30	\r
2f88bd3a MK	31	#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0\r
	32	#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1\r
	33	#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2\r
	34	#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3\r
	35	#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4\r
	36	#define EFI_ACPI_IORT_TYPE_PMCG 0x5\r
4c55f639	37	#define EFI_ACPI_IORT_TYPE_RMR 0x6\r
75ce7ef7	38	\r
2f88bd3a	39	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0\r
75ce7ef7	40	\r
2f88bd3a MK	41	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0\r
	42	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1\r
	43	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2\r
	44	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3\r
75ce7ef7	45	\r
2f88bd3a MK	46	#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0\r
2f88bd3a MK	47	#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1\r
75ce7ef7 AB	48	\r
	49	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0\r
	50	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1\r
	51	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2\r
	52	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3\r
157fb7bf AB	53	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4\r
157fb7bf AB	54	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5\r
75ce7ef7	55	\r
2f88bd3a MK	56	#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0\r
2f88bd3a MK	57	#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1\r
75ce7ef7	58	\r
2f88bd3a MK	59	#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0\r
2f88bd3a MK	60	#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1\r
75ce7ef7 AB	61	\r
	62	#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0\r
	63	#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1\r
27e98391	64	#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3\r
5db84c85	65	#define EFI_ACPI_IORT_SMMUv3_FLAG_DEVICEID_VALID BIT4\r
27e98391	66	\r
2f88bd3a MK	67	#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0\r
	68	#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1\r
	69	#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2\r
75ce7ef7 AB	70	\r
75ce7ef7 AB	71	#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0\r
4c55f639 SM	72	#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED BIT0\r
	73	\r
	74	#define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_UNSUPPORTED 0x0\r
	75	#define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_SUPPORTED BIT1\r
	76	\r
	77	#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_UNSUPPORTED 0x0\r
	78	#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_SUPPORTED BIT2\r
	79	\r
	80	#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_UNSUPPORTED 0x0\r
	81	#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_SUPPORTED BIT1\r
	82	\r
	83	#define EFI_ACPI_IORT_RMR_REMAP_NOT_PERMITTED 0x0\r
	84	#define EFI_ACPI_IORT_RMR_REMAP_PERMITTED BIT0\r
	85	\r
	86	#define EFI_ACPI_IORT_RMR_ACCESS_REQ_NOT_PRIVILEGED 0x0\r
	87	#define EFI_ACPI_IORT_RMR_ACCESS_REQ_PRIVILEGED BIT1\r
	88	\r
	89	#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRNE 0x0\r
	90	#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRE 0x1\r
	91	#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGRE 0x2\r
	92	#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_GRE 0x3\r
	93	#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_NC_OUT_NC 0x4\r
	94	#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_WB_OUT_WB_ISH 0x5\r
75ce7ef7	95	\r
2f88bd3a	96	#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0\r
75ce7ef7	97	\r
4c55f639 SM	98	#define EFI_ACPI_IORT_RMR_NODE_REVISION_02 0x2 // Deprecated\r
4c55f639 SM	99	\r
75ce7ef7 AB	100	#pragma pack(1)\r
	101	\r
	102	///\r
	103	/// Table header\r
	104	///\r
	105	typedef struct {\r
2f88bd3a MK	106	EFI_ACPI_DESCRIPTION_HEADER Header;\r
	107	UINT32 NumNodes;\r
	108	UINT32 NodeOffset;\r
	109	UINT32 Reserved;\r
75ce7ef7 AB	110	} EFI_ACPI_6_0_IO_REMAPPING_TABLE;\r
	111	\r
	112	///\r
	113	/// Definition for ID mapping table shared by all node types\r
	114	///\r
	115	typedef struct {\r
2f88bd3a MK	116	UINT32 InputBase;\r
	117	UINT32 NumIds;\r
	118	UINT32 OutputBase;\r
	119	UINT32 OutputReference;\r
	120	UINT32 Flags;\r
75ce7ef7 AB	121	} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;\r
	122	\r
	123	///\r
	124	/// Node header definition shared by all node types\r
	125	///\r
	126	typedef struct {\r
2f88bd3a MK	127	UINT8 Type;\r
	128	UINT16 Length;\r
	129	UINT8 Revision;\r
4c55f639	130	UINT32 Identifier;\r
2f88bd3a MK	131	UINT32 NumIdMappings;\r
2f88bd3a MK	132	UINT32 IdReference;\r
75ce7ef7 AB	133	} EFI_ACPI_6_0_IO_REMAPPING_NODE;\r
	134	\r
	135	///\r
	136	/// Node type 0: ITS node\r
	137	///\r
	138	typedef struct {\r
2f88bd3a	139	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
75ce7ef7	140	\r
2f88bd3a MK	141	UINT32 NumItsIdentifiers;\r
2f88bd3a MK	142	// UINT32 ItsIdentifiers[NumItsIdentifiers];\r
75ce7ef7 AB	143	} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;\r
	144	\r
	145	///\r
	146	/// Node type 1: root complex node\r
	147	///\r
	148	typedef struct {\r
2f88bd3a	149	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
75ce7ef7	150	\r
2f88bd3a MK	151	UINT32 CacheCoherent;\r
	152	UINT8 AllocationHints;\r
	153	UINT16 Reserved;\r
	154	UINT8 MemoryAccessFlags;\r
75ce7ef7	155	\r
2f88bd3a MK	156	UINT32 AtsAttribute;\r
	157	UINT32 PciSegmentNumber;\r
	158	UINT8 MemoryAddressSize;\r
4c55f639 SM	159	UINT16 PasidCapabilities;\r
	160	UINT8 Reserved1[1];\r
	161	UINT32 Flags;\r
75ce7ef7 AB	162	} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r
	163	\r
	164	///\r
	165	/// Node type 2: named component node\r
	166	///\r
	167	typedef struct {\r
2f88bd3a MK	168	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
	169	\r
	170	UINT32 Flags;\r
	171	UINT32 CacheCoherent;\r
	172	UINT8 AllocationHints;\r
	173	UINT16 Reserved;\r
	174	UINT8 MemoryAccessFlags;\r
	175	UINT8 AddressSizeLimit;\r
	176	// UINT8 ObjectName[];\r
75ce7ef7 AB	177	} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;\r
	178	\r
	179	///\r
	180	/// Node type 3: SMMUv1 or SMMUv2 node\r
	181	///\r
	182	typedef struct {\r
2f88bd3a MK	183	UINT32 Interrupt;\r
2f88bd3a MK	184	UINT32 InterruptFlags;\r
75ce7ef7 AB	185	} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;\r
	186	\r
	187	typedef struct {\r
2f88bd3a MK	188	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
	189	\r
	190	UINT64 Base;\r
	191	UINT64 Span;\r
	192	UINT32 Model;\r
	193	UINT32 Flags;\r
	194	UINT32 GlobalInterruptArrayRef;\r
	195	UINT32 NumContextInterrupts;\r
	196	UINT32 ContextInterruptArrayRef;\r
	197	UINT32 NumPmuInterrupts;\r
	198	UINT32 PmuInterruptArrayRef;\r
	199	\r
	200	UINT32 SMMU_NSgIrpt;\r
	201	UINT32 SMMU_NSgIrptFlags;\r
	202	UINT32 SMMU_NSgCfgIrpt;\r
	203	UINT32 SMMU_NSgCfgIrptFlags;\r
	204	\r
	205	// EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];\r
	206	// EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];\r
75ce7ef7 AB	207	} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r
	208	\r
	209	///\r
27e98391	210	/// Node type 4: SMMUv3 node\r
75ce7ef7 AB	211	///\r
75ce7ef7 AB	212	typedef struct {\r
2f88bd3a MK	213	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
	214	\r
	215	UINT64 Base;\r
	216	UINT32 Flags;\r
	217	UINT32 Reserved;\r
	218	UINT64 VatosAddress;\r
	219	UINT32 Model;\r
	220	UINT32 Event;\r
	221	UINT32 Pri;\r
	222	UINT32 Gerr;\r
	223	UINT32 Sync;\r
	224	UINT32 ProximityDomain;\r
	225	UINT32 DeviceIdMappingIndex;\r
75ce7ef7 AB	226	} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r
75ce7ef7 AB	227	\r
157fb7bf AB	228	///\r
	229	/// Node type 5: PMCG node\r
	230	///\r
	231	typedef struct {\r
2f88bd3a	232	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
157fb7bf	233	\r
2f88bd3a MK	234	UINT64 Base;\r
	235	UINT32 OverflowInterruptGsiv;\r
	236	UINT32 NodeReference;\r
	237	UINT64 Page1Base;\r
	238	// EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];\r
157fb7bf AB	239	} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r
157fb7bf AB	240	\r
4c55f639 SM	241	///\r
	242	/// Memory Range Descriptor.\r
	243	///\r
	244	typedef struct {\r
	245	/// Base address of Reserved Memory Range,\r
	246	/// aligned to a page size of 64K.\r
	247	UINT64 Base;\r
	248	\r
	249	/// Length of the Reserved Memory range.\r
	250	/// Must be a multiple of the page size of 64K.\r
	251	UINT64 Length;\r
	252	\r
	253	/// Reserved, must be zero.\r
	254	UINT32 Reserved;\r
	255	} EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC;\r
	256	\r
	257	///\r
	258	/// Node type 6: Reserved Memory Range (RMR) node\r
	259	///\r
	260	typedef struct {\r
	261	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
	262	\r
	263	/// RMR flags\r
	264	UINT32 Flags;\r
	265	\r
	266	/// Memory range descriptor count.\r
	267	UINT32 NumMemRangeDesc;\r
	268	\r
	269	/// Offset of the memory range descriptor array.\r
	270	UINT32 MemRangeDescRef;\r
	271	// EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE IdMapping[1];\r
	272	// EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC MemRangeDesc[1];\r
	273	} EFI_ACPI_6_0_IO_REMAPPING_RMR_NODE;\r
	274	\r
75ce7ef7 AB	275	#pragma pack()\r
	276	\r
	277	#endif\r