[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Nvme.h

/** @file\r
  Definitions based on NVMe spec. version 1.1.\r
\r
  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
  Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  NVMe Specification 1.1\r
  NVMe Specification 1.4\r
  NVMe Specification 2.0\r
\r
**/\r
\r
#ifndef __NVM_E_H__\r
#define __NVM_E_H__\r
\r
#pragma pack(1)\r
\r
//\r
// controller register offsets\r
//\r
#define NVME_CAP_OFFSET     0x0000        // Controller Capabilities\r
#define NVME_VER_OFFSET     0x0008        // Version\r
#define NVME_INTMS_OFFSET   0x000c        // Interrupt Mask Set\r
#define NVME_INTMC_OFFSET   0x0010        // Interrupt Mask Clear\r
#define NVME_CC_OFFSET      0x0014        // Controller Configuration\r
#define NVME_CSTS_OFFSET    0x001c        // Controller Status\r
#define NVME_NSSR_OFFSET    0x0020        // NVM Subsystem Reset\r
#define NVME_AQA_OFFSET     0x0024        // Admin Queue Attributes\r
#define NVME_ASQ_OFFSET     0x0028        // Admin Submission Queue Base Address\r
#define NVME_ACQ_OFFSET     0x0030        // Admin Completion Queue Base Address\r
#define NVME_BPINFO_OFFSET  0x0040        // Boot Partition Information\r
#define NVME_BPRSEL_OFFSET  0x0044        // Boot Partition Read Select\r
#define NVME_BPMBL_OFFSET   0x0048        // Boot Partition Memory Buffer Location\r
#define NVME_SQ0_OFFSET     0x1000        // Submission Queue 0 (admin) Tail Doorbell\r
#define NVME_CQ0_OFFSET     0x1004        // Completion Queue 0 (admin) Head Doorbell\r
\r
//\r
// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
// Get the doorbell stride bit shift value from the controller capabilities.\r
//\r
#define NVME_SQTDBL_OFFSET(QID, DSTRD)  0x1000 + ((2 * (QID)) * (4 << (DSTRD)))         // Submission Queue y (NVM) Tail Doorbell\r
#define NVME_CQHDBL_OFFSET(QID, DSTRD)  0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD)))   // Completion Queue y (NVM) Head Doorbell\r
\r
#pragma pack(1)\r
\r
//\r
// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
//\r
typedef struct {\r
  UINT16    Mqes;       // Maximum Queue Entries Supported\r
  UINT8     Cqr    : 1; // Contiguous Queues Required\r
  UINT8     Ams    : 2; // Arbitration Mechanism Supported\r
  UINT8     Rsvd1  : 5;\r
  UINT8     To;     // Timeout\r
  UINT16    Dstrd  : 4;\r
  UINT16    Nssrs  : 1; // NVM Subsystem Reset Supported NSSRS\r
  UINT16    Css    : 8; // Command Sets Supported - Bit 37\r
  UINT16    Bps    : 1; // Boot Partition Support - Bit 45 in NVMe1.4\r
  UINT16    Rsvd3  : 2;\r
  UINT8     Mpsmin : 4;\r
  UINT8     Mpsmax : 4;\r
  UINT8     Pmrs   : 1;\r
  UINT8     Cmbs   : 1;\r
  UINT8     Rsvd4  : 6;\r
} NVME_CAP;\r
\r
//\r
// 3.1.2 Offset 08h: VS - Version\r
//\r
typedef struct {\r
  UINT16    Mnr;    // Minor version number\r
  UINT16    Mjr;    // Major version number\r
} NVME_VER;\r
\r
//\r
// 3.1.5 Offset 14h: CC - Controller Configuration\r
//\r
typedef struct {\r
  UINT16    En     : 1; // Enable\r
  UINT16    Rsvd1  : 3;\r
  UINT16    Css    : 3; // I/O Command Set Selected\r
  UINT16    Mps    : 4; // Memory Page Size\r
  UINT16    Ams    : 3; // Arbitration Mechanism Selected\r
  UINT16    Shn    : 2; // Shutdown Notification\r
  UINT8     Iosqes : 4; // I/O Submission Queue Entry Size\r
  UINT8     Iocqes : 4; // I/O Completion Queue Entry Size\r
  UINT8     Rsvd2;\r
} NVME_CC;\r
#define NVME_CC_SHN_NORMAL_SHUTDOWN  1\r
#define NVME_CC_SHN_ABRUPT_SHUTDOWN  2\r
\r
//\r
// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
//\r
typedef struct {\r
  UINT32    Rdy   : 1; // Ready\r
  UINT32    Cfs   : 1; // Controller Fatal Status\r
  UINT32    Shst  : 2; // Shutdown Status\r
  UINT32    Nssro : 1; // NVM Subsystem Reset Occurred\r
  UINT32    Rsvd1 : 27;\r
} NVME_CSTS;\r
#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING  1\r
#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED  2\r
//\r
// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
//\r
typedef struct {\r
  UINT16    Asqs  : 12; // Submission Queue Size\r
  UINT16    Rsvd1 : 4;\r
  UINT16    Acqs  : 12; // Completion Queue Size\r
  UINT16    Rsvd2 : 4;\r
} NVME_AQA;\r
\r
//\r
// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
//\r
#define NVME_ASQ  UINT64\r
//\r
// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
//\r
#define NVME_ACQ  UINT64\r
\r
//\r
// 3.1.13 Offset 40h: BPINFO - Boot Partition Information\r
//\r
typedef struct {\r
  UINT32    Bpsz  : 15; // Boot Partition Size\r
  UINT32    Rsvd1 : 9;\r
  UINT32    Brs   : 2;  // Boot Read Status\r
  UINT32    Rsvd2 : 5;\r
  UINT32    Abpid : 1;  // Active Boot Partition ID\r
} NVME_BPINFO;\r
\r
//\r
// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select\r
//\r
typedef struct {\r
  UINT32    Bprsz : 10; // Boot Partition Read Size\r
  UINT32    Bprof : 20; // Boot Partition Read Offset\r
  UINT32    Rsvd1 : 1;\r
  UINT32    Bpid  : 1;  // Boot Partition Identifier\r
} NVME_BPRSEL;\r
\r
//\r
// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)\r
//\r
typedef struct {\r
  UINT64    Rsvd1 : 12;\r
  UINT64    Bmbba : 52; // Boot Partition Memory Buffer Base Address\r
} NVME_BPMBL;\r
\r
//\r
// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
//\r
typedef struct {\r
  UINT16    Sqt;\r
  UINT16    Rsvd1;\r
} NVME_SQTDBL;\r
\r
//\r
// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
//\r
typedef struct {\r
  UINT16    Cqh;\r
  UINT16    Rsvd1;\r
} NVME_CQHDBL;\r
\r
//\r
// NVM command set structures\r
//\r
// Read Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10, 11\r
  //\r
  UINT64    Slba;             /* Starting Sector Address */\r
  //\r
  // CDW 12\r
  //\r
  UINT16    Nlb;              /* Number of Sectors */\r
  UINT16    Rsvd1  : 10;\r
  UINT16    Prinfo : 4;       /* Protection Info Check */\r
  UINT16    Fua    : 1;       /* Force Unit Access */\r
  UINT16    Lr     : 1;       /* Limited Retry */\r
  //\r
  // CDW 13\r
  //\r
  UINT32    Af     : 4;       /* Access Frequency */\r
  UINT32    Al     : 2;       /* Access Latency */\r
  UINT32    Sr     : 1;       /* Sequential Request */\r
  UINT32    In     : 1;       /* Incompressible */\r
  UINT32    Rsvd2  : 24;\r
  //\r
  // CDW 14\r
  //\r
  UINT32    Eilbrt;           /* Expected Initial Logical Block Reference Tag */\r
  //\r
  // CDW 15\r
  //\r
  UINT16    Elbat;            /* Expected Logical Block Application Tag */\r
  UINT16    Elbatm;           /* Expected Logical Block Application Tag Mask */\r
} NVME_READ;\r
\r
//\r
// Write Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10, 11\r
  //\r
  UINT64    Slba;             /* Starting Sector Address */\r
  //\r
  // CDW 12\r
  //\r
  UINT16    Nlb;              /* Number of Sectors */\r
  UINT16    Rsvd1  : 10;\r
  UINT16    Prinfo : 4;       /* Protection Info Check */\r
  UINT16    Fua    : 1;       /* Force Unit Access */\r
  UINT16    Lr     : 1;       /* Limited Retry */\r
  //\r
  // CDW 13\r
  //\r
  UINT32    Af     : 4;       /* Access Frequency */\r
  UINT32    Al     : 2;       /* Access Latency */\r
  UINT32    Sr     : 1;       /* Sequential Request */\r
  UINT32    In     : 1;       /* Incompressible */\r
  UINT32    Rsvd2  : 24;\r
  //\r
  // CDW 14\r
  //\r
  UINT32    Ilbrt;            /* Initial Logical Block Reference Tag */\r
  //\r
  // CDW 15\r
  //\r
  UINT16    Lbat;             /* Logical Block Application Tag */\r
  UINT16    Lbatm;            /* Logical Block Application Tag Mask */\r
} NVME_WRITE;\r
\r
//\r
// Flush\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Flush;            /* Flush */\r
} NVME_FLUSH;\r
\r
//\r
// Write Uncorrectable command\r
//\r
typedef struct {\r
  //\r
  // CDW 10, 11\r
  //\r
  UINT64    Slba;             /* Starting LBA */\r
  //\r
  // CDW 12\r
  //\r
  UINT32    Nlb   : 16;       /* Number of  Logical Blocks */\r
  UINT32    Rsvd1 : 16;\r
} NVME_WRITE_UNCORRECTABLE;\r
\r
//\r
// Write Zeroes command\r
//\r
typedef struct {\r
  //\r
  // CDW 10, 11\r
  //\r
  UINT64    Slba;             /* Starting LBA */\r
  //\r
  // CDW 12\r
  //\r
  UINT16    Nlb;              /* Number of Logical Blocks */\r
  UINT16    Rsvd1  : 10;\r
  UINT16    Prinfo : 4;       /* Protection Info Check */\r
  UINT16    Fua    : 1;       /* Force Unit Access */\r
  UINT16    Lr     : 1;       /* Limited Retry */\r
  //\r
  // CDW 13\r
  //\r
  UINT32    Rsvd2;\r
  //\r
  // CDW 14\r
  //\r
  UINT32    Ilbrt;            /* Initial Logical Block Reference Tag */\r
  //\r
  // CDW 15\r
  //\r
  UINT16    Lbat;             /* Logical Block Application Tag */\r
  UINT16    Lbatm;            /* Logical Block Application Tag Mask */\r
} NVME_WRITE_ZEROES;\r
\r
//\r
// Compare command\r
//\r
typedef struct {\r
  //\r
  // CDW 10, 11\r
  //\r
  UINT64    Slba;             /* Starting LBA */\r
  //\r
  // CDW 12\r
  //\r
  UINT16    Nlb;              /* Number of Logical Blocks */\r
  UINT16    Rsvd1  : 10;\r
  UINT16    Prinfo : 4;       /* Protection Info Check */\r
  UINT16    Fua    : 1;       /* Force Unit Access */\r
  UINT16    Lr     : 1;       /* Limited Retry */\r
  //\r
  // CDW 13\r
  //\r
  UINT32    Rsvd2;\r
  //\r
  // CDW 14\r
  //\r
  UINT32    Eilbrt;           /* Expected Initial Logical Block Reference Tag */\r
  //\r
  // CDW 15\r
  //\r
  UINT16    Elbat;            /* Expected Logical Block Application Tag */\r
  UINT16    Elbatm;           /* Expected Logical Block Application Tag Mask */\r
} NVME_COMPARE;\r
\r
typedef union {\r
  NVME_READ                   Read;\r
  NVME_WRITE                  Write;\r
  NVME_FLUSH                  Flush;\r
  NVME_WRITE_UNCORRECTABLE    WriteUncorrectable;\r
  NVME_WRITE_ZEROES           WriteZeros;\r
  NVME_COMPARE                Compare;\r
} NVME_CMD;\r
\r
typedef struct {\r
  UINT16    Mp;             /* Maximum Power */\r
  UINT8     Rsvd1;          /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT8     Mps   : 1;      /* Max Power Scale */\r
  UINT8     Nops  : 1;      /* Non-Operational State */\r
  UINT8     Rsvd2 : 6;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT32    Enlat;          /* Entry Latency */\r
  UINT32    Exlat;          /* Exit Latency */\r
  UINT8     Rrt   : 5;      /* Relative Read Throughput */\r
  UINT8     Rsvd3 : 3;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT8     Rrl   : 5;      /* Relative Read Latency */\r
  UINT8     Rsvd4 : 3;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT8     Rwt   : 5;      /* Relative Write Throughput */\r
  UINT8     Rsvd5 : 3;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT8     Rwl   : 5;      /* Relative Write Latency */\r
  UINT8     Rsvd6 : 3;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT8     Rsvd7[16];      /* Reserved as of Nvm Express 1.1 Spec */\r
} NVME_PSDESCRIPTOR;\r
\r
//\r
//  Identify Controller Data\r
//\r
typedef struct {\r
  //\r
  // Controller Capabilities and Features 0-255\r
  //\r
  UINT16               Vid;    /* PCI Vendor ID */\r
  UINT16               Ssvid;  /* PCI sub-system vendor ID */\r
  UINT8                Sn[20]; /* Product serial number */\r
\r
  UINT8                Mn[40];      /* Product model number */\r
  UINT8                Fr[8];       /* Firmware Revision */\r
  UINT8                Rab;         /* Recommended Arbitration Burst */\r
  UINT8                Ieee_oui[3]; /* Organization Unique Identifier */\r
  UINT8                Cmic;        /* Multi-interface Capabilities */\r
  UINT8                Mdts;        /* Maximum Data Transfer Size */\r
  UINT8                Cntlid[2];   /* Controller ID */\r
  UINT8                Rsvd1[176];  /* Reserved as of Nvm Express 1.1 Spec */\r
  //\r
  // Admin Command Set Attributes\r
  //\r
  UINT16               Oacs;  /* Optional Admin Command Support */\r
  #define NAMESPACE_MANAGEMENT_SUPPORTED   BIT3\r
  #define FW_DOWNLOAD_ACTIVATE_SUPPORTED   BIT2\r
  #define FORMAT_NVM_SUPPORTED             BIT1\r
  #define SECURITY_SEND_RECEIVE_SUPPORTED  BIT0\r
  UINT8                Acl;   /* Abort Command Limit */\r
  UINT8                Aerl;  /* Async Event Request Limit */\r
  UINT8                Frmw;  /* Firmware updates */\r
  UINT8                Lpa;   /* Log Page Attributes */\r
  UINT8                Elpe;  /* Error Log Page Entries */\r
  UINT8                Npss;  /* Number of Power States Support */\r
  UINT8                Avscc; /* Admin Vendor Specific Command Configuration */\r
  UINT8                Apsta; /* Autonomous Power State Transition Attributes */\r
  //\r
  // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec\r
  //\r
  UINT16               Wctemp;      /* Warning Composite Temperature Threshold */\r
  UINT16               Cctemp;      /* Critical Composite Temperature Threshold */\r
  UINT16               Mtfa;        /* Maximum Time for Firmware Activation */\r
  UINT32               Hmpre;       /* Host Memory Buffer Preferred Size */\r
  UINT32               Hmmin;       /* Host Memory Buffer Minimum Size */\r
  UINT8                Tnvmcap[16]; /* Total NVM Capacity */\r
  UINT8                Unvmcap[16]; /* Unallocated NVM Capacity */\r
  UINT32               Rpmbs;       /* Replay Protected Memory Block Support */\r
  UINT16               Edstt;       /* Extended Device Self-test Time */\r
  UINT8                Dsto;        /* Device Self-test Options  */\r
  UINT8                Fwug;        /* Firmware Update Granularity */\r
  UINT8                Rsvd2[192];  /* Reserved as of Nvm Express 1.4 Spec */\r
  //\r
  // NVM Command Set Attributes\r
  //\r
  UINT8                Sqes;       /* Submission Queue Entry Size */\r
  UINT8                Cqes;       /* Completion Queue Entry Size */\r
  UINT16               Rsvd3;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT32               Nn;         /* Number of Namespaces */\r
  UINT16               Oncs;       /* Optional NVM Command Support */\r
  UINT16               Fuses;      /* Fused Operation Support */\r
  UINT8                Fna;        /* Format NVM Attributes */\r
  UINT8                Vwc;        /* Volatile Write Cache */\r
  UINT16               Awun;       /* Atomic Write Unit Normal */\r
  UINT16               Awupf;      /* Atomic Write Unit Power Fail */\r
  UINT8                Nvscc;      /* NVM Vendor Specific Command Configuration */\r
  UINT8                Rsvd4;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT16               Acwu;       /* Atomic Compare & Write Unit */\r
  UINT16               Rsvd5;      /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT32               Sgls;       /* SGL Support  */\r
  UINT8                Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
  //\r
  // I/O Command set Attributes\r
  //\r
  UINT8                Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
  //\r
  // Power State Descriptors\r
  //\r
  NVME_PSDESCRIPTOR    PsDescriptor[32];\r
\r
  UINT8                VendorData[1024]; /* Vendor specific data */\r
} NVME_ADMIN_CONTROLLER_DATA;\r
\r
typedef struct {\r
  UINT16    Ms;             /* Metadata Size */\r
  UINT8     Lbads;          /* LBA Data Size */\r
  UINT8     Rp    : 2;      /* Relative Performance */\r
  #define LBAF_RP_BEST      00b\r
  #define LBAF_RP_BETTER    01b\r
  #define LBAF_RP_GOOD      10b\r
  #define LBAF_RP_DEGRADED  11b\r
  UINT8     Rsvd1 : 6;      /* Reserved as of Nvm Express 1.1 Spec */\r
} NVME_LBAFORMAT;\r
\r
//\r
// Identify Namespace Data\r
//\r
typedef struct {\r
  //\r
  // NVM Command Set Specific\r
  //\r
  UINT64            Nsze;      /* Namespace Size (total number of blocks in formatted namespace) */\r
  UINT64            Ncap;      /* Namespace Capacity (max number of logical blocks) */\r
  UINT64            Nuse;      /* Namespace Utilization */\r
  UINT8             Nsfeat;    /* Namespace Features */\r
  UINT8             Nlbaf;     /* Number of LBA Formats */\r
  UINT8             Flbas;     /* Formatted LBA size */\r
  UINT8             Mc;        /* Metadata Capabilities */\r
  UINT8             Dpc;       /* End-to-end Data Protection capabilities */\r
  UINT8             Dps;       /* End-to-end Data Protection Type Settings */\r
  UINT8             Nmic;      /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
  UINT8             Rescap;    /* Reservation Capabilities */\r
  UINT8             Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT64            Eui64;     /* IEEE Extended Unique Identifier */\r
  //\r
  // LBA Format\r
  //\r
  NVME_LBAFORMAT    LbaFormat[16];\r
\r
  UINT8             Rsvd2[192];       /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT8             VendorData[3712]; /* Vendor specific data */\r
} NVME_ADMIN_NAMESPACE_DATA;\r
\r
//\r
// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec\r
//\r
typedef struct {\r
  UINT8    Bppe;       /* Boot Partition Protection Enable */\r
  UINT8    Bpl;        /* Boot Partition Lock */\r
  UINT8    Nwpac;      /* Namespace Write Protection Authentication Control */\r
  UINT8    Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */\r
} NVME_RPMB_CONFIGURATION_DATA;\r
\r
#define RPMB_FRAME_STUFF_BYTES  223\r
\r
//\r
// RPMB Data Frame as of Nvm Express 1.4 Spec\r
//\r
typedef struct {\r
  UINT8     Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */\r
                                             /* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */\r
  UINT8     Rpmbt;                           /* RPMB Target */\r
  UINT64    Nonce[2];\r
  UINT32    Wcounter;                        /* Write Counter */\r
  UINT32    Address;                         /* Starting address of data to be programmed to or read from the RPMB. */\r
  UINT32    Scount;                          /* Sector Count */\r
  UINT16    Result;\r
  UINT16    Rpmessage;                       /* Request/Response Message */\r
  // UINT8    *Data;                         /* Data to be written or read by signed access where M = 512 * Sector Count. */\r
} NVME_RPMB_DATA_FRAME;\r
\r
//\r
// RPMB Device Configuration Block Data Structure.\r
// (ref. NVMe Base spec. v2.0 Figure 460).\r
//\r
typedef struct {\r
  UINT8    BPPEnable;     /* Boot Partition Protection Enabled */\r
  UINT8    BPLock;        /* Boot Partition Lock */\r
  UINT8    NameSpaceWrP;  /* Namespace Write Protection */\r
  UINT8    Rsvd1[509];    /* Reserved as of Nvm Express 2.0 Spec */\r
} NVME_RPMB_DCB;\r
\r
//\r
// RPMB Request and Response Message Types.\r
// (ref. NVMe Base spec. v2.0 Figure 461).\r
//\r
#define NVME_RPMB_AUTHKEY_PROGRAM           0x0001\r
#define NVME_RPMB_COUNTER_READ              0x0002\r
#define NVME_RPMB_AUTHDATA_WRITE            0x0003\r
#define NVME_RPMB_AUTHDATA_READ             0x0004\r
#define NVME_RPMB_RESULT_READ               0x0005\r
#define NVME_RPMB_DCB_WRITE                 0x0006\r
#define NVME_RPMB_DCB_READ                  0x0007\r
#define NVME_RPMB_AUTHKEY_PROGRAM_RESPONSE  0x0100\r
#define NVME_RPMB_COUNTER_READ_RESPONSE     0x0200\r
#define NVME_RPMB_AUTHDATA_WRITE_RESPONSE   0x0300\r
#define NVME_RPMB_AUTHDATA_READ_RESPONSE    0x0400\r
#define NVME_RPMB_DCB_WRITE_RESPONSE        0x0600\r
#define NVME_RPMB_DCB_READ_RESPONSE         0x0700\r
\r
//\r
// RPMB Operation Result.\r
// (ref. NVMe Base spec. v2.0 Figure 462).\r
//\r
#define NVME_RPMB_RESULT_SUCCESS                 0x00\r
#define NVME_RPMB_RESULT_GENERAL_FAILURE         0x01\r
#define NVME_RPMB_RESULT_AHTHENTICATION_FAILURE  0x02\r
#define NVME_RPMB_RESULT_COUNTER_FAILURE         0x03\r
#define NVME_RPMB_RESULT_ADDRESS_FAILURE         0x04\r
#define NVME_RPMB_RESULT_WRITE_FAILURE           0x05\r
#define NVME_RPMB_RESULT_READ_FAILURE            0x06\r
#define NVME_RPMB_RESULT_AUTHKEY_NOT_PROGRAMMED  0x07\r
#define NVME_RPMB_RESULT_INVALID_DCB             0x08\r
\r
//\r
// Get Log Page - Boot Partition Log Header.\r
// (ref. NVMe Base spec. v2.0 Figure 262).\r
//\r
typedef struct {\r
  UINT8     LogIdentifier;   /* Log Identifier, shall be set to 15h */\r
  UINT8     Rsvd1[3];\r
  UINT32    Bpsz  : 15;      /* Boot Partition Size */\r
  UINT32    Rsvd2 : 16;\r
  UINT32    Abpid : 1;       /* Active Boot Partition ID */\r
  UINT8     Rsvd3[8];\r
} NVME_BOOT_PARTITION_HEADER;\r
\r
//\r
// NvmExpress Admin Identify Cmd\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Cns   : 2;\r
  UINT32    Rsvd1 : 30;\r
} NVME_ADMIN_IDENTIFY;\r
\r
//\r
// NvmExpress Admin Create I/O Completion Queue\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Qid   : 16;       /* Queue Identifier */\r
  UINT32    Qsize : 16;       /* Queue Size */\r
\r
  //\r
  // CDW 11\r
  //\r
  UINT32    Pc    : 1;        /* Physically Contiguous */\r
  UINT32    Ien   : 1;        /* Interrupts Enabled */\r
  UINT32    Rsvd1 : 14;       /* reserved as of Nvm Express 1.1 Spec */\r
  UINT32    Iv    : 16;       /* Interrupt Vector for MSI-X or MSI*/\r
} NVME_ADMIN_CRIOCQ;\r
\r
//\r
// NvmExpress Admin Create I/O Submission Queue\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Qid   : 16;       /* Queue Identifier */\r
  UINT32    Qsize : 16;       /* Queue Size */\r
\r
  //\r
  // CDW 11\r
  //\r
  UINT32    Pc    : 1;        /* Physically Contiguous */\r
  UINT32    Qprio : 2;        /* Queue Priority */\r
  UINT32    Rsvd1 : 13;       /* Reserved as of Nvm Express 1.1 Spec */\r
  UINT32    Cqid  : 16;       /* Completion Queue ID */\r
} NVME_ADMIN_CRIOSQ;\r
\r
//\r
// NvmExpress Admin Delete I/O Completion Queue\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT16    Qid;\r
  UINT16    Rsvd1;\r
} NVME_ADMIN_DEIOCQ;\r
\r
//\r
// NvmExpress Admin Delete I/O Submission Queue\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT16    Qid;\r
  UINT16    Rsvd1;\r
} NVME_ADMIN_DEIOSQ;\r
\r
//\r
// NvmExpress Admin Abort Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Sqid : 16;        /* Submission Queue identifier */\r
  UINT32    Cid  : 16;        /* Command Identifier */\r
} NVME_ADMIN_ABORT;\r
\r
//\r
// NvmExpress Admin Firmware Activate Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Fs    : 3;        /* Submission Queue identifier */\r
  UINT32    Aa    : 2;        /* Command Identifier */\r
  UINT32    Rsvd1 : 27;\r
} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
\r
//\r
// NvmExpress Admin Firmware Image Download Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Numd;             /* Number of Dwords */\r
  //\r
  // CDW 11\r
  //\r
  UINT32    Ofst;             /* Offset */\r
} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
\r
//\r
// NvmExpress Admin Get Features Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Fid   : 8;         /* Feature Identifier */\r
  UINT32    Sel   : 3;         /* Select */\r
  UINT32    Rsvd1 : 21;\r
} NVME_ADMIN_GET_FEATURES;\r
\r
//\r
// NvmExpress Admin Get Log Page Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Lid   : 8;        /* Log Page Identifier */\r
  #define LID_ERROR_INFO    0x1\r
  #define LID_SMART_INFO    0x2\r
  #define LID_FW_SLOT_INFO  0x3\r
  #define LID_BP_INFO       0x15\r
  UINT32    Rsvd1 : 8;\r
  UINT32    Numd  : 12;       /* Number of Dwords */\r
  UINT32    Rsvd2 : 4;        /* Reserved as of Nvm Express 1.1 Spec */\r
} NVME_ADMIN_GET_LOG_PAGE;\r
\r
//\r
// NvmExpress Admin Set Features Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Fid   : 8;        /* Feature Identifier */\r
  UINT32    Rsvd1 : 23;\r
  UINT32    Sv    : 1;        /* Save */\r
} NVME_ADMIN_SET_FEATURES;\r
\r
//\r
// NvmExpress Admin Format NVM Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Lbaf  : 4;        /* LBA Format */\r
  UINT32    Ms    : 1;        /* Metadata Settings */\r
  UINT32    Pi    : 3;        /* Protection Information */\r
  UINT32    Pil   : 1;        /* Protection Information Location */\r
  UINT32    Ses   : 3;        /* Secure Erase Settings */\r
  UINT32    Rsvd1 : 20;\r
} NVME_ADMIN_FORMAT_NVM;\r
\r
//\r
// NvmExpress Admin Security Receive Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Rsvd1 : 8;\r
  UINT32    Spsp  : 16;       /* SP Specific */\r
  UINT32    Secp  : 8;        /* Security Protocol */\r
  //\r
  // CDW 11\r
  //\r
  UINT32    Al;               /* Allocation Length */\r
} NVME_ADMIN_SECURITY_RECEIVE;\r
\r
//\r
// NvmExpress Admin Security Send Command\r
//\r
typedef struct {\r
  //\r
  // CDW 10\r
  //\r
  UINT32    Rsvd1 : 8;\r
  UINT32    Spsp  : 16;       /* SP Specific */\r
  UINT32    Secp  : 8;        /* Security Protocol */\r
  //\r
  // CDW 11\r
  //\r
  UINT32    Tl;               /* Transfer Length */\r
} NVME_ADMIN_SECURITY_SEND;\r
\r
typedef union {\r
  NVME_ADMIN_IDENTIFY                   Identify;\r
  NVME_ADMIN_CRIOCQ                     CrIoCq;\r
  NVME_ADMIN_CRIOSQ                     CrIoSq;\r
  NVME_ADMIN_DEIOCQ                     DeIoCq;\r
  NVME_ADMIN_DEIOSQ                     DeIoSq;\r
  NVME_ADMIN_ABORT                      Abort;\r
  NVME_ADMIN_FIRMWARE_ACTIVATE          Activate;\r
  NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD    FirmwareImageDownload;\r
  NVME_ADMIN_GET_FEATURES               GetFeatures;\r
  NVME_ADMIN_GET_LOG_PAGE               GetLogPage;\r
  NVME_ADMIN_SET_FEATURES               SetFeatures;\r
  NVME_ADMIN_FORMAT_NVM                 FormatNvm;\r
  NVME_ADMIN_SECURITY_RECEIVE           SecurityReceive;\r
  NVME_ADMIN_SECURITY_SEND              SecuritySend;\r
} NVME_ADMIN_CMD;\r
\r
typedef struct {\r
  UINT32    Cdw10;\r
  UINT32    Cdw11;\r
  UINT32    Cdw12;\r
  UINT32    Cdw13;\r
  UINT32    Cdw14;\r
  UINT32    Cdw15;\r
} NVME_RAW;\r
\r
typedef union {\r
  NVME_ADMIN_CMD    Admin; // Union of Admin commands\r
  NVME_CMD          Nvm;   // Union of Nvm commands\r
  NVME_RAW          Raw;\r
} NVME_PAYLOAD;\r
\r
//\r
// Submission Queue\r
//\r
typedef struct {\r
  //\r
  // CDW 0, Common to all commands\r
  //\r
  UINT8           Opc;       // Opcode\r
  UINT8           Fuse  : 2; // Fused Operation\r
  UINT8           Rsvd1 : 5;\r
  UINT8           Psdt  : 1; // PRP or SGL for Data Transfer\r
  UINT16          Cid;       // Command Identifier\r
\r
  //\r
  // CDW 1\r
  //\r
  UINT32          Nsid;     // Namespace Identifier\r
\r
  //\r
  // CDW 2,3\r
  //\r
  UINT64          Rsvd2;\r
\r
  //\r
  // CDW 4,5\r
  //\r
  UINT64          Mptr;     // Metadata Pointer\r
\r
  //\r
  // CDW 6-9\r
  //\r
  UINT64          Prp[2];   // First and second PRP entries\r
\r
  NVME_PAYLOAD    Payload;\r
} NVME_SQ;\r
\r
//\r
// Completion Queue\r
//\r
typedef struct {\r
  //\r
  // CDW 0\r
  //\r
  UINT32    Dword0;\r
  //\r
  // CDW 1\r
  //\r
  UINT32    Rsvd1;\r
  //\r
  // CDW 2\r
  //\r
  UINT16    Sqhd;           // Submission Queue Head Pointer\r
  UINT16    Sqid;           // Submission Queue Identifier\r
  //\r
  // CDW 3\r
  //\r
  UINT16    Cid;            // Command Identifier\r
  UINT16    Pt    : 1;      // Phase Tag\r
  UINT16    Sc    : 8;      // Status Code\r
  UINT16    Sct   : 3;      // Status Code Type\r
  UINT16    Rsvd2 : 2;\r
  UINT16    Mo    : 1;      // More\r
  UINT16    Dnr   : 1;      // Do Not Retry\r
} NVME_CQ;\r
\r
//\r
// Nvm Express Admin cmd opcodes\r
//\r
#define NVME_ADMIN_DEIOSQ_CMD               0x00\r
#define NVME_ADMIN_CRIOSQ_CMD               0x01\r
#define NVME_ADMIN_GET_LOG_PAGE_CMD         0x02\r
#define NVME_ADMIN_DEIOCQ_CMD               0x04\r
#define NVME_ADMIN_CRIOCQ_CMD               0x05\r
#define NVME_ADMIN_IDENTIFY_CMD             0x06\r
#define NVME_ADMIN_ABORT_CMD                0x08\r
#define NVME_ADMIN_SET_FEATURES_CMD         0x09\r
#define NVME_ADMIN_GET_FEATURES_CMD         0x0A\r
#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD  0x0C\r
#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD  0x0D\r
#define NVME_ADMIN_FW_COMMIT_CMD            0x10\r
#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD    0x11\r
#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD  0x15\r
#define NVME_ADMIN_FORMAT_NVM_CMD           0x80\r
#define NVME_ADMIN_SECURITY_SEND_CMD        0x81\r
#define NVME_ADMIN_SECURITY_RECEIVE_CMD     0x82\r
\r
#define NVME_IO_FLUSH_OPC  0\r
#define NVME_IO_WRITE_OPC  1\r
#define NVME_IO_READ_OPC   2\r
\r
typedef enum {\r
  DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,\r
  CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,\r
  GetLogPageOpcode              = NVME_ADMIN_GET_LOG_PAGE_CMD,\r
  DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,\r
  CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,\r
  IdentifyOpcode                = NVME_ADMIN_IDENTIFY_CMD,\r
  AbortOpcode                   = NVME_ADMIN_ABORT_CMD,\r
  SetFeaturesOpcode             = NVME_ADMIN_SET_FEATURES_CMD,\r
  GetFeaturesOpcode             = NVME_ADMIN_GET_FEATURES_CMD,\r
  AsyncEventRequestOpcode       = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,\r
  NamespaceManagementOpcode     = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,\r
  FirmwareCommitOpcode          = NVME_ADMIN_FW_COMMIT_CMD,\r
  FirmwareImageDownloadOpcode   = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,\r
  NamespaceAttachmentOpcode     = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,\r
  FormatNvmOpcode               = NVME_ADMIN_FORMAT_NVM_CMD,\r
  SecuritySendOpcode            = NVME_ADMIN_SECURITY_SEND_CMD,\r
  SecurityReceiveOpcode         = NVME_ADMIN_SECURITY_RECEIVE_CMD\r
} NVME_ADMIN_COMMAND_OPCODE;\r
\r
//\r
// Controller or Namespace Structure (CNS) field\r
// (ref. spec. v1.1 figure 82).\r
//\r
typedef enum {\r
  IdentifyNamespaceCns    = 0x0,\r
  IdentifyControllerCns   = 0x1,\r
  IdentifyActiveNsListCns = 0x2\r
} NVME_ADMIN_IDENTIFY_CNS;\r
\r
//\r
// Commit Action\r
// (ref. spec. 1.1 figure 60).\r
//\r
typedef enum {\r
  ActivateActionReplace         = 0x0,\r
  ActivateActionReplaceActivate = 0x1,\r
  ActivateActionActivate        = 0x2\r
} NVME_FW_ACTIVATE_ACTION;\r
\r
//\r
// Firmware Slot\r
// (ref. spec. 1.1 Figure 60).\r
//\r
typedef enum {\r
  FirmwareSlotCtrlChooses = 0x0,\r
  FirmwareSlot1           = 0x1,\r
  FirmwareSlot2           = 0x2,\r
  FirmwareSlot3           = 0x3,\r
  FirmwareSlot4           = 0x4,\r
  FirmwareSlot5           = 0x5,\r
  FirmwareSlot6           = 0x6,\r
  FirmwareSlot7           = 0x7\r
} NVME_FW_ACTIVATE_SLOT;\r
\r
//\r
// Get Log Page ? Log Page Identifiers\r
// (ref. spec. v1.1 Figure 73).\r
//\r
typedef enum {\r
  ErrorInfoLogID        = LID_ERROR_INFO,\r
  SmartHealthInfoLogID  = LID_SMART_INFO,\r
  FirmwareSlotInfoLogID = LID_FW_SLOT_INFO\r
} NVME_LOG_ID;\r
\r
//\r
// Get Log Page ? Firmware Slot Information Log\r
// (ref. spec. v1.1 Figure 77).\r
//\r
typedef struct {\r
  //\r
  // Indicates the firmware slot from which the actively running firmware revision was loaded.\r
  //\r
  UINT8    ActivelyRunningFwSlot : 3;\r
  UINT8                          : 1;\r
  //\r
  // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.\r
  //\r
  UINT8    NextActiveFwSlot      : 3;\r
  UINT8                          : 1;\r
} NVME_ACTIVE_FW_INFO;\r
\r
//\r
// Get Log Page ? Firmware Slot Information Log\r
// (ref. spec. v1.1 Figure 77).\r
//\r
typedef struct {\r
  //\r
  // Specifies information about the active firmware revision.\r
  // s\r
  NVME_ACTIVE_FW_INFO    ActiveFwInfo;\r
  UINT8                  Reserved1[7];\r
  //\r
  // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.\r
  //\r
  CHAR8                  FwRevisionSlot[7][8];\r
  UINT8                  Reserved2[448];\r
} NVME_FW_SLOT_INFO_LOG;\r
\r
//\r
// SMART / Health Information (Log Identifier 02h)\r
// (ref. spec. v1.1 5.10.1.2)\r
//\r
typedef struct {\r
  //\r
  // This field indicates critical warnings for the state of the controller.\r
  //\r
  UINT8     CriticalWarningAvailableSpare : 1;\r
  UINT8     CriticalWarningTemperature    : 1;\r
  UINT8     CriticalWarningReliability    : 1;\r
  UINT8     CriticalWarningMediaReadOnly  : 1;\r
  UINT8     CriticalWarningVolatileBackup : 1;\r
  UINT8     CriticalWarningReserved       : 3;\r
  //\r
  // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.\r
  //\r
  UINT16    CompositeTemp;\r
  //\r
  // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.\r
  //\r
  UINT8     AvailableSpare;\r
  //\r
  // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).\r
  //\r
  UINT8     AvailableSpareThreshold;\r
  //\r
  // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).\r
  //\r
  UINT8     PercentageUsed;\r
  UINT8     Reserved1[26];\r
  //\r
  // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.\r
  //\r
  UINT8     DataUnitsRead[16];\r
  //\r
  // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.\r
  //\r
  UINT8     DataUnitsWritten[16];\r
  //\r
  // Contains the number of read commands completed by the controller.\r
  //\r
  UINT8     HostReadCommands[16];\r
  //\r
  // Contains the number of write commands completed by the controller.\r
  //\r
  UINT8     HostWriteCommands[16];\r
  //\r
  // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.\r
  //\r
  UINT8     ControllerBusyTime[16];\r
  //\r
  // Contains the number of power cycles.\r
  //\r
  UINT8     PowerCycles[16];\r
  //\r
  // Contains the number of power-on hours.\r
  //\r
  UINT8     PowerOnHours[16];\r
  //\r
  // Contains the number of unsafe shutdowns.\r
  //\r
  UINT8     UnsafeShutdowns[16];\r
  //\r
  // Contains the number of occurrences where the controller detected an unrecovered data integrity error.\r
  //\r
  UINT8     MediaAndDataIntegrityErrors[16];\r
  //\r
  // Contains the number of Error Information log entries over the life of the controller.\r
  //\r
  UINT8     NumberErrorInformationLogEntries[16];\r
  //\r
  // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
  //\r
  UINT32    WarningCompositeTemperatureTime;\r
  //\r
  // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
  //\r
  UINT32    CriticalCompositeTemperatureTime;\r
  //\r
  // Contains the current temperature in degrees Kelvin reported by the temperature sensor.  An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.\r
  //\r
  UINT16    TemperatureSensor[8];\r
  UINT8     Reserved2[296];\r
} NVME_SMART_HEALTH_INFO_LOG;\r
\r
#pragma pack()\r
\r
#endif\r