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MdePkg ACPI: Correct processor struct of PPTT
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111cd0dd
DR		 1/** @file\r
2 Definitions based on NVMe spec. version 1.1.\r
3\r
4 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
a607eb97 5 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
111cd0dd
DR		 6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14 @par Specification Reference:\r
15 NVMe Specification 1.1\r
16\r
17**/\r
18\r
19#ifndef __NVM_E_H__\r
20#define __NVM_E_H__\r
21\r
22#pragma pack(1)\r
23\r
24//\r
25// controller register offsets\r
26//\r
27#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
28#define NVME_VER_OFFSET 0x0008 // Version\r
29#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
30#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
31#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
32#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
33#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
34#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
35#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
36#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
37#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
38#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
39\r
40//\r
41// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
42// Get the doorbell stride bit shift value from the controller capabilities.\r
43//\r
44#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
45#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
46\r
47\r
48#pragma pack(1)\r
49\r
50//\r
51// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
52//\r
53typedef struct {\r
54 UINT16 Mqes; // Maximum Queue Entries Supported\r
55 UINT8 Cqr:1; // Contiguous Queues Required\r
56 UINT8 Ams:2; // Arbitration Mechanism Supported\r
57 UINT8 Rsvd1:5;\r
58 UINT8 To; // Timeout\r
59 UINT16 Dstrd:4;\r
60 UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS\r
61 UINT16 Css:4; // Command Sets Supported - Bit 37\r
62 UINT16 Rsvd3:7;\r
63 UINT8 Mpsmin:4;\r
64 UINT8 Mpsmax:4;\r
65 UINT8 Rsvd4;\r
66} NVME_CAP;\r
67\r
68//\r
69// 3.1.2 Offset 08h: VS - Version\r
70//\r
71typedef struct {\r
72 UINT16 Mnr; // Minor version number\r
73 UINT16 Mjr; // Major version number\r
74} NVME_VER;\r
75\r
76//\r
77// 3.1.5 Offset 14h: CC - Controller Configuration\r
78//\r
79typedef struct {\r
80 UINT16 En:1; // Enable\r
81 UINT16 Rsvd1:3;\r
82 UINT16 Css:3; // I/O Command Set Selected\r
83 UINT16 Mps:4; // Memory Page Size\r
84 UINT16 Ams:3; // Arbitration Mechanism Selected\r
85 UINT16 Shn:2; // Shutdown Notification\r
86 UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
87 UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
88 UINT8 Rsvd2;\r
89} NVME_CC;\r
a607eb97
RN		 90#define NVME_CC_SHN_NORMAL_SHUTDOWN 1\r
91#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2\r
111cd0dd
DR		 92\r
93//\r
94// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
95//\r
96typedef struct {\r
97 UINT32 Rdy:1; // Ready\r
98 UINT32 Cfs:1; // Controller Fatal Status\r
99 UINT32 Shst:2; // Shutdown Status\r
100 UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
101 UINT32 Rsvd1:27;\r
102} NVME_CSTS;\r
a607eb97
RN		 103#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1\r
104#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2\r
111cd0dd
DR		 105//\r
106// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
107//\r
108typedef struct {\r
109 UINT16 Asqs:12; // Submission Queue Size\r
110 UINT16 Rsvd1:4;\r
111 UINT16 Acqs:12; // Completion Queue Size\r
112 UINT16 Rsvd2:4;\r
113} NVME_AQA;\r
114\r
115//\r
116// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
117//\r
118#define NVME_ASQ UINT64\r
119//\r
120// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
121//\r
122#define NVME_ACQ UINT64\r
123\r
124//\r
125// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
126//\r
127typedef struct {\r
128 UINT16 Sqt;\r
129 UINT16 Rsvd1;\r
130} NVME_SQTDBL;\r
131\r
132//\r
133// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
134//\r
135typedef struct {\r
136 UINT16 Cqh;\r
137 UINT16 Rsvd1;\r
138} NVME_CQHDBL;\r
139\r
140//\r
141// NVM command set structures\r
142//\r
143// Read Command\r
144//\r
145typedef struct {\r
146 //\r
147 // CDW 10, 11\r
148 //\r
149 UINT64 Slba; /* Starting Sector Address */\r
150 //\r
151 // CDW 12\r
152 //\r
153 UINT16 Nlb; /* Number of Sectors */\r
154 UINT16 Rsvd1:10;\r
155 UINT16 Prinfo:4; /* Protection Info Check */\r
156 UINT16 Fua:1; /* Force Unit Access */\r
157 UINT16 Lr:1; /* Limited Retry */\r
158 //\r
159 // CDW 13\r
160 //\r
161 UINT32 Af:4; /* Access Frequency */\r
162 UINT32 Al:2; /* Access Latency */\r
163 UINT32 Sr:1; /* Sequential Request */\r
164 UINT32 In:1; /* Incompressible */\r
165 UINT32 Rsvd2:24;\r
166 //\r
167 // CDW 14\r
168 //\r
169 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
170 //\r
171 // CDW 15\r
172 //\r
173 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
174 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
175} NVME_READ;\r
176\r
177//\r
178// Write Command\r
179//\r
180typedef struct {\r
181 //\r
182 // CDW 10, 11\r
183 //\r
184 UINT64 Slba; /* Starting Sector Address */\r
185 //\r
186 // CDW 12\r
187 //\r
188 UINT16 Nlb; /* Number of Sectors */\r
189 UINT16 Rsvd1:10;\r
190 UINT16 Prinfo:4; /* Protection Info Check */\r
191 UINT16 Fua:1; /* Force Unit Access */\r
192 UINT16 Lr:1; /* Limited Retry */\r
193 //\r
194 // CDW 13\r
195 //\r
196 UINT32 Af:4; /* Access Frequency */\r
197 UINT32 Al:2; /* Access Latency */\r
198 UINT32 Sr:1; /* Sequential Request */\r
199 UINT32 In:1; /* Incompressible */\r
200 UINT32 Rsvd2:24;\r
201 //\r
202 // CDW 14\r
203 //\r
204 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
205 //\r
206 // CDW 15\r
207 //\r
208 UINT16 Lbat; /* Logical Block Application Tag */\r
209 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
210} NVME_WRITE;\r
211\r
212//\r
213// Flush\r
214//\r
215typedef struct {\r
216 //\r
217 // CDW 10\r
218 //\r
219 UINT32 Flush; /* Flush */\r
220} NVME_FLUSH;\r
221\r
222//\r
223// Write Uncorrectable command\r
224//\r
225typedef struct {\r
226 //\r
227 // CDW 10, 11\r
228 //\r
229 UINT64 Slba; /* Starting LBA */\r
230 //\r
231 // CDW 12\r
232 //\r
233 UINT32 Nlb:16; /* Number of Logical Blocks */\r
234 UINT32 Rsvd1:16;\r
235} NVME_WRITE_UNCORRECTABLE;\r
236\r
237//\r
238// Write Zeroes command\r
239//\r
240typedef struct {\r
241 //\r
242 // CDW 10, 11\r
243 //\r
244 UINT64 Slba; /* Starting LBA */\r
245 //\r
246 // CDW 12\r
247 //\r
248 UINT16 Nlb; /* Number of Logical Blocks */\r
249 UINT16 Rsvd1:10;\r
250 UINT16 Prinfo:4; /* Protection Info Check */\r
251 UINT16 Fua:1; /* Force Unit Access */\r
252 UINT16 Lr:1; /* Limited Retry */\r
253 //\r
254 // CDW 13\r
255 //\r
256 UINT32 Rsvd2;\r
257 //\r
258 // CDW 14\r
259 //\r
260 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
261 //\r
262 // CDW 15\r
263 //\r
264 UINT16 Lbat; /* Logical Block Application Tag */\r
265 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
266} NVME_WRITE_ZEROES;\r
267\r
268//\r
269// Compare command\r
270//\r
271typedef struct {\r
272 //\r
273 // CDW 10, 11\r
274 //\r
275 UINT64 Slba; /* Starting LBA */\r
276 //\r
277 // CDW 12\r
278 //\r
279 UINT16 Nlb; /* Number of Logical Blocks */\r
280 UINT16 Rsvd1:10;\r
281 UINT16 Prinfo:4; /* Protection Info Check */\r
282 UINT16 Fua:1; /* Force Unit Access */\r
283 UINT16 Lr:1; /* Limited Retry */\r
284 //\r
285 // CDW 13\r
286 //\r
287 UINT32 Rsvd2;\r
288 //\r
289 // CDW 14\r
290 //\r
291 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
292 //\r
293 // CDW 15\r
294 //\r
295 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
296 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
297} NVME_COMPARE;\r
298\r
299typedef union {\r
300 NVME_READ Read;\r
301 NVME_WRITE Write;\r
302 NVME_FLUSH Flush;\r
303 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r
304 NVME_WRITE_ZEROES WriteZeros;\r
305 NVME_COMPARE Compare;\r
306} NVME_CMD;\r
307\r
308typedef struct {\r
309 UINT16 Mp; /* Maximum Power */\r
310 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
311 UINT8 Mps:1; /* Max Power Scale */\r
312 UINT8 Nops:1; /* Non-Operational State */\r
313 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
314 UINT32 Enlat; /* Entry Latency */\r
315 UINT32 Exlat; /* Exit Latency */\r
316 UINT8 Rrt:5; /* Relative Read Throughput */\r
317 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
318 UINT8 Rrl:5; /* Relative Read Leatency */\r
319 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
320 UINT8 Rwt:5; /* Relative Write Throughput */\r
321 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
322 UINT8 Rwl:5; /* Relative Write Leatency */\r
323 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
324 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
325} NVME_PSDESCRIPTOR;\r
326\r
327//\r
328// Identify Controller Data\r
329//\r
330typedef struct {\r
331 //\r
332 // Controller Capabilities and Features 0-255\r
333 //\r
334 UINT16 Vid; /* PCI Vendor ID */\r
335 UINT16 Ssvid; /* PCI sub-system vendor ID */\r
336 UINT8 Sn[20]; /* Product serial number */\r
337\r
338 UINT8 Mn[40]; /* Proeduct model number */\r
339 UINT8 Fr[8]; /* Firmware Revision */\r
340 UINT8 Rab; /* Recommended Arbitration Burst */\r
341 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */\r
342 UINT8 Cmic; /* Multi-interface Capabilities */\r
343 UINT8 Mdts; /* Maximum Data Transfer Size */\r
344 UINT8 Cntlid[2]; /* Controller ID */\r
345 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
346 //\r
347 // Admin Command Set Attributes\r
348 //\r
349 UINT16 Oacs; /* Optional Admin Command Support */\r
350 #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3\r
351 #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2\r
352 #define FORMAT_NVM_SUPPORTED BIT1\r
353 #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0\r
354 UINT8 Acl; /* Abort Command Limit */\r
355 UINT8 Aerl; /* Async Event Request Limit */\r
356 UINT8 Frmw; /* Firmware updates */\r
357 UINT8 Lpa; /* Log Page Attributes */\r
358 UINT8 Elpe; /* Error Log Page Entries */\r
359 UINT8 Npss; /* Number of Power States Support */\r
360 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
361 UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
362 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r
363 //\r
364 // NVM Command Set Attributes\r
365 //\r
366 UINT8 Sqes; /* Submission Queue Entry Size */\r
367 UINT8 Cqes; /* Completion Queue Entry Size */\r
368 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
369 UINT32 Nn; /* Number of Namespaces */\r
370 UINT16 Oncs; /* Optional NVM Command Support */\r
371 UINT16 Fuses; /* Fused Operation Support */\r
372 UINT8 Fna; /* Format NVM Attributes */\r
373 UINT8 Vwc; /* Volatile Write Cache */\r
374 UINT16 Awun; /* Atomic Write Unit Normal */\r
375 UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
376 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
377 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
378 UINT16 Acwu; /* Atomic Compare & Write Unit */\r
379 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
380 UINT32 Sgls; /* SGL Support */\r
381 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
382 //\r
383 // I/O Command set Attributes\r
384 //\r
385 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
386 //\r
387 // Power State Descriptors\r
388 //\r
389 NVME_PSDESCRIPTOR PsDescriptor[32];\r
390\r
391 UINT8 VendorData[1024]; /* Vendor specific data */\r
392} NVME_ADMIN_CONTROLLER_DATA;\r
393\r
394typedef struct {\r
395 UINT16 Ms; /* Metadata Size */\r
396 UINT8 Lbads; /* LBA Data Size */\r
397 UINT8 Rp:2; /* Relative Performance */\r
398 #define LBAF_RP_BEST 00b\r
399 #define LBAF_RP_BETTER 01b\r
400 #define LBAF_RP_GOOD 10b\r
401 #define LBAF_RP_DEGRADED 11b\r
402 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
403} NVME_LBAFORMAT;\r
404\r
405//\r
406// Identify Namespace Data\r
407//\r
408typedef struct {\r
409 //\r
410 // NVM Command Set Specific\r
411 //\r
412 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
413 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
414 UINT64 Nuse; /* Namespace Utilization */\r
415 UINT8 Nsfeat; /* Namespace Features */\r
416 UINT8 Nlbaf; /* Number of LBA Formats */\r
417 UINT8 Flbas; /* Formatted LBA size */\r
418 UINT8 Mc; /* Metadata Capabilities */\r
419 UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
420 UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
421 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
422 UINT8 Rescap; /* Reservation Capabilities */\r
423 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
424 UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
425 //\r
426 // LBA Format\r
427 //\r
428 NVME_LBAFORMAT LbaFormat[16];\r
429\r
430 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
431 UINT8 VendorData[3712]; /* Vendor specific data */\r
432} NVME_ADMIN_NAMESPACE_DATA;\r
433\r
434//\r
435// NvmExpress Admin Identify Cmd\r
436//\r
437typedef struct {\r
438 //\r
439 // CDW 10\r
440 //\r
441 UINT32 Cns:2;\r
442 UINT32 Rsvd1:30;\r
443} NVME_ADMIN_IDENTIFY;\r
444\r
445//\r
446// NvmExpress Admin Create I/O Completion Queue\r
447//\r
448typedef struct {\r
449 //\r
450 // CDW 10\r
451 //\r
452 UINT32 Qid:16; /* Queue Identifier */\r
453 UINT32 Qsize:16; /* Queue Size */\r
454\r
455 //\r
456 // CDW 11\r
457 //\r
458 UINT32 Pc:1; /* Physically Contiguous */\r
459 UINT32 Ien:1; /* Interrupts Enabled */\r
460 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
461 UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/\r
462} NVME_ADMIN_CRIOCQ;\r
463\r
464//\r
465// NvmExpress Admin Create I/O Submission Queue\r
466//\r
467typedef struct {\r
468 //\r
469 // CDW 10\r
470 //\r
471 UINT32 Qid:16; /* Queue Identifier */\r
472 UINT32 Qsize:16; /* Queue Size */\r
473\r
474 //\r
475 // CDW 11\r
476 //\r
477 UINT32 Pc:1; /* Physically Contiguous */\r
478 UINT32 Qprio:2; /* Queue Priority */\r
479 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
480 UINT32 Cqid:16; /* Completion Queue ID */\r
481} NVME_ADMIN_CRIOSQ;\r
482\r
483//\r
484// NvmExpress Admin Delete I/O Completion Queue\r
485//\r
486typedef struct {\r
487 //\r
488 // CDW 10\r
489 //\r
490 UINT16 Qid;\r
491 UINT16 Rsvd1;\r
492} NVME_ADMIN_DEIOCQ;\r
493\r
494//\r
495// NvmExpress Admin Delete I/O Submission Queue\r
496//\r
497typedef struct {\r
498 //\r
499 // CDW 10\r
500 //\r
501 UINT16 Qid;\r
502 UINT16 Rsvd1;\r
503} NVME_ADMIN_DEIOSQ;\r
504\r
505//\r
506// NvmExpress Admin Abort Command\r
507//\r
508typedef struct {\r
509 //\r
510 // CDW 10\r
511 //\r
512 UINT32 Sqid:16; /* Submission Queue identifier */\r
513 UINT32 Cid:16; /* Command Identifier */\r
514} NVME_ADMIN_ABORT;\r
515\r
516//\r
517// NvmExpress Admin Firmware Activate Command\r
518//\r
519typedef struct {\r
520 //\r
521 // CDW 10\r
522 //\r
523 UINT32 Fs:3; /* Submission Queue identifier */\r
524 UINT32 Aa:2; /* Command Identifier */\r
525 UINT32 Rsvd1:27;\r
526} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
527\r
528//\r
529// NvmExpress Admin Firmware Image Download Command\r
530//\r
531typedef struct {\r
532 //\r
533 // CDW 10\r
534 //\r
535 UINT32 Numd; /* Number of Dwords */\r
536 //\r
537 // CDW 11\r
538 //\r
539 UINT32 Ofst; /* Offset */\r
540} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
541\r
542//\r
543// NvmExpress Admin Get Features Command\r
544//\r
545typedef struct {\r
546 //\r
547 // CDW 10\r
548 //\r
549 UINT32 Fid:8; /* Feature Identifier */\r
550 UINT32 Sel:3; /* Select */\r
551 UINT32 Rsvd1:21;\r
552} NVME_ADMIN_GET_FEATURES;\r
553\r
554//\r
555// NvmExpress Admin Get Log Page Command\r
556//\r
557typedef struct {\r
558 //\r
559 // CDW 10\r
560 //\r
561 UINT32 Lid:8; /* Log Page Identifier */\r
562 #define LID_ERROR_INFO 0x1\r
563 #define LID_SMART_INFO 0x2\r
564 #define LID_FW_SLOT_INFO 0x3\r
565 UINT32 Rsvd1:8;\r
566 UINT32 Numd:12; /* Number of Dwords */\r
567 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
568} NVME_ADMIN_GET_LOG_PAGE;\r
569\r
570//\r
571// NvmExpress Admin Set Features Command\r
572//\r
573typedef struct {\r
574 //\r
575 // CDW 10\r
576 //\r
577 UINT32 Fid:8; /* Feature Identifier */\r
578 UINT32 Rsvd1:23;\r
579 UINT32 Sv:1; /* Save */\r
580} NVME_ADMIN_SET_FEATURES;\r
581\r
582//\r
583// NvmExpress Admin Format NVM Command\r
584//\r
585typedef struct {\r
586 //\r
587 // CDW 10\r
588 //\r
589 UINT32 Lbaf:4; /* LBA Format */\r
590 UINT32 Ms:1; /* Metadata Settings */\r
591 UINT32 Pi:3; /* Protection Information */\r
592 UINT32 Pil:1; /* Protection Information Location */\r
593 UINT32 Ses:3; /* Secure Erase Settings */\r
594 UINT32 Rsvd1:20;\r
595} NVME_ADMIN_FORMAT_NVM;\r
596\r
597//\r
598// NvmExpress Admin Security Receive Command\r
599//\r
600typedef struct {\r
601 //\r
602 // CDW 10\r
603 //\r
604 UINT32 Rsvd1:8;\r
605 UINT32 Spsp:16; /* SP Specific */\r
606 UINT32 Secp:8; /* Security Protocol */\r
607 //\r
608 // CDW 11\r
609 //\r
610 UINT32 Al; /* Allocation Length */\r
611} NVME_ADMIN_SECURITY_RECEIVE;\r
612\r
613//\r
614// NvmExpress Admin Security Send Command\r
615//\r
616typedef struct {\r
617 //\r
618 // CDW 10\r
619 //\r
620 UINT32 Rsvd1:8;\r
621 UINT32 Spsp:16; /* SP Specific */\r
622 UINT32 Secp:8; /* Security Protocol */\r
623 //\r
624 // CDW 11\r
625 //\r
626 UINT32 Tl; /* Transfer Length */\r
627} NVME_ADMIN_SECURITY_SEND;\r
628\r
629typedef union {\r
630 NVME_ADMIN_IDENTIFY Identify;\r
631 NVME_ADMIN_CRIOCQ CrIoCq;\r
632 NVME_ADMIN_CRIOSQ CrIoSq;\r
633 NVME_ADMIN_DEIOCQ DeIoCq;\r
634 NVME_ADMIN_DEIOSQ DeIoSq;\r
635 NVME_ADMIN_ABORT Abort;\r
636 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r
637 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r
638 NVME_ADMIN_GET_FEATURES GetFeatures;\r
639 NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r
640 NVME_ADMIN_SET_FEATURES SetFeatures;\r
641 NVME_ADMIN_FORMAT_NVM FormatNvm;\r
642 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r
643 NVME_ADMIN_SECURITY_SEND SecuritySend;\r
644} NVME_ADMIN_CMD;\r
645\r
646typedef struct {\r
647 UINT32 Cdw10;\r
648 UINT32 Cdw11;\r
649 UINT32 Cdw12;\r
650 UINT32 Cdw13;\r
651 UINT32 Cdw14;\r
652 UINT32 Cdw15;\r
653} NVME_RAW;\r
654\r
655typedef union {\r
656 NVME_ADMIN_CMD Admin; // Union of Admin commands\r
657 NVME_CMD Nvm; // Union of Nvm commands\r
658 NVME_RAW Raw;\r
659} NVME_PAYLOAD;\r
660\r
661//\r
662// Submission Queue\r
663//\r
664typedef struct {\r
665 //\r
666 // CDW 0, Common to all comnmands\r
667 //\r
668 UINT8 Opc; // Opcode\r
669 UINT8 Fuse:2; // Fused Operation\r
670 UINT8 Rsvd1:5;\r
671 UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
672 UINT16 Cid; // Command Identifier\r
673\r
674 //\r
675 // CDW 1\r
676 //\r
677 UINT32 Nsid; // Namespace Identifier\r
678\r
679 //\r
680 // CDW 2,3\r
681 //\r
682 UINT64 Rsvd2;\r
683\r
684 //\r
685 // CDW 4,5\r
686 //\r
687 UINT64 Mptr; // Metadata Pointer\r
688\r
689 //\r
690 // CDW 6-9\r
691 //\r
692 UINT64 Prp[2]; // First and second PRP entries\r
693\r
694 NVME_PAYLOAD Payload;\r
695\r
696} NVME_SQ;\r
697\r
698//\r
699// Completion Queue\r
700//\r
701typedef struct {\r
702 //\r
703 // CDW 0\r
704 //\r
705 UINT32 Dword0;\r
706 //\r
707 // CDW 1\r
708 //\r
709 UINT32 Rsvd1;\r
710 //\r
711 // CDW 2\r
712 //\r
713 UINT16 Sqhd; // Submission Queue Head Pointer\r
714 UINT16 Sqid; // Submission Queue Identifier\r
715 //\r
716 // CDW 3\r
717 //\r
718 UINT16 Cid; // Command Identifier\r
719 UINT16 Pt:1; // Phase Tag\r
720 UINT16 Sc:8; // Status Code\r
721 UINT16 Sct:3; // Status Code Type\r
722 UINT16 Rsvd2:2;\r
723 UINT16 Mo:1; // More\r
724 UINT16 Dnr:1; // Do Not Retry\r
725} NVME_CQ;\r
726\r
727//\r
728// Nvm Express Admin cmd opcodes\r
729//\r
730#define NVME_ADMIN_DEIOSQ_CMD 0x00\r
731#define NVME_ADMIN_CRIOSQ_CMD 0x01\r
732#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02\r
733#define NVME_ADMIN_DEIOCQ_CMD 0x04\r
734#define NVME_ADMIN_CRIOCQ_CMD 0x05\r
735#define NVME_ADMIN_IDENTIFY_CMD 0x06\r
736#define NVME_ADMIN_ABORT_CMD 0x08\r
737#define NVME_ADMIN_SET_FEATURES_CMD 0x09\r
738#define NVME_ADMIN_GET_FEATURES_CMD 0x0A\r
739#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C\r
740#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D\r
741#define NVME_ADMIN_FW_COMMIT_CMD 0x10\r
742#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11\r
743#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15\r
744#define NVME_ADMIN_FORMAT_NVM_CMD 0x80\r
745#define NVME_ADMIN_SECURITY_SEND_CMD 0x81\r
746#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82\r
747\r
748#define NVME_IO_FLUSH_OPC 0\r
749#define NVME_IO_WRITE_OPC 1\r
750#define NVME_IO_READ_OPC 2\r
751\r
752typedef enum {\r
753 DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,\r
754 CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,\r
755 GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,\r
756 DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,\r
757 CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,\r
758 IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,\r
759 AbortOpcode = NVME_ADMIN_ABORT_CMD,\r
760 SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,\r
761 GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,\r
762 AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,\r
763 NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,\r
764 FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,\r
765 FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,\r
766 NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,\r
767 FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,\r
768 SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,\r
769 SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD\r
770} NVME_ADMIN_COMMAND_OPCODE;\r
771\r
772//\r
773// Controller or Namespace Structure (CNS) field\r
774// (ref. spec. v1.1 figure 82).\r
775//\r
776typedef enum {\r
777IdentifyNamespaceCns = 0x0,\r
778IdentifyControllerCns = 0x1,\r
779IdentifyActiveNsListCns = 0x2\r
780} NVME_ADMIN_IDENTIFY_CNS;\r
781\r
782//\r
783// Commit Action\r
784// (ref. spec. 1.1 figure 60).\r
785//\r
786typedef enum {\r
787 ActivateActionReplace = 0x0,\r
788 ActivateActionReplaceActivate = 0x1,\r
789 ActivateActionActivate = 0x2\r
790} NVME_FW_ACTIVATE_ACTION;\r
791\r
792//\r
793// Firmware Slot\r
794// (ref. spec. 1.1 Figure 60).\r
795//\r
796typedef enum {\r
797 FirmwareSlotCtrlChooses = 0x0,\r
798 FirmwareSlot1 = 0x1,\r
799 FirmwareSlot2 = 0x2,\r
800 FirmwareSlot3 = 0x3,\r
801 FirmwareSlot4 = 0x4,\r
802 FirmwareSlot5 = 0x5,\r
803 FirmwareSlot6 = 0x6,\r
804 FirmwareSlot7 = 0x7\r
805} NVME_FW_ACTIVATE_SLOT;\r
806\r
807//\r
808// Get Log Page ? Log Page Identifiers\r
809// (ref. spec. v1.1 Figure 73).\r
810//\r
811typedef enum {\r
812 ErrorInfoLogID = LID_ERROR_INFO,\r
813 SmartHealthInfoLogID = LID_SMART_INFO,\r
814 FirmwareSlotInfoLogID = LID_FW_SLOT_INFO\r
815} NVME_LOG_ID;\r
816\r
817//\r
818// Get Log Page ? Firmware Slot Information Log\r
819// (ref. spec. v1.1 Figure 77).\r
820//\r
821typedef struct {\r
822 //\r
823 // Indicates the firmware slot from which the actively running firmware revision was loaded.\r
824 //\r
825 UINT8 ActivelyRunningFwSlot:3;\r
826 UINT8 :1;\r
827 //\r
828 // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.\r
829 //\r
830 UINT8 NextActiveFwSlot:3;\r
831 UINT8 :1;\r
832} NVME_ACTIVE_FW_INFO;\r
833\r
834//\r
835// Get Log Page ? Firmware Slot Information Log\r
836// (ref. spec. v1.1 Figure 77).\r
837//\r
838typedef struct {\r
839 //\r
840 // Specifies information about the active firmware revision.\r
841 //s\r
842 NVME_ACTIVE_FW_INFO ActiveFwInfo;\r
843 UINT8 Reserved1[7];\r
844 //\r
845 // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.\r
846 //\r
847 CHAR8 FwRevisionSlot[7][8];\r
848 UINT8 Reserved2[448];\r
849} NVME_FW_SLOT_INFO_LOG;\r
850\r
851//\r
852// SMART / Health Information (Log Identifier 02h)\r
853// (ref. spec. v1.1 5.10.1.2)\r
854//\r
855typedef struct {\r
856 //\r
857 // This field indicates critical warnings for the state of the controller.\r
858 //\r
859 UINT8 CriticalWarningAvailableSpare:1;\r
860 UINT8 CriticalWarningTemperature:1;\r
861 UINT8 CriticalWarningReliability:1;\r
862 UINT8 CriticalWarningMediaReadOnly:1;\r
863 UINT8 CriticalWarningVolatileBackup:1;\r
864 UINT8 CriticalWarningReserved:3;\r
865 //\r
866 // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.\r
867 //\r
868 UINT16 CompositeTemp;\r
869 //\r
870 // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.\r
871 //\r
872 UINT8 AvailableSpare;\r
873 //\r
874 // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).\r
875 //\r
876 UINT8 AvailableSpareThreshold;\r
877 //\r
878 // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).\r
879 //\r
880 UINT8 PercentageUsed;\r
881 UINT8 Reserved1[26];\r
882 //\r
883 // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.\r
884 //\r
885 UINT8 DataUnitsRead[16];\r
886 //\r
887 // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.\r
888 //\r
889 UINT8 DataUnitsWritten[16];\r
890 //\r
891 // Contains the number of read commands completed by the controller.\r
892 //\r
893 UINT8 HostReadCommands[16];\r
894 //\r
895 // Contains the number of write commands completed by the controller.\r
896 //\r
897 UINT8 HostWriteCommands[16];\r
898 //\r
899 // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.\r
900 //\r
901 UINT8 ControllerBusyTime[16];\r
902 //\r
903 // Contains the number of power cycles.\r
904 //\r
905 UINT8 PowerCycles[16];\r
906 //\r
907 // Contains the number of power-on hours.\r
908 //\r
909 UINT8 PowerOnHours[16];\r
910 //\r
911 // Contains the number of unsafe shutdowns.\r
912 //\r
913 UINT8 UnsafeShutdowns[16];\r
914 //\r
915 // Contains the number of occurrences where the controller detected an unrecovered data integrity error.\r
916 //\r
917 UINT8 MediaAndDataIntegrityErrors[16];\r
918 //\r
919 // Contains the number of Error Information log entries over the life of the controller.\r
920 //\r
921 UINT8 NumberErrorInformationLogEntries[16];\r
922 //\r
923 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
924 //\r
925 UINT32 WarningCompositeTemperatureTime;\r
926 //\r
927 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
928 //\r
929 UINT32 CriticalCompositeTemperatureTime;\r
930 //\r
931 // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.\r
932 //\r
933 UINT16 TemperatureSensor[8];\r
934 UINT8 Reserved2[296];\r
935} NVME_SMART_HEALTH_INFO_LOG;\r
936\r
937#pragma pack()\r
938\r
939#endif\r
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