]> git.proxmox.com Git - mirror_edk2.git/blame - MdePkg/Include/IndustryStandard/Pci22.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h
CommitLineData
a7ed1e2e 1/** @file\r
2 Support for PCI 2.2 standard.\r
3\r
bc14bdb3 4 This file includes the definitions in the following specifications,\r
427987f5 5 PCI Local Bus Specification, 2.2\r
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
bc14bdb3 7 PC Card Standard, 8.0\r
b219e2cd 8 PCI Power Management Interface Specification, Revision 1.2\r
bc14bdb3 9\r
9095d37b 10 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
3362c5f1 11 Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
9344f092 12 SPDX-License-Identifier: BSD-2-Clause-Patent\r
a7ed1e2e 13\r
a7ed1e2e 14**/\r
15\r
42eedea9 16#ifndef _PCI22_H_\r
17#define _PCI22_H_\r
a7ed1e2e 18\r
a7ed1e2e 19#define PCI_MAX_BUS 255\r
a7ed1e2e 20#define PCI_MAX_DEVICE 31\r
21#define PCI_MAX_FUNC 7\r
22\r
766f4bc1 23#pragma pack(1)\r
427987f5 24\r
25///\r
26/// Common header region in PCI Configuration Space\r
27/// Section 6.1, PCI Local Bus Specification, 2.2\r
28///\r
a7ed1e2e 29typedef struct {\r
2f88bd3a
MK		 30 UINT16 VendorId;\r
31 UINT16 DeviceId;\r
32 UINT16 Command;\r
33 UINT16 Status;\r
34 UINT8 RevisionID;\r
35 UINT8 ClassCode[3];\r
36 UINT8 CacheLineSize;\r
37 UINT8 LatencyTimer;\r
38 UINT8 HeaderType;\r
39 UINT8 BIST;\r
a7ed1e2e 40} PCI_DEVICE_INDEPENDENT_REGION;\r
41\r
427987f5 42///\r
43/// PCI Device header region in PCI Configuration Space\r
44/// Section 6.1, PCI Local Bus Specification, 2.2\r
45///\r
a7ed1e2e 46typedef struct {\r
2f88bd3a
MK		 47 UINT32 Bar[6];\r
48 UINT32 CISPtr;\r
49 UINT16 SubsystemVendorID;\r
50 UINT16 SubsystemID;\r
51 UINT32 ExpansionRomBar;\r
52 UINT8 CapabilityPtr;\r
53 UINT8 Reserved1[3];\r
54 UINT32 Reserved2;\r
55 UINT8 InterruptLine;\r
56 UINT8 InterruptPin;\r
57 UINT8 MinGnt;\r
58 UINT8 MaxLat;\r
a7ed1e2e 59} PCI_DEVICE_HEADER_TYPE_REGION;\r
60\r
427987f5 61///\r
62/// PCI Device Configuration Space\r
63/// Section 6.1, PCI Local Bus Specification, 2.2\r
64///\r
a7ed1e2e 65typedef struct {\r
2f88bd3a
MK		 66 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
67 PCI_DEVICE_HEADER_TYPE_REGION Device;\r
a7ed1e2e 68} PCI_TYPE00;\r
69\r
bc14bdb3 70///\r
427987f5 71/// PCI-PCI Bridge header region in PCI Configuration Space\r
72/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
bc14bdb3 73///\r
a7ed1e2e 74typedef struct {\r
2f88bd3a
MK		 75 UINT32 Bar[2];\r
76 UINT8 PrimaryBus;\r
77 UINT8 SecondaryBus;\r
78 UINT8 SubordinateBus;\r
79 UINT8 SecondaryLatencyTimer;\r
80 UINT8 IoBase;\r
81 UINT8 IoLimit;\r
82 UINT16 SecondaryStatus;\r
83 UINT16 MemoryBase;\r
84 UINT16 MemoryLimit;\r
85 UINT16 PrefetchableMemoryBase;\r
86 UINT16 PrefetchableMemoryLimit;\r
87 UINT32 PrefetchableBaseUpper32;\r
88 UINT32 PrefetchableLimitUpper32;\r
89 UINT16 IoBaseUpper16;\r
90 UINT16 IoLimitUpper16;\r
91 UINT8 CapabilityPtr;\r
92 UINT8 Reserved[3];\r
93 UINT32 ExpansionRomBAR;\r
94 UINT8 InterruptLine;\r
95 UINT8 InterruptPin;\r
96 UINT16 BridgeControl;\r
a7ed1e2e 97} PCI_BRIDGE_CONTROL_REGISTER;\r
98\r
427987f5 99///\r
100/// PCI-to-PCI Bridge Configuration Space\r
101/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
102///\r
a7ed1e2e 103typedef struct {\r
2f88bd3a
MK		 104 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
105 PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
a7ed1e2e 106} PCI_TYPE01;\r
107\r
108typedef union {\r
2f88bd3a
MK		 109 PCI_TYPE00 Device;\r
110 PCI_TYPE01 Bridge;\r
a7ed1e2e 111} PCI_TYPE_GENERIC;\r
112\r
9095d37b 113///\r
b219e2cd 114/// CardBus Controller Configuration Space,\r
427987f5 115/// Section 4.5.1, PC Card Standard. 8.0\r
bc14bdb3 116///\r
a7ed1e2e 117typedef struct {\r
2f88bd3a
MK		 118 UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base\r
119 UINT8 Cap_Ptr;\r
120 UINT8 Reserved;\r
121 UINT16 SecondaryStatus; ///< Secondary Status\r
122 UINT8 PciBusNumber; ///< PCI Bus Number\r
123 UINT8 CardBusBusNumber; ///< CardBus Bus Number\r
124 UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r
125 UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r
126 UINT32 MemoryBase0; ///< Memory Base Register 0\r
127 UINT32 MemoryLimit0; ///< Memory Limit Register 0\r
128 UINT32 MemoryBase1;\r
129 UINT32 MemoryLimit1;\r
130 UINT32 IoBase0;\r
131 UINT32 IoLimit0; ///< I/O Base Register 0\r
132 UINT32 IoBase1; ///< I/O Limit Register 0\r
133 UINT32 IoLimit1;\r
134 UINT8 InterruptLine; ///< Interrupt Line\r
135 UINT8 InterruptPin; ///< Interrupt Pin\r
136 UINT16 BridgeControl; ///< Bridge Control\r
a7ed1e2e 137} PCI_CARDBUS_CONTROL_REGISTER;\r
138\r
a2461f6b 139//\r
140// Definitions of PCI class bytes and manipulation macros.\r
141//\r
2f88bd3a
MK		 142#define PCI_CLASS_OLD 0x00\r
143#define PCI_CLASS_OLD_OTHER 0x00\r
144#define PCI_CLASS_OLD_VGA 0x01\r
145\r
146#define PCI_CLASS_MASS_STORAGE 0x01\r
147#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
148#define PCI_CLASS_MASS_STORAGE_IDE 0x01\r
149#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
150#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
151#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
152#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
153\r
154#define PCI_CLASS_NETWORK 0x02\r
155#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
156#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
157#define PCI_CLASS_NETWORK_FDDI 0x02\r
158#define PCI_CLASS_NETWORK_ATM 0x03\r
159#define PCI_CLASS_NETWORK_ISDN 0x04\r
160#define PCI_CLASS_NETWORK_OTHER 0x80\r
161\r
162#define PCI_CLASS_DISPLAY 0x03\r
163#define PCI_CLASS_DISPLAY_VGA 0x00\r
164#define PCI_IF_VGA_VGA 0x00\r
165#define PCI_IF_VGA_8514 0x01\r
166#define PCI_CLASS_DISPLAY_XGA 0x01\r
167#define PCI_CLASS_DISPLAY_3D 0x02\r
168#define PCI_CLASS_DISPLAY_OTHER 0x80\r
169\r
170#define PCI_CLASS_MEDIA 0x04\r
171#define PCI_CLASS_MEDIA_VIDEO 0x00\r
172#define PCI_CLASS_MEDIA_AUDIO 0x01\r
173#define PCI_CLASS_MEDIA_TELEPHONE 0x02\r
174#define PCI_CLASS_MEDIA_OTHER 0x80\r
175\r
176#define PCI_CLASS_MEMORY_CONTROLLER 0x05\r
177#define PCI_CLASS_MEMORY_RAM 0x00\r
178#define PCI_CLASS_MEMORY_FLASH 0x01\r
179#define PCI_CLASS_MEMORY_OTHER 0x80\r
180\r
181#define PCI_CLASS_BRIDGE 0x06\r
182#define PCI_CLASS_BRIDGE_HOST 0x00\r
183#define PCI_CLASS_BRIDGE_ISA 0x01\r
184#define PCI_CLASS_BRIDGE_EISA 0x02\r
185#define PCI_CLASS_BRIDGE_MCA 0x03\r
186#define PCI_CLASS_BRIDGE_P2P 0x04\r
187#define PCI_IF_BRIDGE_P2P 0x00\r
188#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
189#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
190#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
191#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
192#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
193#define PCI_CLASS_BRIDGE_OTHER 0x80\r
194#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
195\r
196#define PCI_CLASS_SCC 0x07///< Simple communications controllers\r
197#define PCI_SUBCLASS_SERIAL 0x00\r
198#define PCI_IF_GENERIC_XT 0x00\r
199#define PCI_IF_16450 0x01\r
200#define PCI_IF_16550 0x02\r
201#define PCI_IF_16650 0x03\r
202#define PCI_IF_16750 0x04\r
203#define PCI_IF_16850 0x05\r
204#define PCI_IF_16950 0x06\r
205#define PCI_SUBCLASS_PARALLEL 0x01\r
206#define PCI_IF_PARALLEL_PORT 0x00\r
207#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
208#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
209#define PCI_IF_1284_CONTROLLER 0x03\r
210#define PCI_IF_1284_DEVICE 0xFE\r
211#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
212#define PCI_SUBCLASS_MODEM 0x03\r
213#define PCI_IF_GENERIC_MODEM 0x00\r
214#define PCI_IF_16450_MODEM 0x01\r
215#define PCI_IF_16550_MODEM 0x02\r
216#define PCI_IF_16650_MODEM 0x03\r
217#define PCI_IF_16750_MODEM 0x04\r
218#define PCI_SUBCLASS_SCC_OTHER 0x80\r
219\r
220#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
221#define PCI_SUBCLASS_PIC 0x00\r
222#define PCI_IF_8259_PIC 0x00\r
223#define PCI_IF_ISA_PIC 0x01\r
224#define PCI_IF_EISA_PIC 0x02\r
225#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\r
226#define PCI_IF_APIC_CONTROLLER2 0x20\r
227#define PCI_SUBCLASS_DMA 0x01\r
228#define PCI_IF_8237_DMA 0x00\r
229#define PCI_IF_ISA_DMA 0x01\r
230#define PCI_IF_EISA_DMA 0x02\r
231#define PCI_SUBCLASS_TIMER 0x02\r
232#define PCI_IF_8254_TIMER 0x00\r
233#define PCI_IF_ISA_TIMER 0x01\r
234#define PCI_IF_EISA_TIMER 0x02\r
235#define PCI_SUBCLASS_RTC 0x03\r
236#define PCI_IF_GENERIC_RTC 0x00\r
237#define PCI_IF_ISA_RTC 0x01\r
238#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
239#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
240\r
241#define PCI_CLASS_INPUT_DEVICE 0x09\r
242#define PCI_SUBCLASS_KEYBOARD 0x00\r
243#define PCI_SUBCLASS_PEN 0x01\r
244#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
245#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
246#define PCI_SUBCLASS_GAMEPORT 0x04\r
247#define PCI_IF_GAMEPORT 0x00\r
248#define PCI_IF_GAMEPORT1 0x10\r
249#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
250\r
251#define PCI_CLASS_DOCKING_STATION 0x0A\r
826a66d4
RN		 252#define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r
253#define PCI_SUBCLASS_DOCKING_OTHER 0x80\r
a7ed1e2e 254\r
2f88bd3a
MK		 255#define PCI_CLASS_PROCESSOR 0x0B\r
256#define PCI_SUBCLASS_PROC_386 0x00\r
257#define PCI_SUBCLASS_PROC_486 0x01\r
258#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
259#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
260#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
261#define PCI_SUBCLASS_PROC_MIPS 0x30\r
262#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r
263\r
264#define PCI_CLASS_SERIAL 0x0C\r
265#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
266#define PCI_IF_1394 0x00\r
267#define PCI_IF_1394_OPEN_HCI 0x10\r
268#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
269#define PCI_CLASS_SERIAL_SSA 0x02\r
270#define PCI_CLASS_SERIAL_USB 0x03\r
271#define PCI_IF_UHCI 0x00\r
272#define PCI_IF_OHCI 0x10\r
273#define PCI_IF_USB_OTHER 0x80\r
274#define PCI_IF_USB_DEVICE 0xFE\r
275#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
276#define PCI_CLASS_SERIAL_SMB 0x05\r
277\r
278#define PCI_CLASS_WIRELESS 0x0D\r
279#define PCI_SUBCLASS_IRDA 0x00\r
280#define PCI_SUBCLASS_IR 0x01\r
281#define PCI_SUBCLASS_RF 0x10\r
282#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
283\r
284#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
285\r
286#define PCI_CLASS_SATELLITE 0x0F\r
287#define PCI_SUBCLASS_TV 0x01\r
288#define PCI_SUBCLASS_AUDIO 0x02\r
289#define PCI_SUBCLASS_VOICE 0x03\r
290#define PCI_SUBCLASS_DATA 0x04\r
291\r
292#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
293#define PCI_SUBCLASS_NET_COMPUT 0x00\r
294#define PCI_SUBCLASS_ENTERTAINMENT 0x10\r
295#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
296\r
297#define PCI_CLASS_DPIO 0x11\r
298#define PCI_SUBCLASS_DPIO 0x00\r
299#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
a7ed1e2e 300\r
9095d37b 301/**\r
1833218d 302 Macro that checks whether the Base Class code of device matched.\r
303\r
304 @param _p Specified device.\r
305 @param c Base Class code needs matching.\r
306\r
307 @retval TRUE Base Class code matches the specified device.\r
9095d37b 308 @retval FALSE Base Class code doesn't match the specified device.\r
1833218d 309\r
310**/\r
2f88bd3a
MK		 311#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
312\r
9095d37b 313/**\r
1833218d 314 Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
315\r
316 @param _p Specified device.\r
317 @param c Base Class code needs matching.\r
318 @param s Sub-Class code needs matching.\r
319\r
320 @retval TRUE Base Class code and Sub-Class code match the specified device.\r
9095d37b 321 @retval FALSE Base Class code and Sub-Class code don't match the specified device.\r
1833218d 322\r
323**/\r
2f88bd3a
MK		 324#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
325\r
9095d37b 326/**\r
1833218d 327 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
328\r
329 @param _p Specified device.\r
330 @param c Base Class code needs matching.\r
331 @param s Sub-Class code needs matching.\r
332 @param p Interface code needs matching.\r
333\r
334 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r
9095d37b 335 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.\r
1833218d 336\r
337**/\r
2f88bd3a 338#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
a7ed1e2e 339\r
9095d37b 340/**\r
1833218d 341 Macro that checks whether device is a display controller.\r
342\r
343 @param _p Specified device.\r
344\r
345 @retval TRUE Device is a display controller.\r
346 @retval FALSE Device is not a display controller.\r
347\r
348**/\r
2f88bd3a
MK		 349#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
350\r
9095d37b 351/**\r
1833218d 352 Macro that checks whether device is a VGA-compatible controller.\r
353\r
354 @param _p Specified device.\r
355\r
356 @retval TRUE Device is a VGA-compatible controller.\r
357 @retval FALSE Device is not a VGA-compatible controller.\r
358\r
359**/\r
2f88bd3a
MK		 360#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
361\r
9095d37b 362/**\r
1833218d 363 Macro that checks whether device is an 8514-compatible controller.\r
364\r
365 @param _p Specified device.\r
366\r
367 @retval TRUE Device is an 8514-compatible controller.\r
368 @retval FALSE Device is not an 8514-compatible controller.\r
369\r
370**/\r
2f88bd3a
MK		 371#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
372\r
9095d37b 373/**\r
1833218d 374 Macro that checks whether device is built before the Class Code field was defined.\r
375\r
376 @param _p Specified device.\r
377\r
378 @retval TRUE Device is an old device.\r
379 @retval FALSE Device is not an old device.\r
380\r
381**/\r
2f88bd3a
MK		 382#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
383\r
9095d37b 384/**\r
1833218d 385 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
386\r
387 @param _p Specified device.\r
388\r
389 @retval TRUE Device is an old VGA-compatible device.\r
390 @retval FALSE Device is not an old VGA-compatible device.\r
391\r
392**/\r
2f88bd3a
MK		 393#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
394\r
9095d37b 395/**\r
1833218d 396 Macro that checks whether device is an IDE controller.\r
397\r
398 @param _p Specified device.\r
399\r
400 @retval TRUE Device is an IDE controller.\r
401 @retval FALSE Device is not an IDE controller.\r
402\r
403**/\r
2f88bd3a
MK		 404#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
405\r
9095d37b 406/**\r
1833218d 407 Macro that checks whether device is a SCSI bus controller.\r
408\r
409 @param _p Specified device.\r
410\r
411 @retval TRUE Device is a SCSI bus controller.\r
412 @retval FALSE Device is not a SCSI bus controller.\r
413\r
414**/\r
2f88bd3a
MK		 415#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
416\r
9095d37b 417/**\r
1833218d 418 Macro that checks whether device is a RAID controller.\r
419\r
420 @param _p Specified device.\r
421\r
422 @retval TRUE Device is a RAID controller.\r
423 @retval FALSE Device is not a RAID controller.\r
424\r
425**/\r
2f88bd3a
MK		 426#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
427\r
9095d37b 428/**\r
1833218d 429 Macro that checks whether device is an ISA bridge.\r
430\r
431 @param _p Specified device.\r
432\r
433 @retval TRUE Device is an ISA bridge.\r
434 @retval FALSE Device is not an ISA bridge.\r
435\r
436**/\r
2f88bd3a
MK		 437#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
438\r
9095d37b 439/**\r
1833218d 440 Macro that checks whether device is a PCI-to-PCI bridge.\r
441\r
442 @param _p Specified device.\r
443\r
444 @retval TRUE Device is a PCI-to-PCI bridge.\r
445 @retval FALSE Device is not a PCI-to-PCI bridge.\r
446\r
447**/\r
2f88bd3a
MK		 448#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
449\r
9095d37b 450/**\r
1833218d 451 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
452\r
453 @param _p Specified device.\r
454\r
455 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r
456 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r
457\r
458**/\r
2f88bd3a
MK		 459#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
460\r
9095d37b 461/**\r
1833218d 462 Macro that checks whether device is a 16550-compatible serial controller.\r
463\r
464 @param _p Specified device.\r
465\r
466 @retval TRUE Device is a 16550-compatible serial controller.\r
467 @retval FALSE Device is not a 16550-compatible serial controller.\r
468\r
469**/\r
2f88bd3a
MK		 470#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
471\r
9095d37b 472/**\r
1833218d 473 Macro that checks whether device is a Universal Serial Bus controller.\r
474\r
475 @param _p Specified device.\r
476\r
477 @retval TRUE Device is a Universal Serial Bus controller.\r
478 @retval FALSE Device is not a Universal Serial Bus controller.\r
479\r
480**/\r
2f88bd3a 481#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
a7ed1e2e 482\r
bc14bdb3 483//\r
9095d37b 484// the definition of Header Type\r
bc14bdb3 485//\r
2f88bd3a
MK		 486#define HEADER_TYPE_DEVICE 0x00\r
487#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
488#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
489#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
bc14bdb3 490//\r
491// Mask of Header type\r
492//\r
2f88bd3a
MK		 493#define HEADER_LAYOUT_CODE 0x7f\r
494\r
9095d37b 495/**\r
1833218d 496 Macro that checks whether device is a PCI-PCI bridge.\r
497\r
498 @param _p Specified device.\r
499\r
500 @retval TRUE Device is a PCI-PCI bridge.\r
501 @retval FALSE Device is not a PCI-PCI bridge.\r
a7ed1e2e 502\r
1833218d 503**/\r
2f88bd3a
MK		 504#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
505\r
9095d37b 506/**\r
1833218d 507 Macro that checks whether device is a CardBus bridge.\r
508\r
509 @param _p Specified device.\r
510\r
511 @retval TRUE Device is a CardBus bridge.\r
512 @retval FALSE Device is not a CardBus bridge.\r
513\r
514**/\r
2f88bd3a
MK		 515#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
516\r
9095d37b 517/**\r
1833218d 518 Macro that checks whether device is a multiple functions device.\r
519\r
520 @param _p Specified device.\r
521\r
522 @retval TRUE Device is a multiple functions device.\r
523 @retval FALSE Device is not a multiple functions device.\r
524\r
525**/\r
2f88bd3a 526#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
a7ed1e2e 527\r
bc14bdb3 528///\r
b219e2cd 529/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,\r
bc14bdb3 530///\r
2f88bd3a
MK		 531#define PCI_BRIDGE_ROMBAR 0x38\r
532\r
533#define PCI_MAX_BAR 0x0006\r
534#define PCI_MAX_CONFIG_OFFSET 0x0100\r
535\r
536#define PCI_VENDOR_ID_OFFSET 0x00\r
537#define PCI_DEVICE_ID_OFFSET 0x02\r
538#define PCI_COMMAND_OFFSET 0x04\r
539#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
540#define PCI_REVISION_ID_OFFSET 0x08\r
541#define PCI_CLASSCODE_OFFSET 0x09\r
542#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
543#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
544#define PCI_HEADER_TYPE_OFFSET 0x0E\r
545#define PCI_BIST_OFFSET 0x0F\r
546#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
547#define PCI_CARDBUS_CIS_OFFSET 0x28\r
548#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r
549#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
550#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r
551#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
552#define PCI_EXPANSION_ROM_BASE 0x30\r
553#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
554#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r
555#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r
556#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
557#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
a7ed1e2e 558\r
a2461f6b 559//\r
560// defined in PCI-to-PCI Bridge Architecture Specification\r
561//\r
9095d37b
LG		 562#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18\r
563#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\r
564#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\r
0e8768b6 565#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r
9095d37b
LG		 566#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r
567#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r
a7ed1e2e 568\r
bc14bdb3 569///\r
570/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
571///\r
2f88bd3a 572#define PCI_INT_LINE_UNKNOWN 0xFF\r
a7ed1e2e 573\r
1833218d 574///\r
575/// PCI Access Data Format\r
576///\r
a7ed1e2e 577typedef union {\r
578 struct {\r
2f88bd3a
MK		 579 UINT32 Reg : 8;\r
580 UINT32 Func : 3;\r
581 UINT32 Dev : 5;\r
582 UINT32 Bus : 8;\r
583 UINT32 Reserved : 7;\r
584 UINT32 Enable : 1;\r
a7ed1e2e 585 } Bits;\r
2f88bd3a 586 UINT32 Uint32;\r
a7ed1e2e 587} PCI_CONFIG_ACCESS_CF8;\r
588\r
766f4bc1 589#pragma pack()\r
590\r
2f88bd3a
MK		 591#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
592#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
593#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
594#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r
595#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r
596#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r
597#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r
598#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r
599#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
600#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
a7ed1e2e 601\r
a2461f6b 602//\r
603// defined in PCI-to-PCI Bridge Architecture Specification\r
604//\r
bc14bdb3 605#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r
606#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r
607#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r
608#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r
609#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r
610#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r
611#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r
612#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r
613#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r
614#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r
615#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r
616#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r
617\r
a2461f6b 618//\r
619// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
620//\r
2f88bd3a
MK		 621#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
622#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
623#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
624#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r
a7ed1e2e 625\r
626//\r
627// Following are the PCI status control bit\r
628//\r
2f88bd3a
MK		 629#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r
630#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r
631#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r
632#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r
a7ed1e2e 633\r
bc14bdb3 634///\r
635/// defined in PC Card Standard\r
636///\r
2f88bd3a 637#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
a7ed1e2e 638\r
766f4bc1 639#pragma pack(1)\r
a7ed1e2e 640//\r
641// PCI Capability List IDs and records\r
642//\r
2f88bd3a
MK		 643#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
644#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
645#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
646#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
647#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
648#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
649#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r
a2461f6b 650\r
427987f5 651///\r
652/// Capabilities List Header\r
653/// Section 6.7, PCI Local Bus Specification, 2.2\r
654///\r
a7ed1e2e 655typedef struct {\r
2f88bd3a
MK		 656 UINT8 CapabilityID;\r
657 UINT8 NextItemPtr;\r
a7ed1e2e 658} EFI_PCI_CAPABILITY_HDR;\r
659\r
f0aa06e3
SEHM		 660///\r
661/// PMC - Power Management Capabilities\r
b219e2cd 662/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2\r
f0aa06e3
SEHM		 663///\r
664typedef union {\r
665 struct {\r
2f88bd3a
MK		 666 UINT16 Version : 3;\r
667 UINT16 PmeClock : 1;\r
668 UINT16 Reserved : 1;\r
669 UINT16 DeviceSpecificInitialization : 1;\r
670 UINT16 AuxCurrent : 3;\r
671 UINT16 D1Support : 1;\r
672 UINT16 D2Support : 1;\r
673 UINT16 PmeSupport : 5;\r
f0aa06e3 674 } Bits;\r
2f88bd3a 675 UINT16 Data;\r
f0aa06e3
SEHM		 676} EFI_PCI_PMC;\r
677\r
2f88bd3a 678#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r
f0aa06e3
SEHM		 679\r
680///\r
681/// PMCSR - Power Management Control/Status\r
b219e2cd 682/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2\r
f0aa06e3
SEHM		 683///\r
684typedef union {\r
685 struct {\r
2f88bd3a
MK		 686 UINT16 PowerState : 2;\r
687 UINT16 ReservedForPciExpress : 1;\r
688 UINT16 NoSoftReset : 1;\r
689 UINT16 Reserved : 4;\r
690 UINT16 PmeEnable : 1;\r
691 UINT16 DataSelect : 4;\r
692 UINT16 DataScale : 2;\r
693 UINT16 PmeStatus : 1;\r
f0aa06e3 694 } Bits;\r
2f88bd3a 695 UINT16 Data;\r
f0aa06e3
SEHM		 696} EFI_PCI_PMCSR;\r
697\r
2f88bd3a
MK		 698#define PCI_POWER_STATE_D0 0\r
699#define PCI_POWER_STATE_D1 1\r
700#define PCI_POWER_STATE_D2 2\r
701#define PCI_POWER_STATE_D3_HOT 3\r
cbedba86
RN		 702\r
703///\r
704/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
b219e2cd 705/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2\r
cbedba86
RN		 706///\r
707typedef union {\r
708 struct {\r
2f88bd3a
MK		 709 UINT8 Reserved : 6;\r
710 UINT8 B2B3 : 1;\r
711 UINT8 BusPowerClockControl : 1;\r
cbedba86 712 } Bits;\r
2f88bd3a 713 UINT8 Uint8;\r
cbedba86
RN		 714} EFI_PCI_PMCSR_BSE;\r
715\r
716///\r
717/// Power Management Register Block Definition\r
b219e2cd 718/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2\r
cbedba86
RN		 719///\r
720typedef struct {\r
2f88bd3a
MK		 721 EFI_PCI_CAPABILITY_HDR Hdr;\r
722 EFI_PCI_PMC PMC;\r
723 EFI_PCI_PMCSR PMCSR;\r
724 EFI_PCI_PMCSR_BSE BridgeExtention;\r
725 UINT8 Data;\r
cbedba86
RN		 726} EFI_PCI_CAPABILITY_PMI;\r
727\r
1bc5d021 728///\r
427987f5 729/// A.G.P Capability\r
730/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
1bc5d021 731///\r
a7ed1e2e 732typedef struct {\r
2f88bd3a
MK		 733 EFI_PCI_CAPABILITY_HDR Hdr;\r
734 UINT8 Rev;\r
735 UINT8 Reserved;\r
736 UINT32 Status;\r
737 UINT32 Command;\r
a7ed1e2e 738} EFI_PCI_CAPABILITY_AGP;\r
739\r
1bc5d021 740///\r
427987f5 741/// VPD Capability Structure\r
742/// Appendix I, PCI Local Bus Specification, 2.2\r
1bc5d021 743///\r
a7ed1e2e 744typedef struct {\r
2f88bd3a
MK		 745 EFI_PCI_CAPABILITY_HDR Hdr;\r
746 UINT16 AddrReg;\r
747 UINT32 DataReg;\r
a7ed1e2e 748} EFI_PCI_CAPABILITY_VPD;\r
749\r
1bc5d021 750///\r
427987f5 751/// Slot Numbering Capabilities Register\r
b219e2cd 752/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
1bc5d021 753///\r
a7ed1e2e 754typedef struct {\r
2f88bd3a
MK		 755 EFI_PCI_CAPABILITY_HDR Hdr;\r
756 UINT8 ExpnsSlotReg;\r
757 UINT8 ChassisNo;\r
a7ed1e2e 758} EFI_PCI_CAPABILITY_SLOTID;\r
759\r
1bc5d021 760///\r
427987f5 761/// Message Capability Structure for 32-bit Message Address\r
762/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
1bc5d021 763///\r
a7ed1e2e 764typedef struct {\r
2f88bd3a
MK		 765 EFI_PCI_CAPABILITY_HDR Hdr;\r
766 UINT16 MsgCtrlReg;\r
767 UINT32 MsgAddrReg;\r
768 UINT16 MsgDataReg;\r
a7ed1e2e 769} EFI_PCI_CAPABILITY_MSI32;\r
770\r
427987f5 771///\r
772/// Message Capability Structure for 64-bit Message Address\r
773/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
774///\r
a7ed1e2e 775typedef struct {\r
2f88bd3a
MK		 776 EFI_PCI_CAPABILITY_HDR Hdr;\r
777 UINT16 MsgCtrlReg;\r
778 UINT32 MsgAddrRegLsdw;\r
779 UINT32 MsgAddrRegMsdw;\r
780 UINT16 MsgDataReg;\r
a7ed1e2e 781} EFI_PCI_CAPABILITY_MSI64;\r
782\r
1bc5d021 783///\r
9095d37b 784/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,\r
427987f5 785/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
1bc5d021 786///\r
a7ed1e2e 787typedef struct {\r
2f88bd3a 788 EFI_PCI_CAPABILITY_HDR Hdr;\r
1bc5d021 789 ///\r
790 /// not finished - fields need to go here\r
791 ///\r
a7ed1e2e 792} EFI_PCI_CAPABILITY_HOTPLUG;\r
793\r
2f88bd3a
MK		 794#define PCI_BAR_IDX0 0x00\r
795#define PCI_BAR_IDX1 0x01\r
796#define PCI_BAR_IDX2 0x02\r
797#define PCI_BAR_IDX3 0x03\r
798#define PCI_BAR_IDX4 0x04\r
799#define PCI_BAR_IDX5 0x05\r
a7ed1e2e 800\r
bc14bdb3 801///\r
802/// EFI PCI Option ROM definitions\r
9095d37b 803///\r
2f88bd3a
MK		 804#define EFI_ROOT_BRIDGE_LIST 'eprb'\r
805#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
afcf4907 806\r
2f88bd3a
MK		 807#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
808#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
809#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
810#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
bc14bdb3 811\r
427987f5 812///\r
813/// Standard PCI Expansion ROM Header\r
814/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
815///\r
bc14bdb3 816typedef struct {\r
2f88bd3a
MK		 817 UINT16 Signature; ///< 0xaa55\r
818 UINT8 Reserved[0x16];\r
819 UINT16 PcirOffset;\r
bc14bdb3 820} PCI_EXPANSION_ROM_HEADER;\r
821\r
427987f5 822///\r
823/// Legacy ROM Header Extensions\r
824/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r
825///\r
bc14bdb3 826typedef struct {\r
2f88bd3a
MK		 827 UINT16 Signature; ///< 0xaa55\r
828 UINT8 Size512;\r
829 UINT8 InitEntryPoint[3];\r
830 UINT8 Reserved[0x12];\r
831 UINT16 PcirOffset;\r
bc14bdb3 832} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
833\r
427987f5 834///\r
835/// PCI Data Structure Format\r
836/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r
837///\r
bc14bdb3 838typedef struct {\r
2f88bd3a
MK		 839 UINT32 Signature; ///< "PCIR"\r
840 UINT16 VendorId;\r
841 UINT16 DeviceId;\r
842 UINT16 Reserved0;\r
843 UINT16 Length;\r
844 UINT8 Revision;\r
845 UINT8 ClassCode[3];\r
846 UINT16 ImageLength;\r
847 UINT16 CodeRevision;\r
848 UINT8 CodeType;\r
849 UINT8 Indicator;\r
850 UINT16 Reserved1;\r
bc14bdb3 851} PCI_DATA_STRUCTURE;\r
852\r
853///\r
427987f5 854/// EFI PCI Expansion ROM Header\r
855/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
bc14bdb3 856///\r
afcf4907 857typedef struct {\r
2f88bd3a
MK		 858 UINT16 Signature; ///< 0xaa55\r
859 UINT16 InitializationSize;\r
860 UINT32 EfiSignature; ///< 0x0EF1\r
861 UINT16 EfiSubsystem;\r
862 UINT16 EfiMachineType;\r
863 UINT16 CompressionType;\r
864 UINT8 Reserved[8];\r
865 UINT16 EfiImageHeaderOffset;\r
866 UINT16 PcirOffset;\r
afcf4907 867} EFI_PCI_EXPANSION_ROM_HEADER;\r
868\r
869typedef union {\r
2f88bd3a
MK		 870 UINT8 *Raw;\r
871 PCI_EXPANSION_ROM_HEADER *Generic;\r
872 EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
873 EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
afcf4907 874} EFI_PCI_ROM_HEADER;\r
875\r
766f4bc1 876#pragma pack()\r
877\r
a7ed1e2e 878#endif\r
EFI Development Kit II mirror for PVE