]> git.proxmox.com Git - mirror_edk2.git/blame - MdePkg/Include/IndustryStandard/PciExpress21.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MdePkg: Fix incorrect PCIe Extended Capabilities definition
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / PciExpress21.h
CommitLineData
533403e6 1/** @file\r
2 Support for the latest PCI standard.\r
3\r
a1d20250 4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
0a38a95a 5 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r
9df063a0 6 This program and the accompanying materials \r
533403e6 7 are licensed and made available under the terms and conditions of the BSD License \r
8 which accompanies this distribution. The full text of the license may be found at \r
9 http://opensource.org/licenses/bsd-license.php \r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
13\r
14**/\r
15\r
16#ifndef _PCIEXPRESS21_H_\r
17#define _PCIEXPRESS21_H_\r
18\r
19#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r
20#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r
21#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r
22#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r
23#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r
24#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r
25\r
26//\r
27// for SR-IOV\r
28//\r
29#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r
30#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r
31#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r
32#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r
33\r
34typedef struct {\r
35 UINT32 CapabilityHeader;\r
36 UINT32 Capability;\r
37 UINT16 Control;\r
38 UINT16 Status;\r
39 UINT16 InitialVFs;\r
40 UINT16 TotalVFs;\r
41 UINT16 NumVFs;\r
42 UINT8 FunctionDependencyLink;\r
43 UINT8 Reserved0;\r
44 UINT16 FirstVFOffset;\r
45 UINT16 VFStride;\r
46 UINT16 Reserved1;\r
47 UINT16 VFDeviceID;\r
48 UINT32 SupportedPageSize;\r
49 UINT32 SystemPageSize;\r
50 UINT32 VFBar[6];\r
51 UINT32 VFMigrationStateArrayOffset;\r
52} SR_IOV_CAPABILITY_REGISTER;\r
53\r
54#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r
55#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r
56#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r
57#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r
58#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r
59#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r
60#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r
61#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r
62#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r
63#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r
64#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r
65#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r
66#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r
67#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r
68#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r
69#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r
70#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r
71#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r
72#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r
73\r
a1d20250
JC		 74typedef struct {\r
75 UINT32 CapabilityId:16;\r
76 UINT32 CapabilityVersion:4;\r
77 UINT32 NextCapabilityOffset:12;\r
78} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\r
79\r
80#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r
81\r
82#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r
83#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
84#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
85\r
86typedef struct {\r
87 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
88 UINT32 UncorrectableErrorStatus;\r
89 UINT32 UncorrectableErrorMask;\r
90 UINT32 UncorrectableErrorSeverity;\r
91 UINT32 CorrectableErrorStatus;\r
92 UINT32 CorrectableErrorMask;\r
93 UINT32 AdvancedErrorCapabilitiesAndControl;\r
0a38a95a 94 UINT32 HeaderLog[4];\r
a1d20250
JC		 95 UINT32 RootErrorCommand;\r
96 UINT32 RootErrorStatus;\r
97 UINT16 ErrorSourceIdentification;\r
98 UINT16 CorrectableErrorSourceIdentification;\r
99 UINT32 TlpPrefixLog[4];\r
100} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\r
101\r
102#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\r
103#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009\r
104#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\r
105\r
106typedef struct {\r
107 UINT32 VcResourceCapability:24;\r
108 UINT32 PortArbTableOffset:8;\r
109 UINT32 VcResourceControl;\r
110 UINT16 Reserved1;\r
111 UINT16 VcResourceStatus;\r
112} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\r
113\r
114typedef struct {\r
115 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
116 UINT32 ExtendedVcCount:3;\r
117 UINT32 PortVcCapability1:29;\r
118 UINT32 PortVcCapability2:24;\r
119 UINT32 VcArbTableOffset:8;\r
120 UINT16 PortVcControl;\r
121 UINT16 PortVcStatus;\r
122 PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r
123} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\r
124\r
125#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\r
126#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\r
127\r
128typedef struct {\r
129 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
130 UINT64 SerialNumber;\r
131} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\r
132\r
133#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r
134#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r
135\r
136typedef struct {\r
137 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
138 UINT32 ElementSelfDescription;\r
139 UINT32 Reserved;\r
140 UINT32 LinkEntry[1];\r
141} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\r
142\r
143#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r
144\r
145#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r
146#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r
147\r
148typedef struct {\r
149 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
150 UINT32 RootComplexLinkCapabilities;\r
151 UINT16 RootComplexLinkControl;\r
152 UINT16 RootComplexLinkStatus;\r
153} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\r
154\r
155#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r
156#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r
157\r
158typedef struct {\r
159 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
160 UINT32 DataSelect:8;\r
161 UINT32 Reserved:24;\r
162 UINT32 Data;\r
163 UINT32 PowerBudgetCapability:1;\r
164 UINT32 Reserved2:7;\r
165 UINT32 Reserved3:24;\r
166} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\r
167\r
168#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r
169#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r
170\r
171typedef struct {\r
172 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
173 UINT16 AcsCapability;\r
174 UINT16 AcsControl;\r
175 UINT8 EgressControlVectorArray[1];\r
176} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\r
177\r
178#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r
179#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r
180\r
181#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r
182#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r
183\r
184typedef struct {\r
185 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
186 UINT32 AssociationBitmap;\r
187} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\r
188\r
189#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\r
190#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1\r
191\r
192typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\r
193\r
194#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r
195#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r
196\r
197typedef struct {\r
198 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
199 UINT32 VendorSpecificHeader;\r
200 UINT8 VendorSpecific[1];\r
201} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\r
202\r
203#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r
204\r
205#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r
206#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r
207\r
208typedef struct {\r
209 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
210 UINT16 VendorId;\r
211 UINT16 DeviceId;\r
212 UINT32 RcrbCapabilities;\r
213 UINT32 RcrbControl;\r
214 UINT32 Reserved;\r
215} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\r
216\r
217#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r
218#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r
219\r
220typedef struct {\r
221 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
222 UINT16 MultiCastCapability;\r
223 UINT16 MulticastControl;\r
224 UINT64 McBaseAddress;\r
225 UINT64 McReceiveAddress;\r
226 UINT64 McBlockAll;\r
227 UINT64 McBlockUntranslated;\r
228 UINT64 McOverlayBar;\r
229} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\r
230\r
231#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\r
232#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1\r
233\r
234typedef struct {\r
235 UINT32 ResizableBarCapability;\r
236 UINT16 ResizableBarControl;\r
237 UINT16 Reserved;\r
238} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\r
239\r
240typedef struct {\r
241 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
242 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r
243} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\r
244\r
e1c9edd6
JC		 245#define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)\r
246\r
a1d20250
JC		 247#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\r
248#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\r
249\r
250typedef struct {\r
251 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
252 UINT16 AriCapability;\r
253 UINT16 AriControl;\r
254} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\r
255\r
256#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\r
257#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\r
258\r
259typedef struct {\r
260 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
261 UINT32 DpaCapability;\r
262 UINT32 DpaLatencyIndicator;\r
263 UINT16 DpaStatus;\r
264 UINT16 DpaControl;\r
265 UINT8 DpaPowerAllocationArray[1];\r
266} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\r
267\r
268#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r
269\r
270\r
271#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\r
272#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\r
273\r
274typedef struct {\r
275 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
276 UINT16 MaxSnoopLatency;\r
277 UINT16 MaxNoSnoopLatency;\r
278} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\r
279\r
280#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\r
281#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\r
282\r
283typedef struct {\r
284 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
285 UINT32 TphRequesterCapability;\r
286 UINT32 TphRequesterControl;\r
287 UINT16 TphStTable[1];\r
288} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\r
289\r
e1c9edd6
JC		 290#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
291\r
533403e6 292#endif\r
EFI Development Kit II mirror for PVE