[mirror_edk2.git] / MdePkg / Include / IndustryStandard / PciExpress40.h

/** @file\r
Support for the PCI Express 4.0 standard.\r
\r
This header file may not define all structures.  Please extend as required.\r
\r
Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>\r
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _PCIEXPRESS40_H_\r
#define _PCIEXPRESS40_H_\r
\r
#include <IndustryStandard/PciExpress31.h>\r
\r
#pragma pack(1)\r
\r
/// The Physical Layer PCI Express Extended Capability definitions.\r
///\r
/// Based on section 7.7.5 of PCI Express Base Specification 4.0.\r
///@{\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID    0x0026\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1  0x1\r
\r
// Register offsets from Physical Layer PCI-E Ext Cap Header\r
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET                       0x04\r
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET                            0x08\r
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET                             0x0C\r
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET           0x10\r
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET   0x14\r
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET  0x18\r
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET          0x20\r
\r
typedef union {\r
  struct {\r
    UINT32    Reserved : 32;               // Reserved bit 0:31\r
  } Bits;\r
  UINT32    Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\r
\r
typedef union {\r
  struct {\r
    UINT32    Reserved : 32;               // Reserved bit 0:31\r
  } Bits;\r
  UINT32    Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\r
\r
typedef union {\r
  struct {\r
    UINT32    EqualizationComplete      : 1;  // bit 0\r
    UINT32    EqualizationPhase1Success : 1;  // bit 1\r
    UINT32    EqualizationPhase2Success : 1;  // bit 2\r
    UINT32    EqualizationPhase3Success : 1;  // bit 3\r
    UINT32    LinkEqualizationRequest   : 1;  // bit 4\r
    UINT32    Reserved                  : 27; // Reserved bit 5:31\r
  } Bits;\r
  UINT32    Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\r
\r
typedef union {\r
  struct {\r
    UINT8    DownstreamPortTransmitterPreset : 4; // bit 0..3\r
    UINT8    UpstreamPortTransmitterPreset   : 4; // bit 4..7\r
  } Bits;\r
  UINT8    Uint8;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\r
\r
typedef struct {\r
  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                         Header;\r
  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES                 Capablities;\r
  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL                      Control;\r
  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS                       Status;\r
  UINT32                                                           LocalDataParityMismatchStatus;\r
  UINT32                                                           FirstRetimerDataParityMismatchStatus;\r
  UINT32                                                           SecondRetimerDataParityMismatchStatus;\r
  UINT32                                                           Reserved;\r
  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL    LaneEqualizationControl[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\r
///@}\r
\r
/// The Designated Vendor Specific Capability definitions\r
/// Based on section 7.9.6 of PCI Express Base Specification 4.0.\r
///@{\r
typedef union {\r
  struct {\r
    UINT32    DvsecVendorId : 16;                                     // bit 0..15\r
    UINT32    DvsecRevision : 4;                                      // bit 16..19\r
    UINT32    DvsecLength   : 12;                                     // bit 20..31\r
  } Bits;\r
  UINT32    Uint32;\r
} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;\r
\r
typedef union {\r
  struct {\r
    UINT16    DvsecId : 16;                                           // bit 0..15\r
  } Bits;\r
  UINT16    Uint16;\r
} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;\r
\r
typedef struct {\r
  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER           Header;\r
  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1    DesignatedVendorSpecificHeader1;\r
  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2    DesignatedVendorSpecificHeader2;\r
  UINT8                                              DesignatedVendorSpecific[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;\r
///@}\r
\r
#pragma pack()\r
\r
#endif\r
Commit	Line	Data
8805bd90 FP	1	/** @file\r
	2	Support for the PCI Express 4.0 standard.\r
	3	\r
	4	This header file may not define all structures. Please extend as required.\r
	5	\r
	6	Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>\r
1b6b4a83	7	Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
9344f092	8	SPDX-License-Identifier: BSD-2-Clause-Patent\r
8805bd90 FP	9	\r
	10	**/\r
	11	\r
	12	#ifndef _PCIEXPRESS40_H_\r
	13	#define _PCIEXPRESS40_H_\r
	14	\r
	15	#include <IndustryStandard/PciExpress31.h>\r
	16	\r
	17	#pragma pack(1)\r
	18	\r
	19	/// The Physical Layer PCI Express Extended Capability definitions.\r
	20	///\r
	21	/// Based on section 7.7.5 of PCI Express Base Specification 4.0.\r
	22	///@{\r
	23	#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026\r
	24	#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1\r
	25	\r
	26	// Register offsets from Physical Layer PCI-E Ext Cap Header\r
2f88bd3a MK	27	#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04\r
	28	#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08\r
	29	#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C\r
	30	#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10\r
	31	#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14\r
	32	#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18\r
	33	#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r
8805bd90 FP	34	\r
	35	typedef union {\r
	36	struct {\r
2f88bd3a	37	UINT32 Reserved : 32; // Reserved bit 0:31\r
8805bd90	38	} Bits;\r
2f88bd3a	39	UINT32 Uint32;\r
8805bd90 FP	40	} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\r
	41	\r
	42	typedef union {\r
	43	struct {\r
2f88bd3a	44	UINT32 Reserved : 32; // Reserved bit 0:31\r
8805bd90	45	} Bits;\r
2f88bd3a	46	UINT32 Uint32;\r
8805bd90 FP	47	} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\r
	48	\r
	49	typedef union {\r
	50	struct {\r
2f88bd3a MK	51	UINT32 EqualizationComplete : 1; // bit 0\r
	52	UINT32 EqualizationPhase1Success : 1; // bit 1\r
	53	UINT32 EqualizationPhase2Success : 1; // bit 2\r
	54	UINT32 EqualizationPhase3Success : 1; // bit 3\r
	55	UINT32 LinkEqualizationRequest : 1; // bit 4\r
	56	UINT32 Reserved : 27; // Reserved bit 5:31\r
8805bd90	57	} Bits;\r
2f88bd3a	58	UINT32 Uint32;\r
8805bd90 FP	59	} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\r
	60	\r
	61	typedef union {\r
	62	struct {\r
2f88bd3a MK	63	UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3\r
2f88bd3a MK	64	UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7\r
8805bd90	65	} Bits;\r
2f88bd3a	66	UINT8 Uint8;\r
8805bd90 FP	67	} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\r
	68	\r
	69	typedef struct {\r
2f88bd3a MK	70	PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
	71	PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;\r
	72	PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;\r
	73	PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;\r
	74	UINT32 LocalDataParityMismatchStatus;\r
	75	UINT32 FirstRetimerDataParityMismatchStatus;\r
	76	UINT32 SecondRetimerDataParityMismatchStatus;\r
	77	UINT32 Reserved;\r
	78	PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
8805bd90 FP	79	} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\r
	80	///@}\r
	81	\r
1b6b4a83 JA	82	/// The Designated Vendor Specific Capability definitions\r
	83	/// Based on section 7.9.6 of PCI Express Base Specification 4.0.\r
	84	///@{\r
	85	typedef union {\r
	86	struct {\r
2f88bd3a MK	87	UINT32 DvsecVendorId : 16; // bit 0..15\r
	88	UINT32 DvsecRevision : 4; // bit 16..19\r
	89	UINT32 DvsecLength : 12; // bit 20..31\r
	90	} Bits;\r
	91	UINT32 Uint32;\r
	92	} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;\r
1b6b4a83 JA	93	\r
	94	typedef union {\r
	95	struct {\r
2f88bd3a MK	96	UINT16 DvsecId : 16; // bit 0..15\r
	97	} Bits;\r
	98	UINT16 Uint16;\r
	99	} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;\r
1b6b4a83 JA	100	\r
1b6b4a83 JA	101	typedef struct {\r
2f88bd3a MK	102	PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
	103	PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;\r
	104	PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;\r
	105	UINT8 DesignatedVendorSpecific[1];\r
	106	} PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;\r
1b6b4a83 JA	107	///@}\r
1b6b4a83 JA	108	\r
8805bd90 FP	109	#pragma pack()\r
	110	\r
	111	#endif\r