projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 8805bd90 FP |
1 | /** @file\r |
| 2 | Support for the PCI Express 4.0 standard.\r | |
| 3 | \r | |
| 4 | This header file may not define all structures. Please extend as required.\r | |
| 5 | \r | |
| 6 | Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>\r | |
| 9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 8805bd90 FP |
8 | \r |
| 9 | **/\r | |
| 10 | \r | |
| 11 | #ifndef _PCIEXPRESS40_H_\r | |
| 12 | #define _PCIEXPRESS40_H_\r | |
| 13 | \r | |
| 14 | #include <IndustryStandard/PciExpress31.h>\r | |
| 15 | \r | |
| 16 | #pragma pack(1)\r | |
| 17 | \r | |
| 18 | /// The Physical Layer PCI Express Extended Capability definitions.\r | |
| 19 | ///\r | |
| 20 | /// Based on section 7.7.5 of PCI Express Base Specification 4.0.\r | |
| 21 | ///@{\r | |
| 22 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026\r | |
| 23 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1\r | |
| 24 | \r | |
| 25 | // Register offsets from Physical Layer PCI-E Ext Cap Header\r | |
| 26 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04\r | |
| 27 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08\r | |
| 28 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C\r | |
| 29 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10\r | |
| 30 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14\r | |
| 31 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18\r | |
| 32 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r | |
| 33 | \r | |
| 34 | typedef union {\r | |
| 35 | struct {\r | |
| 36 | UINT32 Reserved : 32; // Reserved bit 0:31\r | |
| 37 | } Bits;\r | |
| 38 | UINT32 Uint32;\r | |
| 39 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\r | |
| 40 | \r | |
| 41 | typedef union {\r | |
| 42 | struct {\r | |
| 43 | UINT32 Reserved : 32; // Reserved bit 0:31\r | |
| 44 | } Bits;\r | |
| 45 | UINT32 Uint32;\r | |
| 46 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\r | |
| 47 | \r | |
| 48 | typedef union {\r | |
| 49 | struct {\r | |
| 50 | UINT32 EqualizationComplete : 1; // bit 0\r | |
| 51 | UINT32 EqualizationPhase1Success : 1; // bit 1\r | |
| 52 | UINT32 EqualizationPhase2Success : 1; // bit 2\r | |
| 53 | UINT32 EqualizationPhase3Success : 1; // bit 3\r | |
| 54 | UINT32 LinkEqualizationRequest : 1; // bit 4\r | |
| 55 | UINT32 Reserved : 27; // Reserved bit 5:31\r | |
| 56 | } Bits;\r | |
| 57 | UINT32 Uint32;\r | |
| 58 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\r | |
| 59 | \r | |
| 60 | typedef union {\r | |
| 61 | struct {\r | |
| 62 | UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3\r | |
| 63 | UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7\r | |
| 64 | } Bits;\r | |
| 65 | UINT8 Uint8;\r | |
| 66 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\r | |
| 67 | \r | |
| 68 | typedef struct {\r | |
| 69 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
| 70 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;\r | |
| 71 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;\r | |
| 72 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;\r | |
| 73 | UINT32 LocalDataParityMismatchStatus;\r | |
| 74 | UINT32 FirstRetimerDataParityMismatchStatus;\r | |
| 75 | UINT32 SecondRetimerDataParityMismatchStatus;\r | |
| 76 | UINT32 Reserved;\r | |
| 77 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r | |
| 78 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\r | |
| 79 | ///@}\r | |
| 80 | \r | |
| 81 | #pragma pack()\r | |
| 82 | \r | |
| 83 | #endif\r |